Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044972
F. Borghetti, N. Massari, D. Stoppa, A. Adami, L. Lorenzelli, F. Maloberti
In this paper a readout circuit for label-free DNA detection based on piezo-resistive MEMS cantilevers is presented. The circuit is designed to have high sensitivity and a precise calibration block in order to deal with possible large variation of the cantilever resistance due to technological mismatch effects. The readout channel has been electrically tested showing, as preliminary results, a total differential dynamic range of 35dB with 15μV as best input resolution, a static offset compensation of about 78dB and a common-mode rejection of about 58dB with about 2.2% of linearity, which demonstrates the suitability of the proposed architecture for the target application. The chip consumes about 10mW from a 3.3V power supply, while the area occupation is of about 1.05mm2 (pad excluded).
{"title":"An analog readout circuit with offset calibration for cantiliver-based DNA detection","authors":"F. Borghetti, N. Massari, D. Stoppa, A. Adami, L. Lorenzelli, F. Maloberti","doi":"10.1109/ESSCIRC.2011.6044972","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044972","url":null,"abstract":"In this paper a readout circuit for label-free DNA detection based on piezo-resistive MEMS cantilevers is presented. The circuit is designed to have high sensitivity and a precise calibration block in order to deal with possible large variation of the cantilever resistance due to technological mismatch effects. The readout channel has been electrically tested showing, as preliminary results, a total differential dynamic range of 35dB with 15μV as best input resolution, a static offset compensation of about 78dB and a common-mode rejection of about 58dB with about 2.2% of linearity, which demonstrates the suitability of the proposed architecture for the target application. The chip consumes about 10mW from a 3.3V power supply, while the area occupation is of about 1.05mm2 (pad excluded).","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132452587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044925
P. Harpe, Cui Zhou, K. Philips, H. D. Groot
This paper presents a low-power fast-startup wideband VGA with a 6th-order low-pass filter function for UWB radios. A DC-coupled 6-stage open-loop topology is proposed, which includes DC offset calibration and fast-startup biasing circuits. The prototype in 90nm CMOS occupies only 0.075mm2, including decoupling capacitors and digital interfacing. The circuit consumes 1.6mW from a 1V supply, achieves −1.2dB up to 37.7dB gain with a programmable bandwidth from 80MHz to 460MHz, and achieves a startup-time of 12ns.
{"title":"A 1.6mW 0.5GHz open-loop VGA with fast startup and offset calibration for UWB radios","authors":"P. Harpe, Cui Zhou, K. Philips, H. D. Groot","doi":"10.1109/ESSCIRC.2011.6044925","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044925","url":null,"abstract":"This paper presents a low-power fast-startup wideband VGA with a 6th-order low-pass filter function for UWB radios. A DC-coupled 6-stage open-loop topology is proposed, which includes DC offset calibration and fast-startup biasing circuits. The prototype in 90nm CMOS occupies only 0.075mm2, including decoupling capacitors and digital interfacing. The circuit consumes 1.6mW from a 1V supply, achieves −1.2dB up to 37.7dB gain with a programmable bandwidth from 80MHz to 460MHz, and achieves a startup-time of 12ns.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133522891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044980
Sunghyuk Lee, A. Chandrakasan, Hae-Seung Lee
A voltage scalable zero-crossing based (ZCB) pipelined ADC is built in 65nm GP (general purpose) CMOS process and LP (low power) CMOS process. The highly digital implementation characteristic of the zero-crossing based circuit technique enables energy efficient operation and supply voltage scaling. A unidirectional coarse-fine charge transfer scheme is developed to allow low-voltage operation as well as high speed and high resolution. At 1.0V(GP) / 1.2V(LP) nominal supply and 50MS/s, the ADC achieves 67.7dB(GP) / 68.1dB(LP) SNDR after calibration while dissipating 4.07mW(GP) / 4.93mW(LP), resulting in an FOM of 41.0fJ/step(GP) / 47.5fJ/step(LP). The supply voltage scalability is demonstrated down to 0.5V(GP) / 0.8V(LP) and improves the FOM to 28.0fJ/step(GP) / 37.8fJ/step(LP), while maintaining higher than 66dB SNDR.
{"title":"A 12b 5-to-50MS/s 0.5-to-1V voltage scalable zero-crossing based pipelined ADC","authors":"Sunghyuk Lee, A. Chandrakasan, Hae-Seung Lee","doi":"10.1109/ESSCIRC.2011.6044980","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044980","url":null,"abstract":"A voltage scalable zero-crossing based (ZCB) pipelined ADC is built in 65nm GP (general purpose) CMOS process and LP (low power) CMOS process. The highly digital implementation characteristic of the zero-crossing based circuit technique enables energy efficient operation and supply voltage scaling. A unidirectional coarse-fine charge transfer scheme is developed to allow low-voltage operation as well as high speed and high resolution. At 1.0V(GP) / 1.2V(LP) nominal supply and 50MS/s, the ADC achieves 67.7dB(GP) / 68.1dB(LP) SNDR after calibration while dissipating 4.07mW(GP) / 4.93mW(LP), resulting in an FOM of 41.0fJ/step(GP) / 47.5fJ/step(LP). The supply voltage scalability is demonstrated down to 0.5V(GP) / 0.8V(LP) and improves the FOM to 28.0fJ/step(GP) / 37.8fJ/step(LP), while maintaining higher than 66dB SNDR.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114340751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044895
Jinmyoung Kim, T. Nakura, H. Takata, K. Ishibashi, M. Ikeda, K. Asada
Switched parasitic capacitors of sleep blocks with a tri-mode power gating structure are implemented to reduce on-chip resonant supply noise in 65nm CMOS process. The proposed method achieves 46.9% and 57.9% noise reduction for wake-up noise and 130MHz periodic supply noise, respectively. The proposed method also realizes without discharging time before noise cancelling, and shows a 8.4× boost of effective capacitance value with 2.1% chip area overhead. To apply the proposed switched parasitic capacitors of sleep blocks for reducing resonant supply noise, we can save chip area for noise reduction more effectively.
{"title":"On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure","authors":"Jinmyoung Kim, T. Nakura, H. Takata, K. Ishibashi, M. Ikeda, K. Asada","doi":"10.1109/ESSCIRC.2011.6044895","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044895","url":null,"abstract":"Switched parasitic capacitors of sleep blocks with a tri-mode power gating structure are implemented to reduce on-chip resonant supply noise in 65nm CMOS process. The proposed method achieves 46.9% and 57.9% noise reduction for wake-up noise and 130MHz periodic supply noise, respectively. The proposed method also realizes without discharging time before noise cancelling, and shows a 8.4× boost of effective capacitance value with 2.1% chip area overhead. To apply the proposed switched parasitic capacitors of sleep blocks for reducing resonant supply noise, we can save chip area for noise reduction more effectively.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114523416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044920
A. Agarwal, S. Hsu, S. Mathew, M. Anders, Himanshu Kaul, F. Sheikh, R. Krishnamurthy
A 128-entry × 128b content addressable memory (CAM) design enables 145ps search operation in 1.0V, 32nm high-k metal-gate CMOS technology. A high-speed 16b wide dynamic AND match-line, combined with a fully static search-line and swapped XOR CAM cell simulations show a 49% reduction of search energy at iso-search delay of 145ps over an optimized high-performance conventional NOR-type CAM design, enabling 1.07fJ/bit/search operation. Scaling the supply voltage of the proposed CAM enables 0.3fJ/bit/search with 1.07ns search delay at 0.5V.
{"title":"A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOS","authors":"A. Agarwal, S. Hsu, S. Mathew, M. Anders, Himanshu Kaul, F. Sheikh, R. Krishnamurthy","doi":"10.1109/ESSCIRC.2011.6044920","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044920","url":null,"abstract":"A 128-entry × 128b content addressable memory (CAM) design enables 145ps search operation in 1.0V, 32nm high-k metal-gate CMOS technology. A high-speed 16b wide dynamic AND match-line, combined with a fully static search-line and swapped XOR CAM cell simulations show a 49% reduction of search energy at iso-search delay of 145ps over an optimized high-performance conventional NOR-type CAM design, enabling 1.07fJ/bit/search operation. Scaling the supply voltage of the proposed CAM enables 0.3fJ/bit/search with 1.07ns search delay at 0.5V.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133697848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044974
I. Triantis, A. Demosthenous, M. Rahal, H. Hong, R. Bayford
This paper presents an integrated circuit for the measurement of tissue impedances. The circuit will be part of a wearable electrical impedance tomography based imaging system intended to be used for neonate lung function monitoring in intensive care units. The ASIC is designed to measure the real and imaginary parts of tissue impedances at two different frequencies simultaneously. It includes both circuitry for current injection and impedance measurement. The readout part employs synchronous chopping detection. The ASIC was fabricated in a 0.6-μm CMOS technology, occupies a core area of 4.5 mm2 and dissipates about 10 mW from ±2.5 V power supplies. It has wideband frequency operation, from DC to about 1 MHz, and a measurement accuracy of less than 1 Ω.
{"title":"A multi-frequency bioimpedance measurement ASIC for electrical impedance tomography","authors":"I. Triantis, A. Demosthenous, M. Rahal, H. Hong, R. Bayford","doi":"10.1109/ESSCIRC.2011.6044974","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044974","url":null,"abstract":"This paper presents an integrated circuit for the measurement of tissue impedances. The circuit will be part of a wearable electrical impedance tomography based imaging system intended to be used for neonate lung function monitoring in intensive care units. The ASIC is designed to measure the real and imaginary parts of tissue impedances at two different frequencies simultaneously. It includes both circuitry for current injection and impedance measurement. The readout part employs synchronous chopping detection. The ASIC was fabricated in a 0.6-μm CMOS technology, occupies a core area of 4.5 mm2 and dissipates about 10 mW from ±2.5 V power supplies. It has wideband frequency operation, from DC to about 1 MHz, and a measurement accuracy of less than 1 Ω.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"218 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133570830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044914
A. Seabaugh
The tunnel field-effect transistor (TFET) utilizes a metal-oxide-semiconductor MOS structure to control the Zener tunneling current in a p+n+ junction. Current understanding and status in the development of TFETs with steep inverse-subthreshold-slope is reviewed.
{"title":"Fundamentals and current status of steep-slope tunnel field-effect transistors","authors":"A. Seabaugh","doi":"10.1109/ESSCIRC.2011.6044914","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044914","url":null,"abstract":"The tunnel field-effect transistor (TFET) utilizes a metal-oxide-semiconductor MOS structure to control the Zener tunneling current in a p+n+ junction. Current understanding and status in the development of TFETs with steep inverse-subthreshold-slope is reviewed.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"38 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130606477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044915
T. Ueda, Tsuyoshi Tanaka, D. Ueda
In this paper, we review the recent advances of GaN power switching and RF transistors developed at Panasonic. The presented devices are formed on cost effective Si substrates, which are very promising for the future mass production contributing to the reduction of the total fabrication cost. We develop the epitaxial growth technology using metal organic chemical vapor deposition (MOCVD) over 6-inch Si substrates by novel buffer layers relaxing the stress caused by the lattice and the thermal mismatches. Aiming at the power switching applications, we propose a new device structure called Gate Injection Transistor (GIT) for strongly desired normally-off operation together with low on-state resistances. The GITs are applied for an inverter to drive a motor which exhibits high operating efficiencies. Further increase of the breakdown voltages up to 2200V on Si is achieved by a novel Blocking Voltage Boosting (BVB) structure which prevents the inversion elections at the AlN/Si flowing at the periphery of the chips. As for the RF devices, we present 203W output power at 2.5GHz and 10.7W at 26.5GHz by AlGaN/GaN devices on Si. These GaN-based switching and RF power devices on Si substrates are very promising for a variety of applications taking advantages of their inherent low cost with superior performances.
{"title":"Current status on GaN-based RF-power devices","authors":"T. Ueda, Tsuyoshi Tanaka, D. Ueda","doi":"10.1109/ESSCIRC.2011.6044915","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044915","url":null,"abstract":"In this paper, we review the recent advances of GaN power switching and RF transistors developed at Panasonic. The presented devices are formed on cost effective Si substrates, which are very promising for the future mass production contributing to the reduction of the total fabrication cost. We develop the epitaxial growth technology using metal organic chemical vapor deposition (MOCVD) over 6-inch Si substrates by novel buffer layers relaxing the stress caused by the lattice and the thermal mismatches. Aiming at the power switching applications, we propose a new device structure called Gate Injection Transistor (GIT) for strongly desired normally-off operation together with low on-state resistances. The GITs are applied for an inverter to drive a motor which exhibits high operating efficiencies. Further increase of the breakdown voltages up to 2200V on Si is achieved by a novel Blocking Voltage Boosting (BVB) structure which prevents the inversion elections at the AlN/Si flowing at the periphery of the chips. As for the RF devices, we present 203W output power at 2.5GHz and 10.7W at 26.5GHz by AlGaN/GaN devices on Si. These GaN-based switching and RF power devices on Si substrates are very promising for a variety of applications taking advantages of their inherent low cost with superior performances.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116755556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044921
M. Berkhout, Lutsen Dooper
In this paper a class-D audio amplifier for mobile applications is presented realized in a 0.14μm CMOS technology tailored for mobile applications. The amplifier has a simple PDM-based digital interface that requires only two pins and enables assembly n 9-bump WL-CSP. A reconfigurable ate driver is used that reduces quiescent current consumption and radiated emission.
{"title":"A 3.4W digital-in class-D audio amplifier","authors":"M. Berkhout, Lutsen Dooper","doi":"10.1109/ESSCIRC.2011.6044921","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044921","url":null,"abstract":"In this paper a class-D audio amplifier for mobile applications is presented realized in a 0.14μm CMOS technology tailored for mobile applications. The amplifier has a simple PDM-based digital interface that requires only two pins and enables assembly n 9-bump WL-CSP. A reconfigurable ate driver is used that reduces quiescent current consumption and radiated emission.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123433370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044932
Mahdi Kashmiri, K. Souri, K. Makinwa
A 16MHz frequency reference that exploits the well-defined thermal diffusivity of IC-grade silicon is presented. The reference is realized in a 0.16μm baseline CMOS process. Occupying 0.5mm2, its absolute inaccuracy after a room temperature trim is ±0.1% from −55°C to 125°C (24 samples). Its cycle-to-cycle jitter is less than 45ps (rms), and it dissipates 2.1mW from a 1.8V supply. Compared to a previous design in a 0.7μm CMOS process, this work achieves 10× higher frequency, 7× less jitter, 3.7× less power, and 12× less chip area, while maintaining the same accuracy. This demonstrates that thermal-diffusivity-based frequency references benefit strongly from technology scaling.
{"title":"A scaled thermal-diffusivity-based frequency reference in 0.16μm CMOS","authors":"Mahdi Kashmiri, K. Souri, K. Makinwa","doi":"10.1109/ESSCIRC.2011.6044932","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044932","url":null,"abstract":"A 16MHz frequency reference that exploits the well-defined thermal diffusivity of IC-grade silicon is presented. The reference is realized in a 0.16μm baseline CMOS process. Occupying 0.5mm<sup>2</sup>, its absolute inaccuracy after a room temperature trim is ±0.1% from −55°C to 125°C (24 samples). Its cycle-to-cycle jitter is less than 45ps (rms), and it dissipates 2.1mW from a 1.8V supply. Compared to a previous design in a 0.7μm CMOS process, this work achieves 10× higher frequency, 7× less jitter, 3.7× less power, and 12× less chip area, while maintaining the same accuracy. This demonstrates that thermal-diffusivity-based frequency references benefit strongly from technology scaling.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122383347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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