Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250045
E. Gad, M. Nakhla
A new algorithm is presented for sensitivity analysis of nonuniform multi-conductor transmission lines in the presence of nonlinear terminations. The algorithm is based on model-order reduction using integrated congruence transform. The proposed algorithm does not require partitioning the nonuniform line into cascaded connections of uniform sections. In addition, sensitivity information are obtained from solving a reduced-order system, which provides significant computational savings.
{"title":"Simulation and sensitivity computation of nonuniform transmission lines via integrated congruence transform","authors":"E. Gad, M. Nakhla","doi":"10.1109/EPEP.2003.1250045","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250045","url":null,"abstract":"A new algorithm is presented for sensitivity analysis of nonuniform multi-conductor transmission lines in the presence of nonlinear terminations. The algorithm is based on model-order reduction using integrated congruence transform. The proposed algorithm does not require partitioning the nonuniform line into cascaded connections of uniform sections. In addition, sensitivity information are obtained from solving a reduced-order system, which provides significant computational savings.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133144409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250001
C. Schuster, D. Kuchta, E. Colgan, G. Cohen, J. Trewhella
In this paper the electrical package design for a 10 Gbps laser diode on a silicon optical bench will be presented. Specifically the wideband impedance matching is addressed. Simulated data will be compared to measurements.
{"title":"Package design and measurement of 10 Gbps laser diode on high-speed silicon optical bench","authors":"C. Schuster, D. Kuchta, E. Colgan, G. Cohen, J. Trewhella","doi":"10.1109/EPEP.2003.1250001","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250001","url":null,"abstract":"In this paper the electrical package design for a 10 Gbps laser diode on a silicon optical bench will be presented. Specifically the wideband impedance matching is addressed. Simulated data will be compared to measurements.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133402964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250068
B. Rubin
In moment-method codes, accurate representation of signal return current usually requires that the basis function in the signal line be projected into the reference planes; this way the return current can closely follow the same path as the signal line. A technique is described that efficiently assures highly accurate return current without the need for such projection. Examples from inductive and full wave modeling of appropriate structures are presented and discussed.
{"title":"Using shadow lines to assure accurate signal return current in electrical package analysis codes","authors":"B. Rubin","doi":"10.1109/EPEP.2003.1250068","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250068","url":null,"abstract":"In moment-method codes, accurate representation of signal return current usually requires that the basis function in the signal line be projected into the reference planes; this way the return current can closely follow the same path as the signal line. A technique is described that efficiently assures highly accurate return current without the need for such projection. Examples from inductive and full wave modeling of appropriate structures are presented and discussed.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116094769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250006
C. Ong, A. Tripathi, D. Miller, Leung Tsang
A novel approximate method for de-embedding probing structures using just the symmetric thru' line calibration structure is described. The method involves application of a de-convolution technique based on the layer-peeling algorithm to construct an equivalent circuit model using cascaded sections of transmission lines for half of the thru' structure from TDR (time-domain reflectometry) measurements. The non-ideal step input waveform of the TDR, obtained through measuring an open-circuited load, is used to correct for the errors inherent in the layer-peeling algorithm due to the assumed ideal step excitation. A comparison of the results of the proposed method is made with that of TRL and SOLT to validate the method. Also illustrated is the applicability of this technique to SMA (surface-mounted-adapter) based probing structures on printed circuit boards (PCBs), where the standard reference calibration structures are generally not available.
{"title":"De-embedding a device-under-test (DUT) using thru' measurements","authors":"C. Ong, A. Tripathi, D. Miller, Leung Tsang","doi":"10.1109/EPEP.2003.1250006","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250006","url":null,"abstract":"A novel approximate method for de-embedding probing structures using just the symmetric thru' line calibration structure is described. The method involves application of a de-convolution technique based on the layer-peeling algorithm to construct an equivalent circuit model using cascaded sections of transmission lines for half of the thru' structure from TDR (time-domain reflectometry) measurements. The non-ideal step input waveform of the TDR, obtained through measuring an open-circuited load, is used to correct for the errors inherent in the layer-peeling algorithm due to the assumed ideal step excitation. A comparison of the results of the proposed method is made with that of TRL and SOLT to validate the method. Also illustrated is the applicability of this technique to SMA (surface-mounted-adapter) based probing structures on printed circuit boards (PCBs), where the standard reference calibration structures are generally not available.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116179428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250017
G. Ji, T. Arabi, G. Taylor
In high performance microprocessors, power supply noise needs to be controlled to ensure reliable high speed bus operation. This is generally done with high quality package capacitors. These capacitors are generally lower equivalent series inductance (ESL) and lower equivalent series resistor (ESR). Contrary to the traditional approach, we will show that a small ESR is not optimal. We will present a novel approach of using an on-die resistor in series with the package capacitance to dampen the high frequency noise. We will show by validation on the 90nm technology that this technique is capable of reducing the noise by nearly 80% without adversely affecting the timings.
{"title":"Design and validation of a power supply noise reduction technique","authors":"G. Ji, T. Arabi, G. Taylor","doi":"10.1109/EPEP.2003.1250017","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250017","url":null,"abstract":"In high performance microprocessors, power supply noise needs to be controlled to ensure reliable high speed bus operation. This is generally done with high quality package capacitors. These capacitors are generally lower equivalent series inductance (ESL) and lower equivalent series resistor (ESR). Contrary to the traditional approach, we will show that a small ESR is not optimal. We will present a novel approach of using an on-die resistor in series with the package capacitance to dampen the high frequency noise. We will show by validation on the 90nm technology that this technique is capable of reducing the noise by nearly 80% without adversely affecting the timings.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"28 23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116604002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250034
W. Beyene, N. Cheng, C. Yuan
The further scaling of chip performance into multi-gigabit data rates puts special demands on the bandwidth of interconnect systems. This leads to the need for careful optimization of the parameters of the channel and the components along the path of the signal and the need of special circuitry in transceivers to mitigate the effects of the band-limited channels. This paper characterizes various bandwidth limiting factors in a low-cost interconnect system and evaluates equalization techniques that are needed to overcome the limitations to improve the interconnect system performance at multi-gigabit data rates. The sensitivity of equalization taps to manufacturing variations in channel parameters is also studied. Finally, detailed analyses of low-cost and high-speed memory operating at 3.2 Gbps and logic-to-logic interconnect systems operating at 6.4 Gbps are presented to illustrate the effectiveness of equalization techniques.
{"title":"Design and analysis of multi-gigahertz parallel bus interfaces of low-cost and band-limited channels","authors":"W. Beyene, N. Cheng, C. Yuan","doi":"10.1109/EPEP.2003.1250034","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250034","url":null,"abstract":"The further scaling of chip performance into multi-gigabit data rates puts special demands on the bandwidth of interconnect systems. This leads to the need for careful optimization of the parameters of the channel and the components along the path of the signal and the need of special circuitry in transceivers to mitigate the effects of the band-limited channels. This paper characterizes various bandwidth limiting factors in a low-cost interconnect system and evaluates equalization techniques that are needed to overcome the limitations to improve the interconnect system performance at multi-gigabit data rates. The sensitivity of equalization taps to manufacturing variations in channel parameters is also studied. Finally, detailed analyses of low-cost and high-speed memory operating at 3.2 Gbps and logic-to-logic interconnect systems operating at 6.4 Gbps are presented to illustrate the effectiveness of equalization techniques.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130090636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250048
B. Mutnury, M. Swaminathan, J. Libous
In this paper a modeling methodology using spline functions with finite time difference is proposed for modeling digital I/O drivers. Digital driver circuits can be accurately modeled using their static characteristics for normal excitations, but for faster excitations static characteristic models tend to lose their accuracy as the dynamic characteristics start to dominate the static characteristics. Spline function with finite time difference modeling includes previous time instances to capture dynamic characteristics for accurate modeling of digital drivers. In this paper the speed and accuracy of the proposed method is analyzed and compared with Radial Basis Function (RBF) modeling for different test cases.
{"title":"Macro-modeling of non-linear I/O drivers using spline functions and finite time difference approximation","authors":"B. Mutnury, M. Swaminathan, J. Libous","doi":"10.1109/EPEP.2003.1250048","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250048","url":null,"abstract":"In this paper a modeling methodology using spline functions with finite time difference is proposed for modeling digital I/O drivers. Digital driver circuits can be accurately modeled using their static characteristics for normal excitations, but for faster excitations static characteristic models tend to lose their accuracy as the dynamic characteristics start to dominate the static characteristics. Spline function with finite time difference modeling includes previous time instances to capture dynamic characteristics for accurate modeling of digital drivers. In this paper the speed and accuracy of the proposed method is analyzed and compared with Radial Basis Function (RBF) modeling for different test cases.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127673964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250070
A. Rong, A. Cangellaris, Limin Dong
This paper proposes a comprehensive integral equation electromagnetic field solver for broadband modeling of on-chip interconnects. Instead of the computationally intensive volumetric discretization model, which appears to be currently the most popular method of choice for handling the tall and narrow cross sections of the on-chip wiring and capturing correctly the impact of adjacent wiring coupling and skin effect, the proposed generalized partial element equivalent circuit (PEEC) methodology utilizes a computationally more efficient conductor surface discretization. Key to the success of such a surface discretization model is the definition of a position- and frequency-dependent surface impedance used to relate the tangential electric field and current on the wire surface. A novel strategy for the identification of loops in the resulting discrete model leads to a numerically-stable and efficient mesh analysis-based PEEC formulation in support of on-chip interconnect electromagnetic modeling from DC to multi-GHz frequencies.
{"title":"Comprehensive broadband electromagnetic modeling of on-chip interconnects with a surface discretization-based generalized PEEC model","authors":"A. Rong, A. Cangellaris, Limin Dong","doi":"10.1109/EPEP.2003.1250070","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250070","url":null,"abstract":"This paper proposes a comprehensive integral equation electromagnetic field solver for broadband modeling of on-chip interconnects. Instead of the computationally intensive volumetric discretization model, which appears to be currently the most popular method of choice for handling the tall and narrow cross sections of the on-chip wiring and capturing correctly the impact of adjacent wiring coupling and skin effect, the proposed generalized partial element equivalent circuit (PEEC) methodology utilizes a computationally more efficient conductor surface discretization. Key to the success of such a surface discretization model is the definition of a position- and frequency-dependent surface impedance used to relate the tangential electric field and current on the wire surface. A novel strategy for the identification of loops in the resulting discrete model leads to a numerically-stable and efficient mesh analysis-based PEEC formulation in support of on-chip interconnect electromagnetic modeling from DC to multi-GHz frequencies.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115606407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250033
Xin Wu, M. H. Kermani, O. Ramahi
In this paper, a novel mesh fencing technique is proposed to mitigate the induced radiation from power bus due to fast switching. The mitigation effectiveness is investigated and quantified using the Finite Element Method (FEM) full wave solver.
{"title":"Mitigating multi-layer PCB power bus radiation through novel mesh fencing techniques","authors":"Xin Wu, M. H. Kermani, O. Ramahi","doi":"10.1109/EPEP.2003.1250033","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250033","url":null,"abstract":"In this paper, a novel mesh fencing technique is proposed to mitigate the induced radiation from power bus due to fast switching. The mitigation effectiveness is investigated and quantified using the Finite Element Method (FEM) full wave solver.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124019665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250019
M. Cases, D. de Araujo, N. Pham, E. Blackshear
As the performance of processors and their associated supporting components increases with improvements in process technologies, the demand on packaging solutions is also increasing. High-speed devices require complex thermal, power delivery and signal integrity solutions at relatively low cost to be competitive in the present marketplace. This paper presents the rapidly evolving laminate package trends and advances for high-speed system-level interconnects. The importance of properly designing the substrate for high-speed signaling is discussed including identification of key parameters and design tradeoffs.
{"title":"Laminate package trends for high-speed system interconnects","authors":"M. Cases, D. de Araujo, N. Pham, E. Blackshear","doi":"10.1109/EPEP.2003.1250019","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250019","url":null,"abstract":"As the performance of processors and their associated supporting components increases with improvements in process technologies, the demand on packaging solutions is also increasing. High-speed devices require complex thermal, power delivery and signal integrity solutions at relatively low cost to be competitive in the present marketplace. This paper presents the rapidly evolving laminate package trends and advances for high-speed system-level interconnects. The importance of properly designing the substrate for high-speed signaling is discussed including identification of key parameters and design tradeoffs.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115196879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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