Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250009
I. Novak, J.R. Miller
Power distribution networks (PDN) use various kinds of capacitors to create the required impedance profile and to suppress noise. The simple model of bypass capacitors is a series R-L-C network with frequency independent parameters. The paper gives measured data for various bulk and ceramic capacitors, showing the extraction procedure and frequency dependent data of all three parameters. Various physical contributors to the frequency dependencies are identified. From low frequencies up to SRF (series resonance frequency), capacitance can drop as much as 60%. Inductance should be measured in a small PCB fixture with planes, vias and pads representing the intended application. The added inductance due to the capacitor body is shown to be fairly independent of via length connecting to the nearest planes.
{"title":"Frequency-dependent characterization of bulk and ceramic bypass capacitors","authors":"I. Novak, J.R. Miller","doi":"10.1109/EPEP.2003.1250009","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250009","url":null,"abstract":"Power distribution networks (PDN) use various kinds of capacitors to create the required impedance profile and to suppress noise. The simple model of bypass capacitors is a series R-L-C network with frequency independent parameters. The paper gives measured data for various bulk and ceramic capacitors, showing the extraction procedure and frequency dependent data of all three parameters. Various physical contributors to the frequency dependencies are identified. From low frequencies up to SRF (series resonance frequency), capacitance can drop as much as 60%. Inductance should be measured in a small PCB fixture with planes, vias and pads representing the intended application. The added inductance due to the capacitor body is shown to be fairly independent of via length connecting to the nearest planes.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133438023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250035
M. Shen, Jian Liu, Lirong Zheng, H. Tenhunen
As technology scales down, the performance of most digital systems is limited by their package, not by their logic because of package parasitics. In this paper, a chip-package co-design approach was used for high-speed transmitter design towards serial links application. Impedance-controlled signal channel and power efficient multi-level current-mode differential signaling were analyzed and used in order to improve the overall system performance and robustness. Simulation results show that noise margin is increased while time margin is decreased for impedance-controlled signal channel in the operation frequencies. In addition, it is found that the bipolar driver can reduce power consumption by a factor of 15% compared with current mode logic driver.
{"title":"Chip-package co-design for high-speed transmitter in serial links application","authors":"M. Shen, Jian Liu, Lirong Zheng, H. Tenhunen","doi":"10.1109/EPEP.2003.1250035","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250035","url":null,"abstract":"As technology scales down, the performance of most digital systems is limited by their package, not by their logic because of package parasitics. In this paper, a chip-package co-design approach was used for high-speed transmitter design towards serial links application. Impedance-controlled signal channel and power efficient multi-level current-mode differential signaling were analyzed and used in order to improve the overall system performance and robustness. Simulation results show that noise margin is increased while time margin is decreased for impedance-controlled signal channel in the operation frequencies. In addition, it is found that the bipolar driver can reduce power consumption by a factor of 15% compared with current mode logic driver.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131135558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250021
C. Wyland, W. Nunn
Due to the performance requirements of the DDR2 memory specification, a study was initiated to determine whether or not it could be implemented in a 1000 ball grid array (BGA) with other equally demanding signaling interfaces. The goals of the study were: to determine if the DDR specification requirements could be met in a 1000 ball BGA, which package would be most cost effective, how many memory modules could be supported, and to offer recommendations for improving the package design and signaling circuit implementation. These goals were challenging due to the emphasis on cost. The cheapest packages with 1000 balls have their routing traces very close together and constrained dimensions on the power supply planes. By being built in this way, they tend to have high crosstalk and power supply noise, which would negatively impact the performance of the signaling interface. By investigating the characteristics of these packages we were able to determine they could be used within certain design constraints.
{"title":"Signal integrity study of 1000 ball grid array package construction effects on DDR2 at 533MHz","authors":"C. Wyland, W. Nunn","doi":"10.1109/EPEP.2003.1250021","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250021","url":null,"abstract":"Due to the performance requirements of the DDR2 memory specification, a study was initiated to determine whether or not it could be implemented in a 1000 ball grid array (BGA) with other equally demanding signaling interfaces. The goals of the study were: to determine if the DDR specification requirements could be met in a 1000 ball BGA, which package would be most cost effective, how many memory modules could be supported, and to offer recommendations for improving the package design and signaling circuit implementation. These goals were challenging due to the emphasis on cost. The cheapest packages with 1000 balls have their routing traces very close together and constrained dimensions on the power supply planes. By being built in this way, they tend to have high crosstalk and power supply noise, which would negatively impact the performance of the signaling interface. By investigating the characteristics of these packages we were able to determine they could be used within certain design constraints.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131086939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1249991
E. Matoglu, Madhavan Swaminathan, M. Cases, Nam H. Pham, D. N. D. Araujo
This paper presents an efficient statistical method to increase the data rate of local I/O bus. Parametric yield of the PCI-X has been computed at a higher data rate. Then yield loss at higher data rate has been recovered by making the most feasible and effective adjustments. Instead of full factorial signal integrity analysis, sensitivity relations and statistical distributions of signal integrity measures have been computed, which supply detailed information to designers and manufacturers.
{"title":"Design space exploration of high-speed busses using statistical methods","authors":"E. Matoglu, Madhavan Swaminathan, M. Cases, Nam H. Pham, D. N. D. Araujo","doi":"10.1109/EPEP.2003.1249991","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1249991","url":null,"abstract":"This paper presents an efficient statistical method to increase the data rate of local I/O bus. Parametric yield of the PCI-X has been computed at a higher data rate. Then yield loss at higher data rate has been recovered by making the most feasible and effective adjustments. Instead of full factorial signal integrity analysis, sensitivity relations and statistical distributions of signal integrity measures have been computed, which supply detailed information to designers and manufacturers.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121467641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250051
S. Grivet-Talocia
This paper presents a new technique for the generation of linear lumped macromodels from input-output port characterization. A complete set of transient port responses is processed by a new time-domain formulation of the well-known Vector Fitting algorithm. The data processing involves a combination of digital filtering and least squares fitting. Passivity of the obtained macromodel is enforced a posteriori by applying an iterative perturbation technique to the associated Hamiltonian matrix.
{"title":"Generation of passive macromodels from transient port responses","authors":"S. Grivet-Talocia","doi":"10.1109/EPEP.2003.1250051","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250051","url":null,"abstract":"This paper presents a new technique for the generation of linear lumped macromodels from input-output port characterization. A complete set of transient port responses is processed by a new time-domain formulation of the well-known Vector Fitting algorithm. The data processing involves a combination of digital filtering and least squares fitting. Passivity of the obtained macromodel is enforced a posteriori by applying an iterative perturbation technique to the associated Hamiltonian matrix.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114369693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250018
R. Schmitt, X. Huang, C. Yuan
As the operating frequency of I/O circuits increases and voltage swing decreases, it becomes increasingly important to verify the power distribution network (PDN). This paper presents a methodology used to design and verify the PDN for a multi-gigabit memory interfaces. It describes the modeling of PDN components, the necessary analysis steps to assist in the design of a high-quality PDN, and the simulations to predict the impact of supply noise on the signal quality in the memory channel.
{"title":"Power distribution analysis methodology for a multi-gigabit I/O interface","authors":"R. Schmitt, X. Huang, C. Yuan","doi":"10.1109/EPEP.2003.1250018","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250018","url":null,"abstract":"As the operating frequency of I/O circuits increases and voltage swing decreases, it becomes increasingly important to verify the power distribution network (PDN). This paper presents a methodology used to design and verify the PDN for a multi-gigabit memory interfaces. It describes the modeling of PDN components, the necessary analysis steps to assist in the design of a high-quality PDN, and the simulations to predict the impact of supply noise on the signal quality in the memory channel.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114566221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250022
Seungyoung Ahn, Jongbae Park, Daehyun Chung, Joungho Kim
We firstly introduce the compensation of ICs input capacitance effect by using the package bondwire inductance. With the analysis of this effect, we suggested the methodology of finding optimized inductance and demonstrated the improvement in time-domain performance by simulation and measurement.
{"title":"Compensation of ESD and input capacitance effect by using package bondwire inductance for over Gbps differential SerDes devices","authors":"Seungyoung Ahn, Jongbae Park, Daehyun Chung, Joungho Kim","doi":"10.1109/EPEP.2003.1250022","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250022","url":null,"abstract":"We firstly introduce the compensation of ICs input capacitance effect by using the package bondwire inductance. With the analysis of this effect, we suggested the methodology of finding optimized inductance and demonstrated the improvement in time-domain performance by simulation and measurement.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123076793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250049
A. Varma, A. Glaser, S. Lipa, Michael B. Steer, P. Franzon
A tool to convert SPICE netlists to IBIS (Input/Output Buffer Information Specification) models is presented. This tool simulates the netlist on a user-desirable SPICE engine and produces both static and dynamic characteristics of the IBIS model.
{"title":"The development of a macro-modeling tool to develop IBIS models","authors":"A. Varma, A. Glaser, S. Lipa, Michael B. Steer, P. Franzon","doi":"10.1109/EPEP.2003.1250049","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250049","url":null,"abstract":"A tool to convert SPICE netlists to IBIS (Input/Output Buffer Information Specification) models is presented. This tool simulates the netlist on a user-desirable SPICE engine and produces both static and dynamic characteristics of the IBIS model.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121332333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250000
L. Shan, J. Trewhella, C. Baks, R. John, W. Dyckman, D. O'connor, E. Pillai
In this work, standard multi-layer ceramic (Alumina) BGA packages were designed and fabricated to accommodate a 50Gb/s flip-chip multiplexing circuit built on SiGe BiCMOS technology. The ceramic packages are of the size of 17/spl times/17 mm/sup 2/ with 8 layer internal stacks, C4 bonding pads on top, and BGA solder joints at the bottom. For comparisons and various application needs, the high-speed output nets were routed with two approaches, "surface coaxial escape" and "through BGA escape". In the case of "through BGA escape", special via structures were designed to optimize the signal transmissions within a wide frequency range, DC/spl sim/50GHz. To test the performance of the package, two types of test carriers were designed and fabricated on low-loss organic boards, one with edge-mount coaxial connectors for full functional tests, and the other with probe sites for through BGA characterizations in both frequency and time domains. Prior to the physical layout of the designs, electrical analysis was performed with segmentation and re-assembling technique that employs full-wave EM simulations. The results were then compared with measurements, and effective model-to-hardware correlations were found. The existing measurement results indicate that, by properly design the critical nets, standard multi-layer BGA packages can be used for high-speed applications up to 40/spl sim/55Gb/sec data-rate/frequency range.
{"title":"A low-cost ceramic BGA package for 50 Gb/s multiplexing circuit","authors":"L. Shan, J. Trewhella, C. Baks, R. John, W. Dyckman, D. O'connor, E. Pillai","doi":"10.1109/EPEP.2003.1250000","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250000","url":null,"abstract":"In this work, standard multi-layer ceramic (Alumina) BGA packages were designed and fabricated to accommodate a 50Gb/s flip-chip multiplexing circuit built on SiGe BiCMOS technology. The ceramic packages are of the size of 17/spl times/17 mm/sup 2/ with 8 layer internal stacks, C4 bonding pads on top, and BGA solder joints at the bottom. For comparisons and various application needs, the high-speed output nets were routed with two approaches, \"surface coaxial escape\" and \"through BGA escape\". In the case of \"through BGA escape\", special via structures were designed to optimize the signal transmissions within a wide frequency range, DC/spl sim/50GHz. To test the performance of the package, two types of test carriers were designed and fabricated on low-loss organic boards, one with edge-mount coaxial connectors for full functional tests, and the other with probe sites for through BGA characterizations in both frequency and time domains. Prior to the physical layout of the designs, electrical analysis was performed with segmentation and re-assembling technique that employs full-wave EM simulations. The results were then compared with measurements, and effective model-to-hardware correlations were found. The existing measurement results indicate that, by properly design the critical nets, standard multi-layer BGA packages can be used for high-speed applications up to 40/spl sim/55Gb/sec data-rate/frequency range.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125514948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250052
Huabo Chen, J. Fang
A new method of enforcing the bounded realness of S parameter macro-model is proposed in this paper. With a given stable rational function obtained from fitting the original data, its closest bounded real rational function is solved through semidefinite programming. This optimization problem is formulated through trace parameterization and uses minimal number of variables.
{"title":"Enforcing bounded realness of S parameter through trace parameterization","authors":"Huabo Chen, J. Fang","doi":"10.1109/EPEP.2003.1250052","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250052","url":null,"abstract":"A new method of enforcing the bounded realness of S parameter macro-model is proposed in this paper. With a given stable rational function obtained from fitting the original data, its closest bounded real rational function is solved through semidefinite programming. This optimization problem is formulated through trace parameterization and uses minimal number of variables.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125662763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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