Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250018
R. Schmitt, X. Huang, C. Yuan
As the operating frequency of I/O circuits increases and voltage swing decreases, it becomes increasingly important to verify the power distribution network (PDN). This paper presents a methodology used to design and verify the PDN for a multi-gigabit memory interfaces. It describes the modeling of PDN components, the necessary analysis steps to assist in the design of a high-quality PDN, and the simulations to predict the impact of supply noise on the signal quality in the memory channel.
{"title":"Power distribution analysis methodology for a multi-gigabit I/O interface","authors":"R. Schmitt, X. Huang, C. Yuan","doi":"10.1109/EPEP.2003.1250018","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250018","url":null,"abstract":"As the operating frequency of I/O circuits increases and voltage swing decreases, it becomes increasingly important to verify the power distribution network (PDN). This paper presents a methodology used to design and verify the PDN for a multi-gigabit memory interfaces. It describes the modeling of PDN components, the necessary analysis steps to assist in the design of a high-quality PDN, and the simulations to predict the impact of supply noise on the signal quality in the memory channel.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114566221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250052
Huabo Chen, J. Fang
A new method of enforcing the bounded realness of S parameter macro-model is proposed in this paper. With a given stable rational function obtained from fitting the original data, its closest bounded real rational function is solved through semidefinite programming. This optimization problem is formulated through trace parameterization and uses minimal number of variables.
{"title":"Enforcing bounded realness of S parameter through trace parameterization","authors":"Huabo Chen, J. Fang","doi":"10.1109/EPEP.2003.1250052","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250052","url":null,"abstract":"A new method of enforcing the bounded realness of S parameter macro-model is proposed in this paper. With a given stable rational function obtained from fitting the original data, its closest bounded real rational function is solved through semidefinite programming. This optimization problem is formulated through trace parameterization and uses minimal number of variables.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125662763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250012
Zhiping Yang, Jin Zhao, S. Camerlo, J. Fang
The impact of anti-pad array on power and ground planes,. especially at the area right under the BGA package, has been studied in this paper. An effective modeling and simulation approach based on 3D field computation has been used to take into account the anti-pad array effect. The simulation results match the measurement results. It has been found that the effect of anti-pad array on power delivery system is considerable; therefore it cannot be ignored in the power delivery system analysis and design for high-speed applications.
{"title":"Impact and modeling of anti-pad array on power delivery system","authors":"Zhiping Yang, Jin Zhao, S. Camerlo, J. Fang","doi":"10.1109/EPEP.2003.1250012","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250012","url":null,"abstract":"The impact of anti-pad array on power and ground planes,. especially at the area right under the BGA package, has been studied in this paper. An effective modeling and simulation approach based on 3D field computation has been used to take into account the anti-pad array effect. The simulation results match the measurement results. It has been found that the effect of anti-pad array on power delivery system is considerable; therefore it cannot be ignored in the power delivery system analysis and design for high-speed applications.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129374192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250015
Hyungsoo Kim, Y. Jeong, Jongbae Park, SeokKyu-lee, JongKuk-Hong, Youngsoo Hong, Joungho Kim
Significant reduction of power/ground inductive impedance and SSN suppression was successfully demonstrated by using embedded capacitor film in high performance package and PCB up to 3GHz frequency range. The reduction of the inductance impedance and SSN are acquired by the help of reduced via inductance in the embedded film capacitor.
{"title":"Significant reduction of power/ground inductive impedance and simultaneous switching noise by using embedded film capacitor","authors":"Hyungsoo Kim, Y. Jeong, Jongbae Park, SeokKyu-lee, JongKuk-Hong, Youngsoo Hong, Joungho Kim","doi":"10.1109/EPEP.2003.1250015","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250015","url":null,"abstract":"Significant reduction of power/ground inductive impedance and SSN suppression was successfully demonstrated by using embedded capacitor film in high performance package and PCB up to 3GHz frequency range. The reduction of the inductance impedance and SSN are acquired by the help of reduced via inductance in the embedded film capacitor.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133091746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250028
C. Sullivan, Yuqin Sun
Measurements show that lumped RLC models for multilayer ceramic capacitors are inadequate. A new transmission-line model offers advantages over previous transmission-line models: a closer fit to measured data, and a physical basis for the model.
{"title":"Physically-based distributed models for multi-layer ceramic capacitors","authors":"C. Sullivan, Yuqin Sun","doi":"10.1109/EPEP.2003.1250028","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250028","url":null,"abstract":"Measurements show that lumped RLC models for multilayer ceramic capacitors are inadequate. A new transmission-line model offers advantages over previous transmission-line models: a closer fit to measured data, and a physical basis for the model.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134317004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250038
A. Wirick, S. Ulrich, N. Pham, M. Cases, D. de Araujo
This paper describes the electrical packaging challenges, design issues, and design solutions for source-synchronous DDR II memory subsystems utilizing the double data rate (DDR) timing protocols. Major design and modeling issues are discussed, such as crosstalk, delay skew, impedance control and inter-symbol interference. The timing and jitter budgets, and the noise margin allocation for the various components of the optimization equations are discussed in conjunction with their associated design control techniques. A novel termination technique is discussed that allows for maximum memory capacity per channel at a given data rate.
{"title":"Design and modeling challenges for DDR II memory subsystems","authors":"A. Wirick, S. Ulrich, N. Pham, M. Cases, D. de Araujo","doi":"10.1109/EPEP.2003.1250038","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250038","url":null,"abstract":"This paper describes the electrical packaging challenges, design issues, and design solutions for source-synchronous DDR II memory subsystems utilizing the double data rate (DDR) timing protocols. Major design and modeling issues are discussed, such as crosstalk, delay skew, impedance control and inter-symbol interference. The timing and jitter budgets, and the noise margin allocation for the various components of the optimization equations are discussed in conjunction with their associated design control techniques. A novel termination technique is discussed that allows for maximum memory capacity per channel at a given data rate.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130296335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250022
Seungyoung Ahn, Jongbae Park, Daehyun Chung, Joungho Kim
We firstly introduce the compensation of ICs input capacitance effect by using the package bondwire inductance. With the analysis of this effect, we suggested the methodology of finding optimized inductance and demonstrated the improvement in time-domain performance by simulation and measurement.
{"title":"Compensation of ESD and input capacitance effect by using package bondwire inductance for over Gbps differential SerDes devices","authors":"Seungyoung Ahn, Jongbae Park, Daehyun Chung, Joungho Kim","doi":"10.1109/EPEP.2003.1250022","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250022","url":null,"abstract":"We firstly introduce the compensation of ICs input capacitance effect by using the package bondwire inductance. With the analysis of this effect, we suggested the methodology of finding optimized inductance and demonstrated the improvement in time-domain performance by simulation and measurement.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123076793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1249997
R. Weekly, S. Chun, A. Haridass, C. O'Reilly, J. Jordan, F. O'Connell
This paper presents a method for extracting current excitations, which a microprocessor (/spl mu/P) can present to its power distribution system (PDS) as a function of frequency. The method uses a clock modulation technique to measure the impedance seen by the uP.
{"title":"Optimum design of power distribution system via clock modulation","authors":"R. Weekly, S. Chun, A. Haridass, C. O'Reilly, J. Jordan, F. O'Connell","doi":"10.1109/EPEP.2003.1249997","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1249997","url":null,"abstract":"This paper presents a method for extracting current excitations, which a microprocessor (/spl mu/P) can present to its power distribution system (PDS) as a function of frequency. The method uses a clock modulation technique to measure the impedance seen by the uP.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129933688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250003
L. Zhu, K. Melde, J. Prince
A broadband CPW to microstrip via-less transition is proposed and the optimal design is discussed. Simulation and measurement results are given. The results of the transition as multiline TRL calibration standards are presented.
{"title":"A broadband CPW-to-microstrip via-less transition for on wafer package probing applications","authors":"L. Zhu, K. Melde, J. Prince","doi":"10.1109/EPEP.2003.1250003","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250003","url":null,"abstract":"A broadband CPW to microstrip via-less transition is proposed and the optimal design is discussed. Simulation and measurement results are given. The results of the transition as multiline TRL calibration standards are presented.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129594091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1249998
X. Duo, Lirong Zheng, H. Tenhunen, Liu Chen, Gang Zou, Johan Liu
In this paper, we present a receiver front-end for 5GHz wireless LAN in novel LCP (liquid crystal polymer) based system-on-package module. The module is based on embedded chip technologies for system-on-package, which eliminates the constraints of off-chip pad drive capability and hence improves electrical performance. Furthermore, the novel LCP material shows excellent RF and microwave performance. The quality factors of key passive components such as inductors integrated in LCP substrate with thin film technologies is as high as 60. The insertion loss of the bandpass filter is 3dB. The conversion gain of the receiver front-end is 20dB and occupies 8.7mm by 3.6mm area.
{"title":"Design and implementation of a 5GHz RF receiver front-end in LCP based system-on-package module with embedded chip technology","authors":"X. Duo, Lirong Zheng, H. Tenhunen, Liu Chen, Gang Zou, Johan Liu","doi":"10.1109/EPEP.2003.1249998","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1249998","url":null,"abstract":"In this paper, we present a receiver front-end for 5GHz wireless LAN in novel LCP (liquid crystal polymer) based system-on-package module. The module is based on embedded chip technologies for system-on-package, which eliminates the constraints of off-chip pad drive capability and hence improves electrical performance. Furthermore, the novel LCP material shows excellent RF and microwave performance. The quality factors of key passive components such as inductors integrated in LCP substrate with thin film technologies is as high as 60. The insertion loss of the bandpass filter is 3dB. The conversion gain of the receiver front-end is 20dB and occupies 8.7mm by 3.6mm area.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124735758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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