Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250066
G. Antonini, A. Ruehli, A. Haridass
The PEEC method and solvers are continuously evolving as more new features are added to the approach. Finite dielectrics were added to solve a new class of multi dielectric problem. Dielectric losses are becoming more important with the recent increase in the frequencies in the problems which need solving. In this work, we provide an approach which is applied to the dielectric model to include losses. Recursive convolution and circuit synthesis techniques are employed to take into account the dispersive behavior of the dielectric. Presently, the algorithm has been applied to materials with a Lorentzian model for the complex permittivity. The accuracy of the proposed approach is demonstrated by an example.
{"title":"Including dispersive dielectrics in PEEC models","authors":"G. Antonini, A. Ruehli, A. Haridass","doi":"10.1109/EPEP.2003.1250066","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250066","url":null,"abstract":"The PEEC method and solvers are continuously evolving as more new features are added to the approach. Finite dielectrics were added to solve a new class of multi dielectric problem. Dielectric losses are becoming more important with the recent increase in the frequencies in the problems which need solving. In this work, we provide an approach which is applied to the dielectric model to include losses. Recursive convolution and circuit synthesis techniques are employed to take into account the dispersive behavior of the dielectric. Presently, the algorithm has been applied to materials with a Lorentzian model for the complex permittivity. The accuracy of the proposed approach is demonstrated by an example.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128155281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250055
S. Ulrich, A. Wirick, D. de Araujo, N. Pham, M. Cases
This paper describes the use of a genetic algorithm to optimize short bitstream inputs to produce approximately worst case jitter in package simulation. Theory behind the algorithm and its applicability to a server memory subsystem simulation is summarized. Custom software utilizing this algorithm and an example of its use are presented.
{"title":"The Nittany Genome Project: a genetic algorithm approach to optimize a worst case bitstream for package simulation","authors":"S. Ulrich, A. Wirick, D. de Araujo, N. Pham, M. Cases","doi":"10.1109/EPEP.2003.1250055","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250055","url":null,"abstract":"This paper describes the use of a genetic algorithm to optimize short bitstream inputs to produce approximately worst case jitter in package simulation. Theory behind the algorithm and its applicability to a server memory subsystem simulation is summarized. Custom software utilizing this algorithm and an example of its use are presented.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"532 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115389436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250023
Y.C. Pan, U. Mughal, M. Rifani, T.M. Wilson
The design of a robust microprocessor requires extensive logic validation. Millions of test vectors are applied and the output of every logic node is checked against the expected output. This is largely done with RTL simulators. Such simulators ignore the analog aspects of the circuits such as power supply noise and transmission line effects. Traditionally, the analog aspects are taken into account using SPICE-like simulators to model representative cases and design for what is perceived to be the worst-case input stimulus. Alternatively, in this paper, we will present a mixed signal validation approach that comprehends both the logic and analog aspects of the circuits. We show how we applied this to the Pentium 4 processor power-up sequence validation. We will also discuss extending this approach to other disciplines such as platform and packaging.
{"title":"Mixed signal validation of the Intel/spl reg/ Pentium/spl reg/ 4 microprocessor power-up sequence","authors":"Y.C. Pan, U. Mughal, M. Rifani, T.M. Wilson","doi":"10.1109/EPEP.2003.1250023","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250023","url":null,"abstract":"The design of a robust microprocessor requires extensive logic validation. Millions of test vectors are applied and the output of every logic node is checked against the expected output. This is largely done with RTL simulators. Such simulators ignore the analog aspects of the circuits such as power supply noise and transmission line effects. Traditionally, the analog aspects are taken into account using SPICE-like simulators to model representative cases and design for what is perceived to be the worst-case input stimulus. Alternatively, in this paper, we will present a mixed signal validation approach that comprehends both the logic and analog aspects of the circuits. We show how we applied this to the Pentium 4 processor power-up sequence validation. We will also discuss extending this approach to other disciplines such as platform and packaging.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129710233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250013
L. Smith, J. Lee
The Power Distribution System (PDS) for a JEDEC DDR2 Dual Inline Memory Module (DIMM) has been designed. The process involved establishing a target impedance in the frequency domain, determining the inductance of the connector and capacitor mounts and selecting a matrix of discrete ceramic capacitors from a menu of previously characterized devices to meet the target impedance. After hardware was available, S21 measurements were made with a 2 port VNA to establish model to hardware correlation.
{"title":"Power distribution system for JEDEC DDR2 memory DIMM","authors":"L. Smith, J. Lee","doi":"10.1109/EPEP.2003.1250013","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250013","url":null,"abstract":"The Power Distribution System (PDS) for a JEDEC DDR2 Dual Inline Memory Module (DIMM) has been designed. The process involved establishing a target impedance in the frequency domain, determining the inductance of the connector and capacitor mounts and selecting a matrix of discrete ceramic capacitors from a menu of previously characterized devices to meet the target impedance. After hardware was available, S21 measurements were made with a 2 port VNA to establish model to hardware correlation.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129121417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1249989
A. Varma, A. Glaser, P. Franzon
A unified method is presented for layout and package design implemented within a commercial design environment that will reduce design time and enable chip-package codesign.
{"title":"CAD flows for chip-package codesign","authors":"A. Varma, A. Glaser, P. Franzon","doi":"10.1109/EPEP.2003.1249989","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1249989","url":null,"abstract":"A unified method is presented for layout and package design implemented within a commercial design environment that will reduce design time and enable chip-package codesign.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127661545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250031
Y. Jeong, Hyungsoo Kim, Jingook Kim, Jongbae Park, Joungho Kim
Various noise isolation methods for low jitter on the power/ground plane are thoroughly analyzed and a new method is proposed. We analyzed using both frequency and time domain measurement methods and the results were verified by jitter measurements.
{"title":"Analysis of noise isolation methods on split power/ground plane of multi-layered package and PCB for low jitter mixed mode system","authors":"Y. Jeong, Hyungsoo Kim, Jingook Kim, Jongbae Park, Joungho Kim","doi":"10.1109/EPEP.2003.1250031","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250031","url":null,"abstract":"Various noise isolation methods for low jitter on the power/ground plane are thoroughly analyzed and a new method is proposed. We analyzed using both frequency and time domain measurement methods and the results were verified by jitter measurements.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126141447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250067
Xin Hu, L. Daniel, J. White
In this paper, conduction mode basis functions, previously developed to improve the efficiency of volume integral equation-based electromagnetic analysis of interconnect, are adapted for use in a surface integral equation formulation. A partitioning scheme is introduced to eliminate low-frequency ill-conditioning. Results for a wire, ring and transmission line are used to show that combining partitioned conduction modes with a Galerkin discretization scheme improves the surface integral solver's wideband accuracy and efficiency.
{"title":"Partitioned conduction modes in surface integral equation-based impedance extraction","authors":"Xin Hu, L. Daniel, J. White","doi":"10.1109/EPEP.2003.1250067","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250067","url":null,"abstract":"In this paper, conduction mode basis functions, previously developed to improve the efficiency of volume integral equation-based electromagnetic analysis of interconnect, are adapted for use in a surface integral equation formulation. A partitioning scheme is introduced to eliminate low-frequency ill-conditioning. Results for a wire, ring and transmission line are used to show that combining partitioned conduction modes with a Galerkin discretization scheme improves the surface integral solver's wideband accuracy and efficiency.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126083810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250062
W. Chew, L.J. Jiang, Y. Chu, G.L. Wang, Y.C. Pan
Summary form only given. In this talk, we review fast integral equation solvers for low frequencies and high frequencies. We discuss some of the current problems and suggest possible solutions. We also describe the use of fast solvers for layered media. When applied to low frequencies, fast solvers usually have a low-frequency breakdown. Methods to overcome this low frequency breakdown are discussed. Moreover, a general method of moments encounters low frequency breakdown problems, and a remedy for this is also given. Many of the low frequency problems can be tackled by setting the frequency identically to zero, hence solving an electrostatic or a magnetostatic problem. Such a solution technique is also presented. For layered structures, we need a special Green's function. A closed form Green's function can be used to solve some of the complicated layered medium problems. Also, some applications of fast solvers to solve the lithography problem are demonstrated.
{"title":"Toward a more robust and accurate fast integral equation solver for microchip applications","authors":"W. Chew, L.J. Jiang, Y. Chu, G.L. Wang, Y.C. Pan","doi":"10.1109/EPEP.2003.1250062","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250062","url":null,"abstract":"Summary form only given. In this talk, we review fast integral equation solvers for low frequencies and high frequencies. We discuss some of the current problems and suggest possible solutions. We also describe the use of fast solvers for layered media. When applied to low frequencies, fast solvers usually have a low-frequency breakdown. Methods to overcome this low frequency breakdown are discussed. Moreover, a general method of moments encounters low frequency breakdown problems, and a remedy for this is also given. Many of the low frequency problems can be tackled by setting the frequency identically to zero, hence solving an electrostatic or a magnetostatic problem. Such a solution technique is also presented. For layered structures, we need a special Green's function. A closed form Green's function can be used to solve some of the complicated layered medium problems. Also, some applications of fast solvers to solve the lithography problem are demonstrated.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125895022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250063
D. Gope, V. Jandhyala
Integral equation methodologies applied to extract parasitics at the board, package, and on-chip levels involve solving a dense system of equations. In this paper, we present an improved oct-tree based multilevel QR compression technique for fast iterative solution. The regular tree and interaction structure of the fast multipole method, and the QR compression scheme applied to interaction sub-matrices as in IES/sup 3/ are combined to achieve superior time and memory efficiency. As is demonstrated by numerical simulation results presented herein, the new algorithm is found to be faster than both existing QR based methods and FastCap.
{"title":"PILOT: a fast algorithm for enhanced 3D parasitic extraction efficiency","authors":"D. Gope, V. Jandhyala","doi":"10.1109/EPEP.2003.1250063","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250063","url":null,"abstract":"Integral equation methodologies applied to extract parasitics at the board, package, and on-chip levels involve solving a dense system of equations. In this paper, we present an improved oct-tree based multilevel QR compression technique for fast iterative solution. The regular tree and interaction structure of the fast multipole method, and the QR compression scheme applied to interaction sub-matrices as in IES/sup 3/ are combined to achieve superior time and memory efficiency. As is demonstrated by numerical simulation results presented herein, the new algorithm is found to be faster than both existing QR based methods and FastCap.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132501752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250060
Yong Wang, D. Quint, E. Fetzer
This paper presents a new approach for the integrated power grid modeling and analysis. A loop-based inductance model is used to simplify the package and on-chip circuit model. A more accurate on-chip load model is created for current and future IC processes.
{"title":"Integrated power grid modeling and analysis","authors":"Yong Wang, D. Quint, E. Fetzer","doi":"10.1109/EPEP.2003.1250060","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250060","url":null,"abstract":"This paper presents a new approach for the integrated power grid modeling and analysis. A loop-based inductance model is used to simplify the package and on-chip circuit model. A more accurate on-chip load model is created for current and future IC processes.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"82 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131625197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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