Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250016
Yong-Ju Kim, Jong-Ho Kang, KunWoo-park, J. Wee, K. Hong
In this letter, a noble methodology for design of the power distribution networks is presented. The proposed method is based on the PDN(power distribution network) synthesis with the path-based equivalent circuit (PBEC) model. From this approach, on-chip decoupling capacitance and effective inductance of the package as well as the amount, number and location of off-chip decoupling capacitors can directly be determined. The result of the proposed method was verified through comparison with that of PEEC (Partial Elements Equivalent Circuit).
{"title":"Synthesis method for design of power distribution network in high-speed digital systems","authors":"Yong-Ju Kim, Jong-Ho Kang, KunWoo-park, J. Wee, K. Hong","doi":"10.1109/EPEP.2003.1250016","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250016","url":null,"abstract":"In this letter, a noble methodology for design of the power distribution networks is presented. The proposed method is based on the PDN(power distribution network) synthesis with the path-based equivalent circuit (PBEC) model. From this approach, on-chip decoupling capacitance and effective inductance of the package as well as the amount, number and location of off-chip decoupling capacitors can directly be determined. The result of the proposed method was verified through comparison with that of PEEC (Partial Elements Equivalent Circuit).","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133951184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1249992
S. Chun, A. Haridass, C. O'Reilly
This paper discusses a methodology to model I/O simultaneous switching noise (SSN) on power distribution of a computer system. The methodology combines two numerically efficient modeling techniques - for modeling plane resonances and non-linear drivers to solve large size problems. Simulation results using the method were compared with SSN measured on a realistic system to show the validity of the method.
{"title":"Efficient modeling of simultaneous switching noise in a realistic computer system","authors":"S. Chun, A. Haridass, C. O'Reilly","doi":"10.1109/EPEP.2003.1249992","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1249992","url":null,"abstract":"This paper discusses a methodology to model I/O simultaneous switching noise (SSN) on power distribution of a computer system. The methodology combines two numerically efficient modeling techniques - for modeling plane resonances and non-linear drivers to solve large size problems. Simulation results using the method were compared with SSN measured on a realistic system to show the validity of the method.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128840943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1249993
A. Waizman
CPU bypass mode clock gating and oscilloscope FFT features enable accurate measurement of a CPU's power delivery network impedance profile. The method described is self checking. Impedance profile characterization up to 100MHz is demonstrated.
{"title":"CPU power supply impedance profile measurement using FFT and clock gating","authors":"A. Waizman","doi":"10.1109/EPEP.2003.1249993","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1249993","url":null,"abstract":"CPU bypass mode clock gating and oscilloscope FFT features enable accurate measurement of a CPU's power delivery network impedance profile. The method described is self checking. Impedance profile characterization up to 100MHz is demonstrated.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133720573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250043
A. Dounavis, N. Nakhla, R. Achar, M. Nakhla
Recently, several algorithms were proposed for time-domain macromodeling of distributed transmission line networks. It has been demonstrated that preserving passivity of the macromodel is essential to guarantee a stable global transient simulation. Techniques such as method-of-characteristics yield fast transient results for long delay lines. However, they do not guarantee the passivity of the macromodel. On the other hand, methods such as matrix rational approximation provide efficient macromodels for lossy coupled lines, while preserving passivity. However, for long lossy delay lines this may require higher order approximations, making the macromodel inefficient. In order to address the above difficulty, this paper presents a new algorithm for efficient macromodeling of lossy coupled lines with long delay. The proposed method employs delay extraction prior to approximating the exponential stamp of the line and guarantees the macromodel passivity. The paper also provides guidelines on the practical applicability of the delay extraction and the matrix rational approximation, based on the knowledge of line parameters.
{"title":"Delay extraction and passive macromodeling of lossy coupled transmission lines","authors":"A. Dounavis, N. Nakhla, R. Achar, M. Nakhla","doi":"10.1109/EPEP.2003.1250043","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250043","url":null,"abstract":"Recently, several algorithms were proposed for time-domain macromodeling of distributed transmission line networks. It has been demonstrated that preserving passivity of the macromodel is essential to guarantee a stable global transient simulation. Techniques such as method-of-characteristics yield fast transient results for long delay lines. However, they do not guarantee the passivity of the macromodel. On the other hand, methods such as matrix rational approximation provide efficient macromodels for lossy coupled lines, while preserving passivity. However, for long lossy delay lines this may require higher order approximations, making the macromodel inefficient. In order to address the above difficulty, this paper presents a new algorithm for efficient macromodeling of lossy coupled lines with long delay. The proposed method employs delay extraction prior to approximating the exponential stamp of the line and guarantees the macromodel passivity. The paper also provides guidelines on the practical applicability of the delay extraction and the matrix rational approximation, based on the knowledge of line parameters.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123488076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1249994
J. Mao, Madhavan Swaminathan, J. Libous, D. O'Connor
This paper describes the effect of substrate loss on simultaneous switching noise (SSN) in on-chip power distribution networks (PDN). Conformal mapping and first-order Debye approximation based Finite Difference Time Domain (FDTD) have been used for model extraction and time domain simulation with frequency dependent parameters, respectively. The importance of substrate loss on power supply noise has been quantified in this paper.
{"title":"Effect of substrate resistivity on switching noise in on-chip power distribution networks","authors":"J. Mao, Madhavan Swaminathan, J. Libous, D. O'Connor","doi":"10.1109/EPEP.2003.1249994","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1249994","url":null,"abstract":"This paper describes the effect of substrate loss on simultaneous switching noise (SSN) in on-chip power distribution networks (PDN). Conformal mapping and first-order Debye approximation based Finite Difference Time Domain (FDTD) have been used for model extraction and time domain simulation with frequency dependent parameters, respectively. The importance of substrate loss on power supply noise has been quantified in this paper.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123495234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1249996
R. Mandrekar, M. Swaminathan, S. Chun
This paper describes a measurement based approach for extraction of the current signature to simulate switching noise in complex high speed systems. The approach is tested on a high speed functioning computer system from Sun Microsystems. Using the current source developed, simultaneous switching noise in the core power distribution network of the system has been simulated with good accuracy.
{"title":"Extraction of current signatures for simulation of simultaneous switching noise in high speed digital systems","authors":"R. Mandrekar, M. Swaminathan, S. Chun","doi":"10.1109/EPEP.2003.1249996","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1249996","url":null,"abstract":"This paper describes a measurement based approach for extraction of the current signature to simulate switching noise in complex high speed systems. The approach is tested on a high speed functioning computer system from Sun Microsystems. Using the current source developed, simultaneous switching noise in the core power distribution network of the system has been simulated with good accuracy.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128735615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250056
A. Deutsch, H.H. Smith, G. Kopcsay, B. Krauter, C. Surovic, A. Elfadel, D. Widiger
This paper discusses the effects of the frequency-dependent losses in the reference return path for wide, on-chip data buses, that must be understood in order to accurately predict the interaction and summation of crosstalk and common-mode noise signals. This interaction can generate excessive noise for on-chip global interconnections. Measured and simulated results are shown for representative 8-12 line couplings and circuit-synthesis techniques are shown to capture the correct R(f)L(f)C behavior of the reference series impedance.
{"title":"Understanding common-mode noise on wide data-buses","authors":"A. Deutsch, H.H. Smith, G. Kopcsay, B. Krauter, C. Surovic, A. Elfadel, D. Widiger","doi":"10.1109/EPEP.2003.1250056","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250056","url":null,"abstract":"This paper discusses the effects of the frequency-dependent losses in the reference return path for wide, on-chip data buses, that must be understood in order to accurately predict the interaction and summation of crosstalk and common-mode noise signals. This interaction can generate excessive noise for on-chip global interconnections. Measured and simulated results are shown for representative 8-12 line couplings and circuit-synthesis techniques are shown to capture the correct R(f)L(f)C behavior of the reference series impedance.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127114134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250029
Young-Seok Hong, Joon-Ho Choi, Chang-Woo Ko, Jin-Won Kim, Gi-Joung Jang, Moon-Hyun Yoo, J. Kong
Due to the increase of portable and high performance integrated circuit (IC) applications, package designs get smaller and more complex. Chip scaled multi-layer IC packages become one of the solutions to accommodate such requirements. In the design environment for complicated packages, a fast and accurate interconnect parasitic extraction method is very important in order to explore alternative designs in a limited time and to cope with lacking of design margins. This paper proposes a novel interconnect parasitic extraction method which combines the advantages of the inherently fast 2D approach and accurate 3D approach. Thus, it efficiently models the 3D effects around traces and vias such as the variable shaped reference plane and shielding, chip placement, package fringes, and current flows. The speed and the accuracy of parasitic, extractions are substantially improved compared to the conventional method in the application of multi-layer packages for leading edge memory products.
{"title":"A new fast and accurate method of extracting the parasitics of multi-layer packages","authors":"Young-Seok Hong, Joon-Ho Choi, Chang-Woo Ko, Jin-Won Kim, Gi-Joung Jang, Moon-Hyun Yoo, J. Kong","doi":"10.1109/EPEP.2003.1250029","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250029","url":null,"abstract":"Due to the increase of portable and high performance integrated circuit (IC) applications, package designs get smaller and more complex. Chip scaled multi-layer IC packages become one of the solutions to accommodate such requirements. In the design environment for complicated packages, a fast and accurate interconnect parasitic extraction method is very important in order to explore alternative designs in a limited time and to cope with lacking of design margins. This paper proposes a novel interconnect parasitic extraction method which combines the advantages of the inherently fast 2D approach and accurate 3D approach. Thus, it efficiently models the 3D effects around traces and vias such as the variable shaped reference plane and shielding, chip placement, package fringes, and current flows. The speed and the accuracy of parasitic, extractions are substantially improved compared to the conventional method in the application of multi-layer packages for leading edge memory products.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126606766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250020
A. Sarangi, S. R. Babcock, J. R. Jones, G. Taylor
This paper presents two approaches that have been used to maintain socket compatibility between a pair of microprocessors operating at different supply voltages. A current balancing scheme to keep independent regulators within their specified operating range when shorted through the microprocessor socket is presented. Using a network of termination resistors in the microprocessor's package, an operating scheme was developed such that minimum regulation current requirements could be met and a balanced current environment could be achieved inside two different switching regulators operating at different frequencies. The design and the implementation details of the current balancing method in the microprocessor is described and compared with measured data.
{"title":"Maintaining microprocessor compatibility across process generations","authors":"A. Sarangi, S. R. Babcock, J. R. Jones, G. Taylor","doi":"10.1109/EPEP.2003.1250020","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250020","url":null,"abstract":"This paper presents two approaches that have been used to maintain socket compatibility between a pair of microprocessors operating at different supply voltages. A current balancing scheme to keep independent regulators within their specified operating range when shorted through the microprocessor socket is presented. Using a network of termination resistors in the microprocessor's package, an operating scheme was developed such that minimum regulation current requirements could be met and a balanced current environment could be achieved inside two different switching regulators operating at different frequencies. The design and the implementation details of the current balancing method in the microprocessor is described and compared with measured data.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132830579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250047
Daehyun Chung, Seungyong Baek, Joungho Kim
Even though point to point transmission technique is the best solution for high speed data transmission, there still exist special signals that should drive multiple loads using H-tree to reduce skew and keep good signal quality at the same time. This paper shows problems of a current H-tree structure and suggests a new H-tree structure which is ISI(Inter Symbol Interference)-free and cost effective.
{"title":"Open load backward matching (OLBM) technique for low ISI differential H-tree clock and data transmission","authors":"Daehyun Chung, Seungyong Baek, Joungho Kim","doi":"10.1109/EPEP.2003.1250047","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250047","url":null,"abstract":"Even though point to point transmission technique is the best solution for high speed data transmission, there still exist special signals that should drive multiple loads using H-tree to reduce skew and keep good signal quality at the same time. This paper shows problems of a current H-tree structure and suggests a new H-tree structure which is ISI(Inter Symbol Interference)-free and cost effective.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116707254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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