Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250054
Huabo Chen, Ji Zheng, J. Fang
A new multipoint moment matching based reduced order modeling approach is proposed to obtain a broadband macro model of complex systems. With the new technique, the least square matrix obtained is better conditioned than that of the AWE-like approach and a high order rational approximation can be achieved to yield a highly accurate broadband model.
{"title":"Multipoint moment matching based model generation for complex systems","authors":"Huabo Chen, Ji Zheng, J. Fang","doi":"10.1109/EPEP.2003.1250054","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250054","url":null,"abstract":"A new multipoint moment matching based reduced order modeling approach is proposed to obtain a broadband macro model of complex systems. With the new technique, the least square matrix obtained is better conditioned than that of the AWE-like approach and a high order rational approximation can be achieved to yield a highly accurate broadband model.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128698074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250053
D. Saraswat, R. Achar, M. Nakhla
With the continually increasing operating frequencies, complex high-speed package and interconnect modules require characterization based on measured/simulated data. Several efficient algorithms were recently suggested for macromodeling of such data to enable transient analysis in the presence of external circuit elements. One of the difficult issues involved here is the passivity violations associated with the computed macromodel. To address this issue, an efficient algorithm is presented in this paper to enforce passivity for macromodels with passivity violations.
{"title":"Enforcing passivity for rational function based macromodels of tabulated data","authors":"D. Saraswat, R. Achar, M. Nakhla","doi":"10.1109/EPEP.2003.1250053","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250053","url":null,"abstract":"With the continually increasing operating frequencies, complex high-speed package and interconnect modules require characterization based on measured/simulated data. Several efficient algorithms were recently suggested for macromodeling of such data to enable transient analysis in the presence of external circuit elements. One of the difficult issues involved here is the passivity violations associated with the computed macromodel. To address this issue, an efficient algorithm is presented in this paper to enforce passivity for macromodels with passivity violations.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114900207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/epep.2003.1249988
G. Katopis, W. Becker, H. Harrer
In this paper we describe the application of the blade packaging concept to the z-series of e-servers. The advantages of such packaging architecture are highlighted and the challenges for the system performance are identified. The physical and electrical attributes of the five types of Buses required to support processing operating frequency of 1.2 GHz in an SMP (Symmetric Multi-Processing) architecture with up to 64 PU (Processing Units) are tabulated. The evolution of the I/O circuits for each of these Buses is described along with the Bus cycle time and bandwidth trends.
{"title":"T-REX, a blade packaging architecture for mainframe servers","authors":"G. Katopis, W. Becker, H. Harrer","doi":"10.1109/epep.2003.1249988","DOIUrl":"https://doi.org/10.1109/epep.2003.1249988","url":null,"abstract":"In this paper we describe the application of the blade packaging concept to the z-series of e-servers. The advantages of such packaging architecture are highlighted and the challenges for the system performance are identified. The physical and electrical attributes of the five types of Buses required to support processing operating frequency of 1.2 GHz in an SMP (Symmetric Multi-Processing) architecture with up to 64 PU (Processing Units) are tabulated. The evolution of the I/O circuits for each of these Buses is described along with the Bus cycle time and bandwidth trends.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122333895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/epep.2003.1249987
H. P. Hofstee
Power is becoming the most significant limiter of processor performance, and increasing the ratio of logic versus cache transistors, as compared to the traditional roadmap, makes the situation worse. Also, the 5/spl times/ additional increase in I/O bandwidth requires significant extra power, putting a premium on signaling techniques that combine high per pin frequencies with low power per Gbit/s: However, limiting frequency improvements - to only 20% per year makes the situation better compared to historical growth rates and especially limits hot spot power densities. Nevertheless, the challenge to improve power efficiency, power delivery, and heat removal remains significant. Though mostly intended as a challenge to the EPEP community; my talk will also cover some of the advances made on addressing the main challenges and discusses some approaches to system and package design that may-help meet the challenges that remain.
{"title":"Architecting interconnect","authors":"H. P. Hofstee","doi":"10.1109/epep.2003.1249987","DOIUrl":"https://doi.org/10.1109/epep.2003.1249987","url":null,"abstract":"Power is becoming the most significant limiter of processor performance, and increasing the ratio of logic versus cache transistors, as compared to the traditional roadmap, makes the situation worse. Also, the 5/spl times/ additional increase in I/O bandwidth requires significant extra power, putting a premium on signaling techniques that combine high per pin frequencies with low power per Gbit/s: However, limiting frequency improvements - to only 20% per year makes the situation better compared to historical growth rates and especially limits hot spot power densities. Nevertheless, the challenge to improve power efficiency, power delivery, and heat removal remains significant. Though mostly intended as a challenge to the EPEP community; my talk will also cover some of the advances made on addressing the main challenges and discusses some approaches to system and package design that may-help meet the challenges that remain.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130220855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EPEP.2003.1250024
K. Araki, H. Kubota, T. Watanabe, H. Asai
This paper describes a full-wave EMI (electromagnetic interference) simulator BLESS (Board Layout Evaluation and Suggestion System) for the printed wiring board (PWB) design with the consideration of electromagnetic compatibility (EMC) and power/signal integrity. This simulator is based on the parallel-distributed finite-difference time-domain (FDTD) method, and works on a PC-cluster. The accuracy of analysis by BLESS is verified in comparison with s-parameter measurements. Using the simulator, the full-wave analysis of the multi-layer PWB in a commercial digital still camera is demonstrated. With the aid of what-if analysis results, PWB design can be verified and optimized with less number of trial productions.
本文介绍了一种全波电磁干扰模拟器BLESS (Board Layout Evaluation and Suggestion System)，用于考虑电磁兼容性(EMC)和电源/信号完整性的印刷线路板设计。该仿真器基于并行分布时域有限差分(FDTD)方法，工作在pc机集群上。通过与s参数测量的比较，验证了BLESS分析的准确性。利用该仿真器，对商用数码相机中多层印制电路板进行了全波分析。利用假设分析结果，可以在较少的试制次数下验证和优化压路板设计。
{"title":"What-if analyses of multi-layer PWB embedded in the digital still camera with parallel-distributed FDTD-based simulator \"BLESS\"","authors":"K. Araki, H. Kubota, T. Watanabe, H. Asai","doi":"10.1109/EPEP.2003.1250024","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250024","url":null,"abstract":"This paper describes a full-wave EMI (electromagnetic interference) simulator BLESS (Board Layout Evaluation and Suggestion System) for the printed wiring board (PWB) design with the consideration of electromagnetic compatibility (EMC) and power/signal integrity. This simulator is based on the parallel-distributed finite-difference time-domain (FDTD) method, and works on a PC-cluster. The accuracy of analysis by BLESS is verified in comparison with s-parameter measurements. Using the simulator, the full-wave analysis of the multi-layer PWB in a commercial digital still camera is demonstrated. With the aid of what-if analysis results, PWB design can be verified and optimized with less number of trial productions.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128820078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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