Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412151
E. G. Colgan, B. Furman, M. Gaynes, W. Graham, N. LaBianca, J. H. Magerlein, R. J. Polastre, M. B. Rothwell, R. J. Bezama, R. Choudhary, K. Marston, H. Toy, J. Wakil, J. Zitz, R. Schmidt, Ibm Poughkeepsie
The paper describes a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors. Through the use of multiple heat exchanger zones and optimized cooler fin designs, a unit thermal resistance of 10.5 C-mm/sup 2//W from the cooler surface to the inlet water was demonstrated with a fluid pressure drop of less than 35 kPa. Further, cooling of a thermal test chip with a microchannel cooler bonded to it packaged in a single chip module was also demonstrated for a chip power density greater than 300 W/cm/sup 2/. Coolers of this design should be able to cool chips with average power densities of 400 W/cm/sup 2/ or more.
{"title":"A practical implementation of silicon microchannel coolers for high power chips","authors":"E. G. Colgan, B. Furman, M. Gaynes, W. Graham, N. LaBianca, J. H. Magerlein, R. J. Polastre, M. B. Rothwell, R. J. Bezama, R. Choudhary, K. Marston, H. Toy, J. Wakil, J. Zitz, R. Schmidt, Ibm Poughkeepsie","doi":"10.1109/STHERM.2005.1412151","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412151","url":null,"abstract":"The paper describes a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors. Through the use of multiple heat exchanger zones and optimized cooler fin designs, a unit thermal resistance of 10.5 C-mm/sup 2//W from the cooler surface to the inlet water was demonstrated with a fluid pressure drop of less than 35 kPa. Further, cooling of a thermal test chip with a microchannel cooler bonded to it packaged in a single chip module was also demonstrated for a chip power density greater than 300 W/cm/sup 2/. Coolers of this design should be able to cool chips with average power densities of 400 W/cm/sup 2/ or more.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115531454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412159
R. A. Smith, R.J. Culharn
A critical property in understanding and accurately predicting the thermal resistance of polymer-like thermal interface joints in micro-electronic cooling applications is the bulk thermal conductivity of thermal interface materials (TIMs). A unique experimental test stand was developed and validated which accurately measures the in-situ thickness of a TIM sample in a vacuum during thermal resistance testing. The system has a resolution capability of /spl plusmn/ 1.0 /spl mu/m and is designed in such a manner as to continuously measure the true relative deflection of a TIM sample taking into account any mechanical and/or thermal deflections of the entire test stand. The data and analysis demonstrate that applying the current American standard test method (ASTM) ASTM D 5470 without accounting for in-situ thickness deviations can result in over estimating the bulk thermal conductivities for these types of materials by as much as 40%. These types of errors in fundamental material properties can cause the over-prediction of thermal heat flux in a system and an under-prediction of the temperatures of the system.
了解和准确预测微电子冷却应用中类聚合物热界面接头热阻的关键性质是热界面材料(TIMs)的体导热系数。开发并验证了一种独特的实验测试台，该测试台在热阻测试过程中可以准确地测量真空中TIM样品的原位厚度。该系统的分辨率为/spl plusmn/ 1.0 /spl mu/m，其设计方式是考虑到整个试验台的任何机械和/或热挠度，连续测量TIM样品的真实相对挠度。数据和分析表明，在不考虑原位厚度偏差的情况下，应用当前的美国标准测试方法(ASTM) ASTM D 5470可能导致对这些类型材料的体热导率的高估高达40%。这些类型的基本材料性质的误差会导致系统中热通量的过度预测和系统温度的不足预测。
{"title":"In-situ thickness method of measuring thermo-physical properties of polymer-like thermal interface materials [microelectronics cooling applications]","authors":"R. A. Smith, R.J. Culharn","doi":"10.1109/STHERM.2005.1412159","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412159","url":null,"abstract":"A critical property in understanding and accurately predicting the thermal resistance of polymer-like thermal interface joints in micro-electronic cooling applications is the bulk thermal conductivity of thermal interface materials (TIMs). A unique experimental test stand was developed and validated which accurately measures the in-situ thickness of a TIM sample in a vacuum during thermal resistance testing. The system has a resolution capability of /spl plusmn/ 1.0 /spl mu/m and is designed in such a manner as to continuously measure the true relative deflection of a TIM sample taking into account any mechanical and/or thermal deflections of the entire test stand. The data and analysis demonstrate that applying the current American standard test method (ASTM) ASTM D 5470 without accounting for in-situ thickness deviations can result in over estimating the bulk thermal conductivities for these types of materials by as much as 40%. These types of errors in fundamental material properties can cause the over-prediction of thermal heat flux in a system and an under-prediction of the temperatures of the system.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116033816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/TCAPT.2007.897993
M. R. Abel, T. L. Wright, W. King, S. Graham
The effects of temperature and stress on the Raman shift in single crystal silicon and polycrystalline silicon films were calibrated. Polysilicon films were grown by LPCVD using a range of temperatures to produce amorphous and crystalline materials followed by doping and annealing. The dependencies of the linear coefficients were related to the polysilicon microstructure using AFM surface scans to determine any possible links. Finally, the technique was utilized in measuring the temperature distribution in a thermal MEMS cantilever device with micron spatial resolution.
{"title":"Thermal metrology of silicon microstructures using Raman spectroscopy","authors":"M. R. Abel, T. L. Wright, W. King, S. Graham","doi":"10.1109/TCAPT.2007.897993","DOIUrl":"https://doi.org/10.1109/TCAPT.2007.897993","url":null,"abstract":"The effects of temperature and stress on the Raman shift in single crystal silicon and polycrystalline silicon films were calibrated. Polysilicon films were grown by LPCVD using a range of temperatures to produce amorphous and crystalline materials followed by doping and annealing. The dependencies of the linear coefficients were related to the polysilicon microstructure using AFM surface scans to determine any possible links. Finally, the technique was utilized in measuring the temperature distribution in a thermal MEMS cantilever device with micron spatial resolution.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123677888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412152
S. Kandlikar, H. Upadhye
The high heat transfer coefficients in microchannels are attractive for direct cooling of computer chips requiring high heat-flux removal. However, this is associated with a severe pressure drop penalty. Channel size optimization therefore becomes necessary in selecting an appropriate channel geometry configuration. As the heat flux increases beyond about 2 MW/m/sup 2/, the heat transfer and pressure drop characteristics of the plain channels dictate the use of turbulent flow through the channels, which suffers from an excessive pressure drop penalty. It therefore becomes essential to incorporate enhancement features in the microchannels and multiple passes with shorter flow lengths to provide the desired solution. Results obtained from a theoretical analysis are presented as parametric plots for the heat transfer and pressure drop performance of a 10 mm/spl times/10 mm silicon chip incorporating plain microchannels. Enhanced microchannels with offset strip fins in single-pass and split-flow arrangements are also investigated. The results show that the enhanced structures are capable of dissipating heat fluxes extending beyond 3 MW/m/sup 2/ using water as the coolant in a split-flow arrangement with a core pressure drop of around 35 kPa.
{"title":"Extending the heat flux limit with enhanced microchannels in direct single-phase cooling of computer chips","authors":"S. Kandlikar, H. Upadhye","doi":"10.1109/STHERM.2005.1412152","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412152","url":null,"abstract":"The high heat transfer coefficients in microchannels are attractive for direct cooling of computer chips requiring high heat-flux removal. However, this is associated with a severe pressure drop penalty. Channel size optimization therefore becomes necessary in selecting an appropriate channel geometry configuration. As the heat flux increases beyond about 2 MW/m/sup 2/, the heat transfer and pressure drop characteristics of the plain channels dictate the use of turbulent flow through the channels, which suffers from an excessive pressure drop penalty. It therefore becomes essential to incorporate enhancement features in the microchannels and multiple passes with shorter flow lengths to provide the desired solution. Results obtained from a theoretical analysis are presented as parametric plots for the heat transfer and pressure drop performance of a 10 mm/spl times/10 mm silicon chip incorporating plain microchannels. Enhanced microchannels with offset strip fins in single-pass and split-flow arrangements are also investigated. The results show that the enhanced structures are capable of dissipating heat fluxes extending beyond 3 MW/m/sup 2/ using water as the coolant in a split-flow arrangement with a core pressure drop of around 35 kPa.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127580051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412198
O. Steffens, P. Szabó, M. Lenz, G. Farkas
High-power semiconductor packages typically exhibit a 3D heat flow, resulting in large lateral changes in chip and case surface temperature. For single-chip devices we propose to use an unambiguous definition for the junction-to-case thermal resistance as a key parameter, based on a transient measurement technique with much higher repeatability, also for very low thermal resistances compared to a two-point thermal resistance measurement. The technique is illustrated on thermal transient measurements of power MOSFETs. A comparison between different thermal coupling to the ambient is used to demonstrate the method's capability to reveal even subtle internal details of the package. The concept is extended to multichip and stacked-chip structures, where transfer impedances have to be introduced. Here, the dynamic properties of the package are important and complex impedance mapping is the proper way to characterize the package.
{"title":"Thermal transient characterization methodology for single-chip and stacked structures","authors":"O. Steffens, P. Szabó, M. Lenz, G. Farkas","doi":"10.1109/STHERM.2005.1412198","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412198","url":null,"abstract":"High-power semiconductor packages typically exhibit a 3D heat flow, resulting in large lateral changes in chip and case surface temperature. For single-chip devices we propose to use an unambiguous definition for the junction-to-case thermal resistance as a key parameter, based on a transient measurement technique with much higher repeatability, also for very low thermal resistances compared to a two-point thermal resistance measurement. The technique is illustrated on thermal transient measurements of power MOSFETs. A comparison between different thermal coupling to the ambient is used to demonstrate the method's capability to reveal even subtle internal details of the package. The concept is extended to multichip and stacked-chip structures, where transfer impedances have to be introduced. Here, the dynamic properties of the package are important and complex impedance mapping is the proper way to characterize the package.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125540927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412156
T. Brunschwiler, U. Kloter, R. Linderman, H. Rothuizen, B. Michel
We report a simple method to improve bondline formation kinetics by means of a hierarchical set of channels patterned into one of the surfaces. These channel arrays are used to improve the gap squeezing and cooling of single and multiple flip chip electronic modules with highly viscous fluids and thermal pastes. They allow a fast formation of thin gaps or bond lines by reducing the pressure gradient in the thermal interface material as it moves in and out of the gap. Models describing the dynamics of Newtonian fluids in these "hierarchically nested channel" (HNC) interfaces combine squeeze flow and Hagen-Poiseuille theories. Rapid bond line formation is demonstrated for Newtonian fluids and selected particle-filled pastes. Modeling of particle-laden polymeric pastes includes Bingham and Hershel-Bulkley fluid properties. Bond line formation and thermal resistance is improved particularly for high viscosity-high thermal conductivity interface materials created from higher volumetric particle loadings or for thermal interface materials with smaller filler particle diameters.
{"title":"Hierarchically nested channels for fast squeezing interfaces with reduced thermal resistance [IC cooling applications]","authors":"T. Brunschwiler, U. Kloter, R. Linderman, H. Rothuizen, B. Michel","doi":"10.1109/STHERM.2005.1412156","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412156","url":null,"abstract":"We report a simple method to improve bondline formation kinetics by means of a hierarchical set of channels patterned into one of the surfaces. These channel arrays are used to improve the gap squeezing and cooling of single and multiple flip chip electronic modules with highly viscous fluids and thermal pastes. They allow a fast formation of thin gaps or bond lines by reducing the pressure gradient in the thermal interface material as it moves in and out of the gap. Models describing the dynamics of Newtonian fluids in these \"hierarchically nested channel\" (HNC) interfaces combine squeeze flow and Hagen-Poiseuille theories. Rapid bond line formation is demonstrated for Newtonian fluids and selected particle-filled pastes. Modeling of particle-laden polymeric pastes includes Bingham and Hershel-Bulkley fluid properties. Bond line formation and thermal resistance is improved particularly for high viscosity-high thermal conductivity interface materials created from higher volumetric particle loadings or for thermal interface materials with smaller filler particle diameters.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126517093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412157
M. Stern, V. Gektin, S. Pecavar, D. Kearns, T. Chen
High performance thermal greases have been evaluated in three separate environments: ideal laboratory, in situ laboratory, and system mockup testing to better understand how bulk and interfacial thermal properties, in combination with the test vehicles used, effect the resultant thermal performance. The three methodologies are described and measurements on a baseline material reported.
{"title":"Evaluation of high performance thermal greases for CPU package cooling applications","authors":"M. Stern, V. Gektin, S. Pecavar, D. Kearns, T. Chen","doi":"10.1109/STHERM.2005.1412157","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412157","url":null,"abstract":"High performance thermal greases have been evaluated in three separate environments: ideal laboratory, in situ laboratory, and system mockup testing to better understand how bulk and interfacial thermal properties, in combination with the test vehicles used, effect the resultant thermal performance. The three methodologies are described and measurements on a baseline material reported.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127484565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412190
T. Salem, D. Porschet, S. Bayne
As power electronic applications continue to switch higher levels of voltage and current in smaller-sized component packages, the resulting increase in power density requires efficient thermal management. This paper compares the thermal performance for operating a MOSFET on a water-cooled pole-arrayed heat sink versus a novel water-cooled microchannel heat sink. Details are presented on an innovative technique for determining the thermal capacitance modeling parameter for the heat sinks from experimental data.
{"title":"Thermal performance of water-cooled heat sinks: a comparison of two different designs","authors":"T. Salem, D. Porschet, S. Bayne","doi":"10.1109/STHERM.2005.1412190","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412190","url":null,"abstract":"As power electronic applications continue to switch higher levels of voltage and current in smaller-sized component packages, the resulting increase in power density requires efficient thermal management. This paper compares the thermal performance for operating a MOSFET on a water-cooled pole-arrayed heat sink versus a novel water-cooled microchannel heat sink. Details are presented on an innovative technique for determining the thermal capacitance modeling parameter for the heat sinks from experimental data.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126205618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412187
D. Borca-Tasciuc, L. Pietruszka, T. Borca-Tasciuc, R. Vajtai, P. Ajayan
This work reports temperature-dependent thermal conductivity, specific heat and thermal diffusivity measurements of multi-wall carbon nanotube strands. Thermal property characterization has been carried out along the carbon nanotube alignment direction with an AC driven, self-heating 3/spl omega/ method over a temperature range from 90-310K. The specific heat and thermal conductivity increases linearly with temperature. The thermal diffusivity is 5/spl times/10/sup -6/ m/sup 2/s/sup -1/ at room temperature and is nearly constant across the temperature range, slightly increasing at lower temperatures. The observed trends in specific heat and thermal conductivity are similar with other published multi-wall carbon nanotube data. The measured thermal diffusivity agrees with data reported elsewhere for the same MWCNT material measured by a different technique.
{"title":"Thermal transport measurements in multi-wall carbon nanotube strands using the 3/spl omega/ method","authors":"D. Borca-Tasciuc, L. Pietruszka, T. Borca-Tasciuc, R. Vajtai, P. Ajayan","doi":"10.1109/STHERM.2005.1412187","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412187","url":null,"abstract":"This work reports temperature-dependent thermal conductivity, specific heat and thermal diffusivity measurements of multi-wall carbon nanotube strands. Thermal property characterization has been carried out along the carbon nanotube alignment direction with an AC driven, self-heating 3/spl omega/ method over a temperature range from 90-310K. The specific heat and thermal conductivity increases linearly with temperature. The thermal diffusivity is 5/spl times/10/sup -6/ m/sup 2/s/sup -1/ at room temperature and is nearly constant across the temperature range, slightly increasing at lower temperatures. The observed trends in specific heat and thermal conductivity are similar with other published multi-wall carbon nanotube data. The measured thermal diffusivity agrees with data reported elsewhere for the same MWCNT material measured by a different technique.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129854405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412188
D. Luerssen, J. Hudgings, P. Mayer, Rajeev J Ram
We present 2D temperature measurements with 250nm spatial and 10mK temperature resolution using thermoreflectance microscopy. We measure the temperature-induced reflectivity change with an accuracy better than /spl Delta/R/R=2/spl middot/10/sup -6/ using a 12bit CCD, which has a quantization limitation of /spl Delta/R/R=2.5/spl middot/10/sup -4/. The dynamic range is thus expanded from 72dB to 114dB, equivalent to more than 18 effective bits. We quantitatively explain this dramatic improvement using the concept of stochastic resonance. In addition, we optimize the thermoreflectance calibration coefficient K/spl equiv/R/sup -1//spl middot/ R/T by matching the illumination wavelength to a combination of the thermoreflectance coefficient spectrum R/T and the reflectivity spectrum R. For gold illuminated with a 467nm LED, we obtain the extraordinarily large value /spl kappa/ =3.3/spl middot/10/sup -4/ K/sup -1/. This calibration coefficient yields a temperature resolution of better than 10mK.
{"title":"Nanoscale thermoreflectance with 10mK temperature resolution using stochastic resonance","authors":"D. Luerssen, J. Hudgings, P. Mayer, Rajeev J Ram","doi":"10.1109/STHERM.2005.1412188","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412188","url":null,"abstract":"We present 2D temperature measurements with 250nm spatial and 10mK temperature resolution using thermoreflectance microscopy. We measure the temperature-induced reflectivity change with an accuracy better than /spl Delta/R/R=2/spl middot/10/sup -6/ using a 12bit CCD, which has a quantization limitation of /spl Delta/R/R=2.5/spl middot/10/sup -4/. The dynamic range is thus expanded from 72dB to 114dB, equivalent to more than 18 effective bits. We quantitatively explain this dramatic improvement using the concept of stochastic resonance. In addition, we optimize the thermoreflectance calibration coefficient K/spl equiv/R/sup -1//spl middot/ R/T by matching the illumination wavelength to a combination of the thermoreflectance coefficient spectrum R/T and the reflectivity spectrum R. For gold illuminated with a 467nm LED, we obtain the extraordinarily large value /spl kappa/ =3.3/spl middot/10/sup -4/ K/sup -1/. This calibration coefficient yields a temperature resolution of better than 10mK.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130405098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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