Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412167
P. Rodgers, V. Eveloy, Michael Pecht
Despite the perception that the limits of air-cooling have been reached, this paper reviews approaches that could maintain the effectiveness of this technology. Key thermal management areas that need to be addressed are discussed including heat sink design and analysis, interface thermal resistance minimization, heat spreading, fan performance, hybrid thermal management, heat sink surface fouling, and sustainability.
{"title":"Limits of air-cooling: status and challenges","authors":"P. Rodgers, V. Eveloy, Michael Pecht","doi":"10.1109/STHERM.2005.1412167","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412167","url":null,"abstract":"Despite the perception that the limits of air-cooling have been reached, this paper reviews approaches that could maintain the effectiveness of this technology. Key thermal management areas that need to be addressed are discussed including heat sink design and analysis, interface thermal resistance minimization, heat spreading, fan performance, hybrid thermal management, heat sink surface fouling, and sustainability.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131559820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412172
A. Nabi, A. Asias
A novel experimental technique for the characterization of the performance of thermoelectric coolers (TECs) is presented. The test setup is simple and enables validation of TEC performance in a wide temperature range, especially, at the high temperatures required for modem high-temperature TECs. The proposed experimental setup was found to perform remarkably well in characterizing several TECs of two vendors. The TECs under the present study showed markedly different performance than predicted using the vendors recommended equations and thermophysical properties. It was demonstrated that the major cause for the observed deviations was related to a substantial difference between the thermophysical properties provided by the vendors and the actual effective properties of the assembled TECs. Especially the effective Seebeck coefficient measured in the present study was lower by almost 25% than for the pure material.
{"title":"A simple experimental technique for the characterization of the performance of thermoelectric-coolers beyond 100/spl deg/C","authors":"A. Nabi, A. Asias","doi":"10.1109/STHERM.2005.1412172","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412172","url":null,"abstract":"A novel experimental technique for the characterization of the performance of thermoelectric coolers (TECs) is presented. The test setup is simple and enables validation of TEC performance in a wide temperature range, especially, at the high temperatures required for modem high-temperature TECs. The proposed experimental setup was found to perform remarkably well in characterizing several TECs of two vendors. The TECs under the present study showed markedly different performance than predicted using the vendors recommended equations and thermophysical properties. It was demonstrated that the major cause for the observed deviations was related to a substantial difference between the thermophysical properties provided by the vendors and the actual effective properties of the assembled TECs. Especially the effective Seebeck coefficient measured in the present study was lower by almost 25% than for the pure material.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128592397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412179
T. Nozu
Thermal characterization of InGaP/GaAs HBT power amplifiers for CDMA cellular phone handsets has been demonstrated on the basis of DC measurements of the HBTs and 3D finite element modeling, which made the treatment of non-uniform heat flow in this problem possible. Evaluation of conductive adhesives in the actual power amplifier environment has also been carried out. The finite element modeling including thermal contact resistance was applied to the HBTs with various numbers of emitter fingers and good agreement with measurements was obtained. For an adhesive with a high thermal conductance, it was found that 1/3 of the total thermal resistance of the power amplifier was attributable to the contact thermal resistance around GaAs/adhesive/heat sink bond line and that the bulk thermal contribution was negligible.
{"title":"Thermal characterization of power amplifiers for CDMA cellular phone applications","authors":"T. Nozu","doi":"10.1109/STHERM.2005.1412179","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412179","url":null,"abstract":"Thermal characterization of InGaP/GaAs HBT power amplifiers for CDMA cellular phone handsets has been demonstrated on the basis of DC measurements of the HBTs and 3D finite element modeling, which made the treatment of non-uniform heat flow in this problem possible. Evaluation of conductive adhesives in the actual power amplifier environment has also been carried out. The finite element modeling including thermal contact resistance was applied to the HBTs with various numbers of emitter fingers and good agreement with measurements was obtained. For an adhesive with a high thermal conductance, it was found that 1/3 of the total thermal resistance of the power amplifier was attributable to the contact thermal resistance around GaAs/adhesive/heat sink bond line and that the bulk thermal contribution was negligible.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124712657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412189
L. Li, R. Coccioli, K. Nary, P. Canfield
A multi-scale modeling approach is proposed and employed to investigate thermal issues in GaAs MMIC. Thermal analysis down to the signal transistor level was made possible with the development of this approach using the finite element technique. The multi-scale modeling results are then verified with an infrared temperature measurement technique (infrared micro-thermal imaging technique). Both modeling and experiment results have shown that due to its intrinsic low thermal conductivity, self-heating of the GaAs MMIC chip is very localized around the FET gate fingers especially concentrated within the output stage of the GaAs RF device. Thermal management solutions at both the package and system level are needed to keep chip operating temperature under the maximum allowable channel temperature of the device. Steps involved with the multi-scale thermal modeling and parameters affecting thermal characteristics of GaAs MMIC are also discussed.
{"title":"Multi-scale thermal analysis of GaAs RF device","authors":"L. Li, R. Coccioli, K. Nary, P. Canfield","doi":"10.1109/STHERM.2005.1412189","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412189","url":null,"abstract":"A multi-scale modeling approach is proposed and employed to investigate thermal issues in GaAs MMIC. Thermal analysis down to the signal transistor level was made possible with the development of this approach using the finite element technique. The multi-scale modeling results are then verified with an infrared temperature measurement technique (infrared micro-thermal imaging technique). Both modeling and experiment results have shown that due to its intrinsic low thermal conductivity, self-heating of the GaAs MMIC chip is very localized around the FET gate fingers especially concentrated within the output stage of the GaAs RF device. Thermal management solutions at both the package and system level are needed to keep chip operating temperature under the maximum allowable channel temperature of the device. Steps involved with the multi-scale thermal modeling and parameters affecting thermal characteristics of GaAs MMIC are also discussed.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129457481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412194
Xuejiao Hu, A. Padilla, Jun Xu, T. Fisher, K. Goodson
An exploratory thermal interface structure, made of vertically oriented carbon nanotubes directly grown on a silicon substrate, has been thermally characterized using a 3-omega method. The effective thermal conductivities of the CNT sample, including the effects of voids, are found to be 74 W/m/spl middot/K to 83 W/m/spl middot/K in the temperature range of 295K to 323K, one order higher than that of the best thermal greases or phase change materials. This suggests that the vertically oriented CNT potentially can be a promising next-generation thermal interface solution. However, fairly large thermal resistances were observed at the interfaces between the CNT samples and the experimental contact. Minimizing these contact resistances is critical for the application of these materials.
{"title":"Thermal characterization of vertically-oriented carbon nanotubes on silicon","authors":"Xuejiao Hu, A. Padilla, Jun Xu, T. Fisher, K. Goodson","doi":"10.1109/STHERM.2005.1412194","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412194","url":null,"abstract":"An exploratory thermal interface structure, made of vertically oriented carbon nanotubes directly grown on a silicon substrate, has been thermally characterized using a 3-omega method. The effective thermal conductivities of the CNT sample, including the effects of voids, are found to be 74 W/m/spl middot/K to 83 W/m/spl middot/K in the temperature range of 295K to 323K, one order higher than that of the best thermal greases or phase change materials. This suggests that the vertically oriented CNT potentially can be a promising next-generation thermal interface solution. However, fairly large thermal resistances were observed at the interfaces between the CNT samples and the experimental contact. Minimizing these contact resistances is critical for the application of these materials.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"280 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132235847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412182
S.B. Park, R. Joshi, B. Sammakia
Numerical and experimental techniques were employed to assess the thermomechanical behavior of ceramic and organic flip chip packages under power and accelerated thermal cycling (ATC). In power cycling (PC), the non-uniform temperature distribution and different coefficients of thermal expansion (CTE) of each component make the package deform differently than in the case of ATC. Conventionally, reliability assessment is conducted by ATC that assumes uniform temperature throughout the assembly. This is because ATC is believed to be a worse case condition compared to PC, which is similar to actual field conditions. For ceramic and organic flip chip ball grid array (FC-BGA) packages, numerical simulations of ATC and PC were performed by a combination of computational fluid dynamics (CFD) and finite element analyses (FEA). For PC, CFD analysis was used to extract transient heat transfer coefficients while subsequent thermal and structural FEA was performed with heat generation and heat transfer coefficient from CFD as thermal boundary condition. The numerical simulations were compared with an in-situ, real-time moire/spl acute/ interferometry experiment. It was found that, for certain organic packages, power cycling was the more severe condition that caused solder interconnects to fail earlier than ATC, while ceramic packages fail earlier in ATC than PC. Accordingly, qualification based on ATC testing may overestimate the life of the package.
{"title":"Thermomechanical behavior of organic and ceramic flip chip BGA packages under power cycling","authors":"S.B. Park, R. Joshi, B. Sammakia","doi":"10.1109/STHERM.2005.1412182","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412182","url":null,"abstract":"Numerical and experimental techniques were employed to assess the thermomechanical behavior of ceramic and organic flip chip packages under power and accelerated thermal cycling (ATC). In power cycling (PC), the non-uniform temperature distribution and different coefficients of thermal expansion (CTE) of each component make the package deform differently than in the case of ATC. Conventionally, reliability assessment is conducted by ATC that assumes uniform temperature throughout the assembly. This is because ATC is believed to be a worse case condition compared to PC, which is similar to actual field conditions. For ceramic and organic flip chip ball grid array (FC-BGA) packages, numerical simulations of ATC and PC were performed by a combination of computational fluid dynamics (CFD) and finite element analyses (FEA). For PC, CFD analysis was used to extract transient heat transfer coefficients while subsequent thermal and structural FEA was performed with heat generation and heat transfer coefficient from CFD as thermal boundary condition. The numerical simulations were compared with an in-situ, real-time moire/spl acute/ interferometry experiment. It was found that, for certain organic packages, power cycling was the more severe condition that caused solder interconnects to fail earlier than ATC, while ceramic packages fail earlier in ATC than PC. Accordingly, qualification based on ATC testing may overestimate the life of the package.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124918416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412154
K. Mohseni
Electrical modulation of surface tension is proposed for actuation and pumping of discrete droplets of liquid metals/alloys for active heat management of ICs and removal of hot spots on any solid surface. The proposed technique is based on two observations: (i) by using liquid metals or alloys at room temperature heat transfer rate of a cooling system can be enhanced significantly; (ii) electrowetting is an efficient, low power consumption, and low voltage actuation technique for pumping liquids at micro-scales. Preliminary calculations indicate that more than two orders of magnitude increase in heat transfer rate could be achieved by using liquid metals as compared to systems using water. Liquid velocities above 10 cm/s are observed with extremely low pumping power consumption and at low actuation voltage (/spl sim/2 V). It is expected that digitized electrowetting can offer a viable cooling strategy to achieve the most important objectives of electronic cooling; i.e. minimization of the maximum substrate temperature and reduction of the substrate temperature gradient and removing substrate hot spots.
{"title":"Effective cooling of integrated circuits using liquid alloy electrowetting","authors":"K. Mohseni","doi":"10.1109/STHERM.2005.1412154","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412154","url":null,"abstract":"Electrical modulation of surface tension is proposed for actuation and pumping of discrete droplets of liquid metals/alloys for active heat management of ICs and removal of hot spots on any solid surface. The proposed technique is based on two observations: (i) by using liquid metals or alloys at room temperature heat transfer rate of a cooling system can be enhanced significantly; (ii) electrowetting is an efficient, low power consumption, and low voltage actuation technique for pumping liquids at micro-scales. Preliminary calculations indicate that more than two orders of magnitude increase in heat transfer rate could be achieved by using liquid metals as compared to systems using water. Liquid velocities above 10 cm/s are observed with extremely low pumping power consumption and at low actuation voltage (/spl sim/2 V). It is expected that digitized electrowetting can offer a viable cooling strategy to achieve the most important objectives of electronic cooling; i.e. minimization of the maximum substrate temperature and reduction of the substrate temperature gradient and removing substrate hot spots.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128868959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412191
Guixiang Tan, Yinan Wu
Package thermal performance is determined by package design and its environment in a system. In reality, it is often costly, and sometimes impossible to include all the detailed features of a package into its system thermal management simulation. This is particularly true for stacked packages due to the design complexity. This paper proposes a methodology to realistically model stacked packages by simplifying the detailed package using a compact model with correlated equivalent thermal performance through a design of experiment (DOE) approach. The correlation between the compact model and package detailed model showed a less than 6.5% error under various boundary conditions, and thus becomes a powerful tool for further evaluation and optimization of the package thermal design.
{"title":"Modeling of stacked packaging thermal performance in module/system environment","authors":"Guixiang Tan, Yinan Wu","doi":"10.1109/STHERM.2005.1412191","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412191","url":null,"abstract":"Package thermal performance is determined by package design and its environment in a system. In reality, it is often costly, and sometimes impossible to include all the detailed features of a package into its system thermal management simulation. This is particularly true for stacked packages due to the design complexity. This paper proposes a methodology to realistically model stacked packages by simplifying the detailed package using a compact model with correlated equivalent thermal performance through a design of experiment (DOE) approach. The correlation between the compact model and package detailed model showed a less than 6.5% error under various boundary conditions, and thus becomes a powerful tool for further evaluation and optimization of the package thermal design.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129489870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412192
J. Leija, W. Wei
This paper presents the: requirements necessary to create an adequate thermal design for an advanced mezzanine card. The cooling limits of an AdvancedMC platform in an AdvancedTCA/spl reg/ chassis are determined based on the principles of mass and energy conservation. This article also provides recommendations to optimize the AdvancedMC platform for maximum heat dissipation. In addition, it includes a case study on methods to cool the processor advanced mezzanine card. (PrAMC) utilizing typical single board computer components. Finally, practical cooling limitations are established for microprocessors in the PrAMC form factor. The method presented can be used to determine practical cooling limitations for all other critical components on the platform. It is recommended that AdvancedMC designers use these techniques to determine the cooling limitations for AdvancedMC platform designs. The intent of this document is to instill an understanding that the cooling capacity for AdvancedMC platforms is limited due to system boundary conditions, component limitations, and physics.
{"title":"Thermal design considerations for the advanced mezzanine card form factor","authors":"J. Leija, W. Wei","doi":"10.1109/STHERM.2005.1412192","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412192","url":null,"abstract":"This paper presents the: requirements necessary to create an adequate thermal design for an advanced mezzanine card. The cooling limits of an AdvancedMC platform in an AdvancedTCA/spl reg/ chassis are determined based on the principles of mass and energy conservation. This article also provides recommendations to optimize the AdvancedMC platform for maximum heat dissipation. In addition, it includes a case study on methods to cool the processor advanced mezzanine card. (PrAMC) utilizing typical single board computer components. Finally, practical cooling limitations are established for microprocessors in the PrAMC form factor. The method presented can be used to determine practical cooling limitations for all other critical components on the platform. It is recommended that AdvancedMC designers use these techniques to determine the cooling limitations for AdvancedMC platform designs. The intent of this document is to instill an understanding that the cooling capacity for AdvancedMC platforms is limited due to system boundary conditions, component limitations, and physics.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124463108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412162
C. Patel, C. Bash, R. Sharma, A. Beitelmal, C. Malone
The management of energy as a key resource will be a requirement from an economic and sustainability standpoint for the future computing utility. In addition to billions of computing devices, the miniaturization of semiconductor technologies will push the current power density of the microprocessor core over 200 W/cm/sup 2/ resulting in the use of active heat removal techniques. In order to facilitate thermal management of such high power density sources, and to enable energy efficiency, measured application of active cooling resources will be required. State of the art application of heat removal technologies, applied based on maximum heat load and managed with a lack of knowledge of the overall system requirements, will not suffice. Balanced use of energy to actively remove heat from the source, together with management of heat dissipated from the source, will be necessary to reduce the total cost of ownership of information technology equipment and services. Indeed, based on the current trajectory in chip design, future chips will have the flexibility to scale power, albeit at some performance penalty. This variability in heat generation must be utilized to enable balanced chip performance based on the most efficient provisioning of cooling resources. To enable "right" provisioning of cooling resources, flexibility must be devised at all levels of the heat removal stack - chip, system and data center. The ability to change the temperature and coolant mass flow is the required high level abstraction in this heat removal stack. With these underlying flexibilities in heat generation and heat removal, one can overlay a low-cost sensing network and create a control system that can modulate the cooling resources and work "hand in hand" with a power scheduling mechanism to create an energy aware global computing utility.
{"title":"Smart chip, system and data center enabled by advanced flexible cooling resources","authors":"C. Patel, C. Bash, R. Sharma, A. Beitelmal, C. Malone","doi":"10.1109/STHERM.2005.1412162","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412162","url":null,"abstract":"The management of energy as a key resource will be a requirement from an economic and sustainability standpoint for the future computing utility. In addition to billions of computing devices, the miniaturization of semiconductor technologies will push the current power density of the microprocessor core over 200 W/cm/sup 2/ resulting in the use of active heat removal techniques. In order to facilitate thermal management of such high power density sources, and to enable energy efficiency, measured application of active cooling resources will be required. State of the art application of heat removal technologies, applied based on maximum heat load and managed with a lack of knowledge of the overall system requirements, will not suffice. Balanced use of energy to actively remove heat from the source, together with management of heat dissipated from the source, will be necessary to reduce the total cost of ownership of information technology equipment and services. Indeed, based on the current trajectory in chip design, future chips will have the flexibility to scale power, albeit at some performance penalty. This variability in heat generation must be utilized to enable balanced chip performance based on the most efficient provisioning of cooling resources. To enable \"right\" provisioning of cooling resources, flexibility must be devised at all levels of the heat removal stack - chip, system and data center. The ability to change the temperature and coolant mass flow is the required high level abstraction in this heat removal stack. With these underlying flexibilities in heat generation and heat removal, one can overlay a low-cost sensing network and create a control system that can modulate the cooling resources and work \"hand in hand\" with a power scheduling mechanism to create an energy aware global computing utility.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114544551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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