Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412164
D. Copeland
Cooling of 64-bit servers is constrained by increasing power and decreasing space. Power dissipation of high performance processors is predicted to increase linearly over the next decade. Thermal interface, heat spreading and heatsink-to-ambient convection each provide similar resistances in the thermal path from chip to ambient. One departure from previous practice will be the increasing sensitivity of power dissipation with junction temperature. As leakage current, previously a small contribution to total power dissipation, becomes significant, chip power dissipation will become a stronger function of temperature. Expenditure of energy on enhanced cooling, such as pumped water or vapor-cycle refrigeration, may result in reduced total system power. Recent advances in thermoelectrics could change many assumptions in refrigeration, enabling distributed and localized refrigeration at the processor level with minimum space requirements.
{"title":"64-bit server cooling requirements","authors":"D. Copeland","doi":"10.1109/STHERM.2005.1412164","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412164","url":null,"abstract":"Cooling of 64-bit servers is constrained by increasing power and decreasing space. Power dissipation of high performance processors is predicted to increase linearly over the next decade. Thermal interface, heat spreading and heatsink-to-ambient convection each provide similar resistances in the thermal path from chip to ambient. One departure from previous practice will be the increasing sensitivity of power dissipation with junction temperature. As leakage current, previously a small contribution to total power dissipation, becomes significant, chip power dissipation will become a stronger function of temperature. Expenditure of energy on enhanced cooling, such as pumped water or vapor-cycle refrigeration, may result in reduced total system power. Recent advances in thermoelectrics could change many assumptions in refrigeration, enabling distributed and localized refrigeration at the processor level with minimum space requirements.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"195 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124347749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412183
K. Black, K. Kelly, N. Wright
Increased subthreshold leakage, inherent with decreasing transistor dimensions, has proven to be a manufacturability challenge within many areas of the semiconductor industry. One such challenge is maintaining device thermal stability during the device testing process. By understanding the relationship between subthreshold leakage and device junction temperature, it is possible to determine the thermal characteristics of the device. The thermal characteristics can then be applied to establish optimum conditions for achieving device thermal stability in the most challenging environment of the test process, burn-in. The paper presents a cost and manufacturing resource conscious method for predicting device thermal stability based on device specific data that may be obtained in the existing production test environment.
{"title":"Modeling subthreshold leakage and thermal stability in a production life test environment","authors":"K. Black, K. Kelly, N. Wright","doi":"10.1109/STHERM.2005.1412183","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412183","url":null,"abstract":"Increased subthreshold leakage, inherent with decreasing transistor dimensions, has proven to be a manufacturability challenge within many areas of the semiconductor industry. One such challenge is maintaining device thermal stability during the device testing process. By understanding the relationship between subthreshold leakage and device junction temperature, it is possible to determine the thermal characteristics of the device. The thermal characteristics can then be applied to establish optimum conditions for achieving device thermal stability in the most challenging environment of the test process, burn-in. The paper presents a cost and manufacturing resource conscious method for predicting device thermal stability based on device specific data that may be obtained in the existing production test environment.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121439265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412158
M. Bahrami, M. Yovanovich, J. Culham
Existing models over-predict the thermal contact resistance of conforming rough joints at low contact pressures. However, the applicable pressure range in the microelectronics industry is low due to load constraints. In this paper, a new model is presented which is more suitable for low pressures. The present model assumes plastic deformation at microcontacts. The effect of elastic deformations beneath the microcontacts is determined by superimposing normal deformations in an elastic half-space due to adjacent microcontacts. The model also accounts for the variation of the effective microhardness. A parametric study is conducted to investigate the effects of main contact input parameters on the elastic effect. The study reveals that the elastic deformation effect is an important phenomenon especially in low contact pressures. The present model is compared with experimental data and good agreement is observed at low contact pressures.
{"title":"Thermal contact resistance: effect of elastic deformation [microelectronics packaging]","authors":"M. Bahrami, M. Yovanovich, J. Culham","doi":"10.1109/STHERM.2005.1412158","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412158","url":null,"abstract":"Existing models over-predict the thermal contact resistance of conforming rough joints at low contact pressures. However, the applicable pressure range in the microelectronics industry is low due to load constraints. In this paper, a new model is presented which is more suitable for low pressures. The present model assumes plastic deformation at microcontacts. The effect of elastic deformations beneath the microcontacts is determined by superimposing normal deformations in an elastic half-space due to adjacent microcontacts. The model also accounts for the variation of the effective microhardness. A parametric study is conducted to investigate the effects of main contact input parameters on the elastic effect. The study reveals that the elastic deformation effect is an important phenomenon especially in low contact pressures. The present model is compared with experimental data and good agreement is observed at low contact pressures.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128730474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412165
A. Shah, V. Carey, C. Bash, C. Patel
Chip power consumption is quickly becoming an important issue because of increased electricity costs and thermal management limitations. Existing techniques assess the impact of chip power dissipation by evaluating maximum junction temperature and total power consumption, but only limited information is available about what power profile may be optimal within allowable limits. This paper explores these issues by analyzing chip packages from an exergy perspective. The framework required for such an analysis is developed, and example cases are presented to illustrate application of the technique. Different design choices are explored in the context of traditional thermodynamic efficiencies as well as a recently proposed exergy-based figure-of-merit.
{"title":"Impact of chip power dissipation on thermodynamic performance","authors":"A. Shah, V. Carey, C. Bash, C. Patel","doi":"10.1109/STHERM.2005.1412165","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412165","url":null,"abstract":"Chip power consumption is quickly becoming an important issue because of increased electricity costs and thermal management limitations. Existing techniques assess the impact of chip power dissipation by evaluating maximum junction temperature and total power consumption, but only limited information is available about what power profile may be optimal within allowable limits. This paper explores these issues by analyzing chip packages from an exergy perspective. The framework required for such an analysis is developed, and example cases are presented to illustrate application of the technique. Different design choices are explored in the context of traditional thermodynamic efficiencies as well as a recently proposed exergy-based figure-of-merit.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123782062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412180
Jongsu Park, Y. Park, Yong Kim
Telecommunication equipments are so complex and the components involve so wide range of physical lengths that it is almost impossible to simulate the convection heat transfer of the whole device. Therefore, we performed two-level modeling, system-level analysis and board-level analysis. The two analyses are coupled to each other as a boundary condition in terms of velocity and pressure. We performed board-level and system-level experiments and verified the proposed model.
{"title":"Thermal design and verification of telecommunication equipment","authors":"Jongsu Park, Y. Park, Yong Kim","doi":"10.1109/STHERM.2005.1412180","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412180","url":null,"abstract":"Telecommunication equipments are so complex and the components involve so wide range of physical lengths that it is almost impossible to simulate the convection heat transfer of the whole device. Therefore, we performed two-level modeling, system-level analysis and board-level analysis. The two analyses are coupled to each other as a boundary condition in terms of velocity and pressure. We performed board-level and system-level experiments and verified the proposed model.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126520476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412201
P. Foroughi, V. Benetis, M. Ohadi, Yuan Zhao, J. Lawler
The performance of two micropumps with different electrode designs in liquid N/sub 2/ was investigated in this study. One of the experimental challenges was developing a method for measuring the flow rate of the liquid N/sub 2/. By combining a numerical model of the non-isothermal flow of the liquid N/sub 2/ around the loop and the experimental measurements of the temperatures around the flow loop, the liquid N/sub 2/ flow rates could be determined accurately enough to compare the pumping performance of these micropumps. The first tested micropump had an electrode spacing of 20 /spl mu/m and an electrode pair spacing of 80 /spl mu/m, while the second pump had an electrode spacing of 50 /spl mu/m and electrode-pair spacing of 200 /spl mu/m. The results showed that both micropumps pumped sufficient liquid N/sub 2/ to cool a typical superconductive sensor or other low power device. For both pumps, the pumping capacities increased with increasing EHD voltage. The pump with the smaller electrode spacing generated a higher flow rate at a lower applied voltage. This pump generated flow rates as high as 10 mL/min at an applied voltage of 500 V.
{"title":"Design, testing and optimization of a micropump for cryogenic spot cooling applications","authors":"P. Foroughi, V. Benetis, M. Ohadi, Yuan Zhao, J. Lawler","doi":"10.1109/STHERM.2005.1412201","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412201","url":null,"abstract":"The performance of two micropumps with different electrode designs in liquid N/sub 2/ was investigated in this study. One of the experimental challenges was developing a method for measuring the flow rate of the liquid N/sub 2/. By combining a numerical model of the non-isothermal flow of the liquid N/sub 2/ around the loop and the experimental measurements of the temperatures around the flow loop, the liquid N/sub 2/ flow rates could be determined accurately enough to compare the pumping performance of these micropumps. The first tested micropump had an electrode spacing of 20 /spl mu/m and an electrode pair spacing of 80 /spl mu/m, while the second pump had an electrode spacing of 50 /spl mu/m and electrode-pair spacing of 200 /spl mu/m. The results showed that both micropumps pumped sufficient liquid N/sub 2/ to cool a typical superconductive sensor or other low power device. For both pumps, the pumping capacities increased with increasing EHD voltage. The pump with the smaller electrode spacing generated a higher flow rate at a lower applied voltage. This pump generated flow rates as high as 10 mL/min at an applied voltage of 500 V.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131713112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412204
Satish C. Mohapatra, Daniel Loikits Dynalene
There are several liquid coolants existing today. Among these, some are based on old technologies and the others are based on new advancements. All these liquids have been divided into six chemistries and a methodology has been presented to compare their overall efficiency, which was determined from heat transfer rate as well as pumping power requirements in microchannels. It was found that potassium formate (PF) solution exhibits the highest overall efficiency among the coolant chemistries evaluated. Other factors such as flammability, toxicity, corrosivity and electrical conductivity have been discussed in reference to these coolants. Based on electrical conductivity, liquid coolants have been divided into three categories: (1) liquid in which direct immersion cooling is possible; (2) liquid in which direct immersion is not possible but a leak or a spill will not damage the electronics; and (3) liquid in which neither direct immersion nor leakage is tolerable.
{"title":"Advances in liquid coolant technologies for electronics cooling","authors":"Satish C. Mohapatra, Daniel Loikits Dynalene","doi":"10.1109/STHERM.2005.1412204","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412204","url":null,"abstract":"There are several liquid coolants existing today. Among these, some are based on old technologies and the others are based on new advancements. All these liquids have been divided into six chemistries and a methodology has been presented to compare their overall efficiency, which was determined from heat transfer rate as well as pumping power requirements in microchannels. It was found that potassium formate (PF) solution exhibits the highest overall efficiency among the coolant chemistries evaluated. Other factors such as flammability, toxicity, corrosivity and electrical conductivity have been discussed in reference to these coolants. Based on electrical conductivity, liquid coolants have been divided into three categories: (1) liquid in which direct immersion cooling is possible; (2) liquid in which direct immersion is not possible but a leak or a spill will not damage the electronics; and (3) liquid in which neither direct immersion nor leakage is tolerable.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"30 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133587528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412174
C. Zweben
Thermal management problems are now critical in microelectronic and optoelectronic packaging. In response to the serious limitations of traditional packaging materials, material suppliers are developing an increasing number of new thermal management materials with low coefficients of thermal expansion (CTEs), ultrahigh thermal conductivities (CT), and low densities. There are now 15 low-CTE materials with CT between that of copper (400 W/m-K) and four times that of copper (1600 W/m-K), several of which are being used in production applications. Thermally conductive carbon fibers are being used to reduce the CTEs and increase the CT of printed circuit boards. These materials greatly expand the options of the packaging engineer, making it possible to eliminate heat pipes and fans. This paper provides an overview of the state of the art of advanced packaging materials, including their key properties, state of maturity, applications, manufacturing, cost and lessons learned. We also look at likely future directions, including nanocomposites.
{"title":"Ultrahigh-thermal-conductivity packaging materials","authors":"C. Zweben","doi":"10.1109/STHERM.2005.1412174","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412174","url":null,"abstract":"Thermal management problems are now critical in microelectronic and optoelectronic packaging. In response to the serious limitations of traditional packaging materials, material suppliers are developing an increasing number of new thermal management materials with low coefficients of thermal expansion (CTEs), ultrahigh thermal conductivities (CT), and low densities. There are now 15 low-CTE materials with CT between that of copper (400 W/m-K) and four times that of copper (1600 W/m-K), several of which are being used in production applications. Thermally conductive carbon fibers are being used to reduce the CTEs and increase the CT of printed circuit boards. These materials greatly expand the options of the packaging engineer, making it possible to eliminate heat pipes and fans. This paper provides an overview of the state of the art of advanced packaging materials, including their key properties, state of maturity, applications, manufacturing, cost and lessons learned. We also look at likely future directions, including nanocomposites.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134119250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412196
Jianhua Zhou, Li Shi
Scanning probe microscopy techniques including scanning gate microscopy (SGM) and scanning thermal microscopy (SThM) have been used to investigate electron transport and energy dissipation mechanisms in single-walled carbon nanotube (CNT) electronic devices. An ultra thin (5-10 nm) layer of polystyrene was coated on the device to protect the CNT devices during thermal imaging. A first harmonic ac measurement SThM method has been developed to improve the signal-noise ratio. Our recent results reveal diffusive and dissipative charge transport in a semiconducting single-walled CNT at applied bias as low as 0.1 V. We have also observed uniform heat dissipation in a metallic single-walled carbon nanotube at applied biases above 0.4 V.
{"title":"Scanning thermal microscopy of carbon nanotube electronic devices","authors":"Jianhua Zhou, Li Shi","doi":"10.1109/STHERM.2005.1412196","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412196","url":null,"abstract":"Scanning probe microscopy techniques including scanning gate microscopy (SGM) and scanning thermal microscopy (SThM) have been used to investigate electron transport and energy dissipation mechanisms in single-walled carbon nanotube (CNT) electronic devices. An ultra thin (5-10 nm) layer of polystyrene was coated on the device to protect the CNT devices during thermal imaging. A first harmonic ac measurement SThM method has been developed to improve the signal-noise ratio. Our recent results reveal diffusive and dissipative charge transport in a semiconducting single-walled CNT at applied bias as low as 0.1 V. We have also observed uniform heat dissipation in a metallic single-walled carbon nanotube at applied biases above 0.4 V.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132970768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412155
A. Jain, T. Borca-Tasciuc, A. P. Roday, M. Jensen, S. Kandlikar
Boiling in microchannels is an important candidate for cooling of electronic chips. A crucially important factor in the design of microchannel boiling heat transfer is the critical heat flux (CHF). This work presents the development of a glass microchannel device for quantitative investigations of CHF and visualization of boiling phenomena at microscale. The device is instrumented with heaters and temperature sensors to map the temperature distribution in the axial direction. The use of low thermal conductivity glass reduces the heat conduction losses, and improves the accuracy of CHF values extracted from experimental results. This work presents the fabrication and packaging of a single microchannel device.
{"title":"Development of an instrumented glass microchannel device for critical heat flux visualization and studies [IC cooling applications]","authors":"A. Jain, T. Borca-Tasciuc, A. P. Roday, M. Jensen, S. Kandlikar","doi":"10.1109/STHERM.2005.1412155","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412155","url":null,"abstract":"Boiling in microchannels is an important candidate for cooling of electronic chips. A crucially important factor in the design of microchannel boiling heat transfer is the critical heat flux (CHF). This work presents the development of a glass microchannel device for quantitative investigations of CHF and visualization of boiling phenomena at microscale. The device is instrumented with heaters and temperature sensors to map the temperature distribution in the axial direction. The use of low thermal conductivity glass reduces the heat conduction losses, and improves the accuracy of CHF values extracted from experimental results. This work presents the fabrication and packaging of a single microchannel device.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130493464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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