Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856803
A. Maxim, D. Andreu, J. Boucher
The aim of this paper is to present a new method of building a high accuracy and computational efficient SPICE library for the main existing power semiconductor devices. Its great points are the portability in virtually all the modern SPICE simulators that have behavioral macromodeling capabilities, the high accuracy, comparable with that given by the AHDL and C code models, the full user access to the model's internal equations and variables, and the modular character, that enables the easy development of SPICE models for new power devices using the available elementary behavioral building blocks.
{"title":"A unified high accuracy SPICE library for the power semiconductor devices built with the analog behavioral macromodeling technique","authors":"A. Maxim, D. Andreu, J. Boucher","doi":"10.1109/ISPSD.2000.856803","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856803","url":null,"abstract":"The aim of this paper is to present a new method of building a high accuracy and computational efficient SPICE library for the main existing power semiconductor devices. Its great points are the portability in virtually all the modern SPICE simulators that have behavioral macromodeling capabilities, the high accuracy, comparable with that given by the AHDL and C code models, the full user access to the model's internal equations and variables, and the modular character, that enables the easy development of SPICE models for new power devices using the available elementary behavioral building blocks.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117241689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856808
T. Steiner, R. Sittig
Chances of liquid cooling integrated into power modules were investigated during an extended research project. It turned out that a flowing liquid yields better characteristics than a boiling liquid and that water offers superior thermal properties compared to electrical isolating fluids although the latter would allow to omit the isolating ceramic layer. Experimental investigations as well as numerical simulations revealed that the coefficient of heat transfer from solid to liquid can be increased by more than an order of magnitude compared to usually given numbers. To this goal a suited geometry of flow channels and a sufficiently high velocity of the liquid have to be chosen. A corresponding micro-heat sink for double sided cooling of an IGBT and a diode was constructed. The height of the total setup amounts to about 9 mm and with a 12/spl times/12 mm/sup 2/ test chip a thermal resistance of 0.087 K/W was achieved.
{"title":"IGBT module setup with integrated micro-heat sinks","authors":"T. Steiner, R. Sittig","doi":"10.1109/ISPSD.2000.856808","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856808","url":null,"abstract":"Chances of liquid cooling integrated into power modules were investigated during an extended research project. It turned out that a flowing liquid yields better characteristics than a boiling liquid and that water offers superior thermal properties compared to electrical isolating fluids although the latter would allow to omit the isolating ceramic layer. Experimental investigations as well as numerical simulations revealed that the coefficient of heat transfer from solid to liquid can be increased by more than an order of magnitude compared to usually given numbers. To this goal a suited geometry of flow channels and a sufficiently high velocity of the liquid have to be chosen. A corresponding micro-heat sink for double sided cooling of an IGBT and a diode was constructed. The height of the total setup amounts to about 9 mm and with a 12/spl times/12 mm/sup 2/ test chip a thermal resistance of 0.087 K/W was achieved.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128968256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856772
Shuming Xu, Yuanzheng Zhu, P. Foo, Y.C. Liang, J. Sin
In this paper, a novel LDMOSFET is proposed with low on-resistance and high transconductance. The silicon substrate surface is trenched by using an extra mask, resulting in a folded gate structure. The channel density is doubled in the experiment. With the Folded Gate LDMOS (FG-gate LDMOS) concept, the on-resistance was reduced by 40%, while the transconductance was improved by 80%. The significance of the folded gate concept will be available for CMOS and other MOS-gated devices.
{"title":"Folded gate LDMOS with low on-resistance and high transconductance","authors":"Shuming Xu, Yuanzheng Zhu, P. Foo, Y.C. Liang, J. Sin","doi":"10.1109/ISPSD.2000.856772","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856772","url":null,"abstract":"In this paper, a novel LDMOSFET is proposed with low on-resistance and high transconductance. The silicon substrate surface is trenched by using an extra mask, resulting in a folded gate structure. The channel density is doubled in the experiment. With the Folded Gate LDMOS (FG-gate LDMOS) concept, the on-resistance was reduced by 40%, while the transconductance was improved by 80%. The significance of the folded gate concept will be available for CMOS and other MOS-gated devices.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123414402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856831
P. Bohm, G. Wachutka
This article presents a new approach to the evaluation of the eigendynamics of interconnects encountered in high frequency power converters and high power semiconductor modules. It is based on a three-dimensional transient electromagnetic field analysis under realistic switching conditions which allows to investigate the various distributed parasitic effects caused by short switching times, steep current and voltage gradients and therefore large di/dt. The finite element simulator NM SESES/sup TM/ has been extended by an electromagnetic kernel to solve these problems. The capability of the simulator is demonstrated by some illustrative examples.
{"title":"Modelling and simulation of the transient electromagnetic behavior of high power bus bars under switching conditions","authors":"P. Bohm, G. Wachutka","doi":"10.1109/ISPSD.2000.856831","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856831","url":null,"abstract":"This article presents a new approach to the evaluation of the eigendynamics of interconnects encountered in high frequency power converters and high power semiconductor modules. It is based on a three-dimensional transient electromagnetic field analysis under realistic switching conditions which allows to investigate the various distributed parasitic effects caused by short switching times, steep current and voltage gradients and therefore large di/dt. The finite element simulator NM SESES/sup TM/ has been extended by an electromagnetic kernel to solve these problems. The capability of the simulator is demonstrated by some illustrative examples.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121367447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856827
F. Nallet, A. Sénès, D. Planson, M. Locatelli, J. Chante, D. Renault
This work presents a novel field for solid state power devices: a 4H-SiC specific device is examined as a current limiting device for serial protection application. The device structure is a vertical power MOSFET like with a existing N channel. Its performances is simulated with ISE TCAD tools. A study of its electrothermal behavior is presented, demonstrating the SiC superiority over silicon with regard to this field.
{"title":"Electrical and electrothermal 2D simulations of a 4H-SiC high voltage current limiting device for serial protection applications","authors":"F. Nallet, A. Sénès, D. Planson, M. Locatelli, J. Chante, D. Renault","doi":"10.1109/ISPSD.2000.856827","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856827","url":null,"abstract":"This work presents a novel field for solid state power devices: a 4H-SiC specific device is examined as a current limiting device for serial protection application. The device structure is a vertical power MOSFET like with a existing N channel. Its performances is simulated with ISE TCAD tools. A study of its electrothermal behavior is presented, demonstrating the SiC superiority over silicon with regard to this field.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125240242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856830
F. Hille, L. Hoffmann, H. Schulze, G. Wachutka
We investigated the correlation of the high-level lifetime of platinum-diffused power diodes with the platinum diffusion temperature, varying over a range of 40 K, and the operating temperature, varying from 223 K to 398 K. The high-level lifetime has been extracted from carrier profiles determined by an optimized free carrier absorption technique, assuming a homogeneous lifetime over the base region. We find an exponential dependence of the high-level lifetime on the operating temperature and no dependence of the injection levels under investigation. Therefore, the recombination processes can be properly described by using the Shockley-Read-Hall model in the electrothermal device simulation. The mean high-level-lifetime for a calibrated device simulation is only 20% lower than the experimentally determined one. The simulated carrier distributions are in very good agreement with the experiment if a weak lifetime gradient in the base region is assumed.
{"title":"Carrier lifetime characterization using an optimized free carrier absorption technique","authors":"F. Hille, L. Hoffmann, H. Schulze, G. Wachutka","doi":"10.1109/ISPSD.2000.856830","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856830","url":null,"abstract":"We investigated the correlation of the high-level lifetime of platinum-diffused power diodes with the platinum diffusion temperature, varying over a range of 40 K, and the operating temperature, varying from 223 K to 398 K. The high-level lifetime has been extracted from carrier profiles determined by an optimized free carrier absorption technique, assuming a homogeneous lifetime over the base region. We find an exponential dependence of the high-level lifetime on the operating temperature and no dependence of the injection levels under investigation. Therefore, the recombination processes can be properly described by using the Shockley-Read-Hall model in the electrothermal device simulation. The mean high-level-lifetime for a calibrated device simulation is only 20% lower than the experimentally determined one. The simulated carrier distributions are in very good agreement with the experiment if a weak lifetime gradient in the base region is assumed.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122788064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856776
T. Minato, T. Nitta, A. Uenisi, M. Yano, M. Harada, S. Hine
STM structure makes it possible to break through the Si limit via new RESURF effect in very tight periodic p and n columns repetition by using deep trench technology and trench sidewall ion implantation. In a wide breakdown voltage range from 200 to 1000 V, STM also gives greatly improved electrical characteristics at the cost of only one extra mask step in the DMOS fabrication wafer process procedure.
{"title":"Which is cooler, trench or multi-epitaxy? Cutting edge approach for the silicon limit by the super trench power MOS-FET (STM)","authors":"T. Minato, T. Nitta, A. Uenisi, M. Yano, M. Harada, S. Hine","doi":"10.1109/ISPSD.2000.856776","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856776","url":null,"abstract":"STM structure makes it possible to break through the Si limit via new RESURF effect in very tight periodic p and n columns repetition by using deep trench technology and trench sidewall ion implantation. In a wide breakdown voltage range from 200 to 1000 V, STM also gives greatly improved electrical characteristics at the cost of only one extra mask step in the DMOS fabrication wafer process procedure.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132626635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856839
S. Pendharkar, R. Teggatz, J. Devore, J. Carpenter, T. Efland, C. Tsai
A novel lateral power device structure with a very high degree of ESD (electrostatic discharge) robustness is presented. This device called the SCR-LDMOS is a modification of the lateral LDMOSFET with good on state and blocking characteristics.
{"title":"SCR-LDMOS. A novel LDMOS device with ESD robustness","authors":"S. Pendharkar, R. Teggatz, J. Devore, J. Carpenter, T. Efland, C. Tsai","doi":"10.1109/ISPSD.2000.856839","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856839","url":null,"abstract":"A novel lateral power device structure with a very high degree of ESD (electrostatic discharge) robustness is presented. This device called the SCR-LDMOS is a modification of the lateral LDMOSFET with good on state and blocking characteristics.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"129 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124244601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856821
T. Trajkovic, F. Udrea, P. Waind, G. Amaratunga
Parasitic charge in the passivation layer or at the interface may severely degrade the breakdown capability of high voltage devices. This is attributed to the change of the electric field contours in the presence of the interface charge from an optimal distribution to an unbalanced distribution. A solution to minimise this effect is proposed in this paper. The proposed breakdown termination technique can be used in a wide range of devices such as power MOSFETs, IGBTs or MOS-controlled thyristors and it is especially effective at voltages above 1.2 kV when the n-drift concentration is reduced.
{"title":"The effect of static and dynamic parasitic charge in the termination area of high voltage devices and possible solutions","authors":"T. Trajkovic, F. Udrea, P. Waind, G. Amaratunga","doi":"10.1109/ISPSD.2000.856821","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856821","url":null,"abstract":"Parasitic charge in the passivation layer or at the interface may severely degrade the breakdown capability of high voltage devices. This is attributed to the change of the electric field contours in the presence of the interface charge from an optimal distribution to an unbalanced distribution. A solution to minimise this effect is proposed in this paper. The proposed breakdown termination technique can be used in a wide range of devices such as power MOSFETs, IGBTs or MOS-controlled thyristors and it is especially effective at voltages above 1.2 kV when the n-drift concentration is reduced.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124241315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856820
Y. Bai, A.Q. Huang, X. Li
The theory of junction termination for super junction devices is proposed in this paper. Using this theory, junction termination techniques for super junction structures are developed that achieve over 95% of the ideal breakdown voltage.
{"title":"Junction termination technique for super junction devices","authors":"Y. Bai, A.Q. Huang, X. Li","doi":"10.1109/ISPSD.2000.856820","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856820","url":null,"abstract":"The theory of junction termination for super junction devices is proposed in this paper. Using this theory, junction termination techniques for super junction structures are developed that achieve over 95% of the ideal breakdown voltage.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"164 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127529923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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