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12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)最新文献

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Using "Adaptive resurf" to improve the SOA of LDMOS transistors 采用“自适应回流”技术改善LDMOS晶体管的SOA
P. Hower, J. Lin, S. Merchant, S. Paiva
Measured SOA is compared with simulations for field gap LDMOS transistors. The utility of an n-type "resurf" or "nfield" implant under the field oxide is considered. For a fixed VDS, it is shown that there is an optimum value of nfield dose.
将实测的SOA与场隙LDMOS晶体管的仿真结果进行了比较。在场氧化物下考虑了n型“回流”或“内场”植入物的实用性。对于一个固定的VDS,存在一个最佳的场内剂量值。
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引用次数: 21
A novel vertical deep trench RESURF DMOS (VTR-DMOS) 一种新型的垂直深沟复路DMOS (VTR-DMOS)
J. Glenn, J. Siekkinen
A new super junction (SJ)-DMOS device, the vertical deep trench RESURF DMOS or VTR-DMOS, is proposed. The VTR-DMOS is a conventional vertical N-channel DMOS with a deep trench adjacent to the gate. The trench creates a vertical sidewall into which boron is solid source diffused to form a P-type doping pillar which is charge balanced to the N-type epitaxial drift region. 2-D simulations comparing a VTR-DMOS to a conventional VDMOS indicate a 5.5/spl times/ improvement in silicon-only Rsp for a BVdss>700 V.
提出了一种新型的超级结(SJ)-DMOS器件,即垂直深沟槽RESURF DMOS或VTR-DMOS。VTR-DMOS是一种传统的垂直n沟道DMOS,在栅极附近有一个深沟槽。该沟槽形成一个垂直的侧壁,其中硼作为固体源扩散,形成一个p型掺杂柱,该柱与n型外延漂移区电荷平衡。将VTR-DMOS与传统VDMOS进行对比的二维仿真表明,当BVdss>700 V时,纯硅Rsp提高了5.5倍。
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引用次数: 22
High density, sub 10 m Ohm R/sub dson/ 100 volt N-channel FETs for automotive applications 高密度,小于10 m欧姆R/sub dson/ 100伏n沟道场效应管,用于汽车应用
S. Sobhani, D. Kinzer, L. Ma, D. Asselanis
Presented in this paper are the results of high-density trench designs in producing extremely low R/sub dson/ MOSFETs in the 100 VN voltage class. R.A. products of 110 m/spl Omega/.mm/sup 2/ and 125 m/spl Omega/.mm/sup 2/ (depending on design) at 10 V gate are the lowest reported in the industry. The incentive behind this work is to address the rising need of this class of MOSFETs in Automotive applications.
本文介绍了高密度沟槽设计在100 VN电压等级下生产极低R/sub / mosfet的结果。R.A.产品110m /spl ω /。mm/sup 2/和125 m/spl Omega/。mm/sup 2/(取决于设计)在10v栅极是最低的行业报告。这项工作背后的动机是为了满足汽车应用中对这类mosfet日益增长的需求。
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引用次数: 8
Substrate current protection in smart power IC's 智能功率集成电路中的衬底电流保护
O. Gonnard, G. Charitat, P. Lance, E. Stefanov, M. Suquet, M. Bafleur, N. Mauran, A. Peyre-Lavigne
In this paper, we describe and characterize a parasitic current, called substrate current injection in a SMART POWER technology. This parasitic current occurs when a normally reversed bias diode becomes forward biased and can disrupt the normal IC's functionality. We propose two design solutions able to decrease this parasitic current influence. These solutions, based on 2D simulation and on real-size measurements, are fully compatible with a standard technological process. The first one, consists in a correct guard ring polarization, in this case we can divide by 3 the injected current. The second one, based upon a special alignment for the N buried layer can decrease the parasitic current by a factor of 10.
在本文中,我们描述和表征了一种寄生电流,即SMART POWER技术中的衬底电流注入。当一个正常反向的偏置二极管变成正向偏置时,这种寄生电流就会发生,并且会破坏正常的集成电路的功能。我们提出了两种能够减少寄生电流影响的设计方案。这些基于二维仿真和实际尺寸测量的解决方案与标准技术流程完全兼容。第一个,包含一个正确的保护环极化,在这种情况下,我们可以除以3注入电流。第二种方法,基于对N埋层的特殊排列,可以将寄生电流降低10倍。
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引用次数: 33
An advanced FWD design concept with superior soft reverse recovery characteristics 先进的FWD设计理念,具有优越的软反向恢复特性
M. Nemoto, A. Nishiura, T. Naito, M. Kirisawa, M. Otsuki, Y. Seki
In this paper an improved FWD design concept has been investigated having superior soft reverse recovery behavior, for the first time. The basic concept of the FWD design is a combination of low anode injection efficiency (MPS structure) and inhomogeneous lifetime controlling (platinum) in order to achieve the optimum carrier distributions. From experimental results, the rate of the rise in the cathode voltage (dV/dt) can be dramatically reduced. The new diode exhibits superior characteristics of the soft recovery than that of the conventional MPS diode, especially in the low current turn-on of the IGBT.
本文首次研究了一种改进的FWD设计理念,该设计理念具有优异的软反向恢复性能。FWD设计的基本概念是结合低阳极注入效率(MPS结构)和非均匀寿命控制(铂),以实现最佳载流子分布。从实验结果来看,阴极电压(dV/dt)的上升速率可以显著降低。与传统MPS二极管相比,该二极管具有更好的软恢复特性,特别是在IGBT的小电流导通中。
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引用次数: 11
Resurfed lateral bipolar transistors for high-voltage, high-frequency applications 用于高电压、高频应用的补液侧双极晶体管
G. Cao, M. M. De Souza, E. Narayanan
A high performance 40-V lateral bipolar transistor has been evaluated. The incorporation of the Resurf effect together with a gradually doped collector results in a significant suppression of the Kirk effect. As a result, a cut-off frequency of 7 GHz can be obtained with the resurfed device in comparison to 3.5 GHz for the conventional device with an identical breakdown voltage.
研究了一种高性能的40 v侧双极晶体管。将雷夫效应与逐渐掺杂的集电极结合在一起,可显著抑制柯克效应。因此,与具有相同击穿电压的传统器件的3.5 GHz相比,使用换料器件可以获得7 GHz的截止频率。
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引用次数: 5
Light-triggered thyristors with integrated protection functions 具有集成保护功能的光触发晶闸管
F. Niedernostheide, H. Schulze, J. Dorn, U. Kellner-Werdehausen, D. Westerholt
The main objectives of developments in high-power thyristor converters are to reduce of cost of development and production and increase reliability. This can be achieved by reducing the complexity of thyristor valves through the use of light-triggered thyristors with integrated protection functions, in this paper we report how the required functions have been realized and on the advantages this has for the application.
大功率晶闸管变换器发展的主要目标是降低开发和生产成本,提高可靠性。这可以通过使用具有集成保护功能的光触发晶闸管来降低晶闸管阀的复杂性来实现,在本文中,我们报告了如何实现所需的功能以及这对应用的优势。
{"title":"Light-triggered thyristors with integrated protection functions","authors":"F. Niedernostheide, H. Schulze, J. Dorn, U. Kellner-Werdehausen, D. Westerholt","doi":"10.1109/ISPSD.2000.856822","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856822","url":null,"abstract":"The main objectives of developments in high-power thyristor converters are to reduce of cost of development and production and increase reliability. This can be achieved by reducing the complexity of thyristor valves through the use of light-triggered thyristors with integrated protection functions, in this paper we report how the required functions have been realized and on the advantages this has for the application.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"18 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125765275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A SOI LDMOS/CMOS/BJT technology for fully-integrated RF power amplifiers 用于全集成射频功率放大器的SOI LDMOS/CMOS/BJT技术
Y. Tan, M. Kumar, J. Sin, L. Shi, J. Lau
This paper describes a SOI LDMOS/CMOS/BJT technology which can be used in portable wireless communication applications. This technology allows the complete integration of the front-end and baseband circuits for low-cost/low-power/high-volume single-chip transceiver implementation. The LDMOS transistors (0.35 /spl mu/m channel length, 3.8 /spl mu/m drift length, 4.5 GHz f/sub T/ and 20 V breakdown voltage), CMOS transistors (1.5 /spl mu/m channel length, 0.8/-1.2V threshold voltage), lateral NPN transistor (18 V BV/sub CBO/ and h/sub FE/ of 20), and high Q-factor (up to 6.1 at 900 MHz and 6.5 at 1.8 GHz) on-chip inductors are fabricated. A fully-functional high performance integrated power amplifier for 900 MHz wireless transceiver application is also demonstrated.
本文介绍了一种可用于便携式无线通信的SOI LDMOS/CMOS/BJT技术。该技术允许前端和基带电路的完全集成,以实现低成本/低功耗/大容量的单芯片收发器。制作了LDMOS晶体管(通道长度0.35 /spl μ m,漂移长度3.8 /spl μ m, 4.5 GHz f/sub T/和20 V击穿电压)、CMOS晶体管(通道长度1.5 /spl μ m,阈值电压0.8/-1.2V)、横向NPN晶体管(18 V BV/sub CBO/和h/sub FE/为20)和高q因子(900 MHz时高达6.1,1.8 GHz时高达6.5)片上电感。还演示了一种用于900 MHz无线收发器的全功能高性能集成功率放大器。
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引用次数: 4
Dummy gated radio frequency VDMOSFET with high breakdown voltage and low feedback capacitance 具有高击穿电压和低反馈电容的假门控射频VDMOSFET
Shuming Xu, C. Ren, P. Foo, Y. Liu, Yi Su
In this paper, a novel radio frequency power device called dummy gated VDMOS has been proposed and demonstrated experimentally. The new device is produced using the standard RF VDMOS process technology. An improvement in breakdown voltage by 20% is realized, while the feedback capacitance C/sub rss/ is reduced by three times leading to a desired HF performance and high reliability.
本文提出了一种新型的射频功率器件——虚门控VDMOS,并进行了实验验证。新器件采用标准RF VDMOS工艺技术生产。击穿电压提高了20%,而反馈电容C/sub / rss/降低了三分之一,从而实现了理想的高频性能和高可靠性。
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引用次数: 11
Optimization of the body-diode of power MOSFETs for high efficiency synchronous rectification 大功率mosfet体二极管的高效同步整流优化
J. Zeng, C. F. Wheatley, R. Stokes, C. Kocon, S. Benczkowski
An investigation is performed in this paper upon the impact of the parasitic bipolar junction transistor (BJT) with respect to the body-diode characteristics of the power MOSFET. Simulated and experimental results show that the forward conduction and the reverse recovery characteristics of the body-diode can be improved by enhancing the parasitic BJT, formed by the N/sup +/ source (emitter), P-well (base) and N-epi layer (collector) of power MOSFETs, Furthermore, the trade-off between enhancing the parasitic BJT and retaining the device's unclamped inductive switching (UIS) capability is also addressed.
本文研究了寄生双极结晶体管(BJT)对功率MOSFET体-二极管特性的影响。仿真和实验结果表明,通过增强功率mosfet的N/sup +/源(发射极)、p阱(基极)和N-epi层(集电极)形成的寄生BJT,可以改善体二极管的正向导通和反向恢复特性,并解决了增强寄生BJT与保持器件的非箝位电感开关(UIS)能力之间的权衡问题。
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引用次数: 19
期刊
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)
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