Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856840
P. Hower, J. Lin, S. Merchant, S. Paiva
Measured SOA is compared with simulations for field gap LDMOS transistors. The utility of an n-type "resurf" or "nfield" implant under the field oxide is considered. For a fixed VDS, it is shown that there is an optimum value of nfield dose.
{"title":"Using \"Adaptive resurf\" to improve the SOA of LDMOS transistors","authors":"P. Hower, J. Lin, S. Merchant, S. Paiva","doi":"10.1109/ISPSD.2000.856840","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856840","url":null,"abstract":"Measured SOA is compared with simulations for field gap LDMOS transistors. The utility of an n-type \"resurf\" or \"nfield\" implant under the field oxide is considered. For a fixed VDS, it is shown that there is an optimum value of nfield dose.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114200955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856825
M. Tanaka, S. Teramae, Y. Takahashi, T. Takeda, M. Yamaguchi, T. Ogura, T. Tsunoda, S. Nakao
The 600 V Non-Punch Through (NPT) IGBT which has low on-state voltage (V/sub CE/(sat)) has been developed. This device has a fine pitch trench-gate structure at the emitter side and the collector layer with low injection efficiency at collector side. A novel profile has been installed to realize low injection efficiency and low V/sub CE/(sat). By numerical simulation, it has been confirmed that the trade-off relation between V/sub CE/(sat) and turn-off loss of the trench-gate NPT-IGBT is as good as that of the trench-gate punch through (PT-)IGBT. Adopting the novel profile for the collector structure, the low V/sub CE/(sat) of 1.6 V at 180 A/cm/sup 2/ has been realized for the 600 V trench-gate NPT-IGBT.
研制了具有低导通电压(V/sub CE/(sat))的600 V Non-Punch Through (NPT) IGBT。该装置在发射极侧具有细间距沟栅结构，在集电极侧具有低注入效率的集电极层。安装了一种新颖的剖面，以实现低喷射效率和低V/sub CE/(sat)。通过数值模拟，证实了沟栅NPT-IGBT的V/sub CE/(sat)与关断损耗之间的权衡关系与沟栅冲通(PT-)IGBT一样好。采用新颖的集电极结构，实现了600 V槽栅NPT-IGBT在180 A/cm/sup 2/下1.6 V的低V/sub CE/(sat)。
{"title":"600 V trench-gate NPT-IGBT with excellent low on-state voltage","authors":"M. Tanaka, S. Teramae, Y. Takahashi, T. Takeda, M. Yamaguchi, T. Ogura, T. Tsunoda, S. Nakao","doi":"10.1109/ISPSD.2000.856825","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856825","url":null,"abstract":"The 600 V Non-Punch Through (NPT) IGBT which has low on-state voltage (V/sub CE/(sat)) has been developed. This device has a fine pitch trench-gate structure at the emitter side and the collector layer with low injection efficiency at collector side. A novel profile has been installed to realize low injection efficiency and low V/sub CE/(sat). By numerical simulation, it has been confirmed that the trade-off relation between V/sub CE/(sat) and turn-off loss of the trench-gate NPT-IGBT is as good as that of the trench-gate punch through (PT-)IGBT. Adopting the novel profile for the collector structure, the low V/sub CE/(sat) of 1.6 V at 180 A/cm/sup 2/ has been realized for the 600 V trench-gate NPT-IGBT.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128116792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856846
S. Sobhani, D. Kinzer, L. Ma, D. Asselanis
Presented in this paper are the results of high-density trench designs in producing extremely low R/sub dson/ MOSFETs in the 100 VN voltage class. R.A. products of 110 m/spl Omega/.mm/sup 2/ and 125 m/spl Omega/.mm/sup 2/ (depending on design) at 10 V gate are the lowest reported in the industry. The incentive behind this work is to address the rising need of this class of MOSFETs in Automotive applications.
{"title":"High density, sub 10 m Ohm R/sub dson/ 100 volt N-channel FETs for automotive applications","authors":"S. Sobhani, D. Kinzer, L. Ma, D. Asselanis","doi":"10.1109/ISPSD.2000.856846","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856846","url":null,"abstract":"Presented in this paper are the results of high-density trench designs in producing extremely low R/sub dson/ MOSFETs in the 100 VN voltage class. R.A. products of 110 m/spl Omega/.mm/sup 2/ and 125 m/spl Omega/.mm/sup 2/ (depending on design) at 10 V gate are the lowest reported in the industry. The incentive behind this work is to address the rising need of this class of MOSFETs in Automotive applications.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127884546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856792
J. Zeng, C. F. Wheatley, R. Stokes, C. Kocon, S. Benczkowski
An investigation is performed in this paper upon the impact of the parasitic bipolar junction transistor (BJT) with respect to the body-diode characteristics of the power MOSFET. Simulated and experimental results show that the forward conduction and the reverse recovery characteristics of the body-diode can be improved by enhancing the parasitic BJT, formed by the N/sup +/ source (emitter), P-well (base) and N-epi layer (collector) of power MOSFETs, Furthermore, the trade-off between enhancing the parasitic BJT and retaining the device's unclamped inductive switching (UIS) capability is also addressed.
{"title":"Optimization of the body-diode of power MOSFETs for high efficiency synchronous rectification","authors":"J. Zeng, C. F. Wheatley, R. Stokes, C. Kocon, S. Benczkowski","doi":"10.1109/ISPSD.2000.856792","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856792","url":null,"abstract":"An investigation is performed in this paper upon the impact of the parasitic bipolar junction transistor (BJT) with respect to the body-diode characteristics of the power MOSFET. Simulated and experimental results show that the forward conduction and the reverse recovery characteristics of the body-diode can be improved by enhancing the parasitic BJT, formed by the N/sup +/ source (emitter), P-well (base) and N-epi layer (collector) of power MOSFETs, Furthermore, the trade-off between enhancing the parasitic BJT and retaining the device's unclamped inductive switching (UIS) capability is also addressed.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121618976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856798
O. Gonnard, G. Charitat, P. Lance, E. Stefanov, M. Suquet, M. Bafleur, N. Mauran, A. Peyre-Lavigne
In this paper, we describe and characterize a parasitic current, called substrate current injection in a SMART POWER technology. This parasitic current occurs when a normally reversed bias diode becomes forward biased and can disrupt the normal IC's functionality. We propose two design solutions able to decrease this parasitic current influence. These solutions, based on 2D simulation and on real-size measurements, are fully compatible with a standard technological process. The first one, consists in a correct guard ring polarization, in this case we can divide by 3 the injected current. The second one, based upon a special alignment for the N buried layer can decrease the parasitic current by a factor of 10.
{"title":"Substrate current protection in smart power IC's","authors":"O. Gonnard, G. Charitat, P. Lance, E. Stefanov, M. Suquet, M. Bafleur, N. Mauran, A. Peyre-Lavigne","doi":"10.1109/ISPSD.2000.856798","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856798","url":null,"abstract":"In this paper, we describe and characterize a parasitic current, called substrate current injection in a SMART POWER technology. This parasitic current occurs when a normally reversed bias diode becomes forward biased and can disrupt the normal IC's functionality. We propose two design solutions able to decrease this parasitic current influence. These solutions, based on 2D simulation and on real-size measurements, are fully compatible with a standard technological process. The first one, consists in a correct guard ring polarization, in this case we can divide by 3 the injected current. The second one, based upon a special alignment for the N buried layer can decrease the parasitic current by a factor of 10.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121825685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856850
Shuming Xu, C. Ren, P. Foo, Y. Liu, Yi Su
In this paper, a novel radio frequency power device called dummy gated VDMOS has been proposed and demonstrated experimentally. The new device is produced using the standard RF VDMOS process technology. An improvement in breakdown voltage by 20% is realized, while the feedback capacitance C/sub rss/ is reduced by three times leading to a desired HF performance and high reliability.
{"title":"Dummy gated radio frequency VDMOSFET with high breakdown voltage and low feedback capacitance","authors":"Shuming Xu, C. Ren, P. Foo, Y. Liu, Yi Su","doi":"10.1109/ISPSD.2000.856850","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856850","url":null,"abstract":"In this paper, a novel radio frequency power device called dummy gated VDMOS has been proposed and demonstrated experimentally. The new device is produced using the standard RF VDMOS process technology. An improvement in breakdown voltage by 20% is realized, while the feedback capacitance C/sub rss/ is reduced by three times leading to a desired HF performance and high reliability.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121596901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856790
Y. Tan, M. Kumar, J. Sin, L. Shi, J. Lau
This paper describes a SOI LDMOS/CMOS/BJT technology which can be used in portable wireless communication applications. This technology allows the complete integration of the front-end and baseband circuits for low-cost/low-power/high-volume single-chip transceiver implementation. The LDMOS transistors (0.35 /spl mu/m channel length, 3.8 /spl mu/m drift length, 4.5 GHz f/sub T/ and 20 V breakdown voltage), CMOS transistors (1.5 /spl mu/m channel length, 0.8/-1.2V threshold voltage), lateral NPN transistor (18 V BV/sub CBO/ and h/sub FE/ of 20), and high Q-factor (up to 6.1 at 900 MHz and 6.5 at 1.8 GHz) on-chip inductors are fabricated. A fully-functional high performance integrated power amplifier for 900 MHz wireless transceiver application is also demonstrated.
{"title":"A SOI LDMOS/CMOS/BJT technology for fully-integrated RF power amplifiers","authors":"Y. Tan, M. Kumar, J. Sin, L. Shi, J. Lau","doi":"10.1109/ISPSD.2000.856790","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856790","url":null,"abstract":"This paper describes a SOI LDMOS/CMOS/BJT technology which can be used in portable wireless communication applications. This technology allows the complete integration of the front-end and baseband circuits for low-cost/low-power/high-volume single-chip transceiver implementation. The LDMOS transistors (0.35 /spl mu/m channel length, 3.8 /spl mu/m drift length, 4.5 GHz f/sub T/ and 20 V breakdown voltage), CMOS transistors (1.5 /spl mu/m channel length, 0.8/-1.2V threshold voltage), lateral NPN transistor (18 V BV/sub CBO/ and h/sub FE/ of 20), and high Q-factor (up to 6.1 at 900 MHz and 6.5 at 1.8 GHz) on-chip inductors are fabricated. A fully-functional high performance integrated power amplifier for 900 MHz wireless transceiver application is also demonstrated.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114661428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856802
G. Cao, M. M. De Souza, E. Narayanan
A high performance 40-V lateral bipolar transistor has been evaluated. The incorporation of the Resurf effect together with a gradually doped collector results in a significant suppression of the Kirk effect. As a result, a cut-off frequency of 7 GHz can be obtained with the resurfed device in comparison to 3.5 GHz for the conventional device with an identical breakdown voltage.
{"title":"Resurfed lateral bipolar transistors for high-voltage, high-frequency applications","authors":"G. Cao, M. M. De Souza, E. Narayanan","doi":"10.1109/ISPSD.2000.856802","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856802","url":null,"abstract":"A high performance 40-V lateral bipolar transistor has been evaluated. The incorporation of the Resurf effect together with a gradually doped collector results in a significant suppression of the Kirk effect. As a result, a cut-off frequency of 7 GHz can be obtained with the resurfed device in comparison to 3.5 GHz for the conventional device with an identical breakdown voltage.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121398410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856786
M. Nemoto, A. Nishiura, T. Naito, M. Kirisawa, M. Otsuki, Y. Seki
In this paper an improved FWD design concept has been investigated having superior soft reverse recovery behavior, for the first time. The basic concept of the FWD design is a combination of low anode injection efficiency (MPS structure) and inhomogeneous lifetime controlling (platinum) in order to achieve the optimum carrier distributions. From experimental results, the rate of the rise in the cathode voltage (dV/dt) can be dramatically reduced. The new diode exhibits superior characteristics of the soft recovery than that of the conventional MPS diode, especially in the low current turn-on of the IGBT.
{"title":"An advanced FWD design concept with superior soft reverse recovery characteristics","authors":"M. Nemoto, A. Nishiura, T. Naito, M. Kirisawa, M. Otsuki, Y. Seki","doi":"10.1109/ISPSD.2000.856786","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856786","url":null,"abstract":"In this paper an improved FWD design concept has been investigated having superior soft reverse recovery behavior, for the first time. The basic concept of the FWD design is a combination of low anode injection efficiency (MPS structure) and inhomogeneous lifetime controlling (platinum) in order to achieve the optimum carrier distributions. From experimental results, the rate of the rise in the cathode voltage (dV/dt) can be dramatically reduced. The new diode exhibits superior characteristics of the soft recovery than that of the conventional MPS diode, especially in the low current turn-on of the IGBT.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127932264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856842
T. Laska, M. Munzer, F. Pfirsch, C. Schaeffer, T. Schmidt
By a vertical shrink of the NPT IGBT to a structure with a thin n/sup -/ base and a low doped field stop layer a new IGBT can be realized with drastically reduced overall losses. Especially the combination of the field stop concept with a trench transistor cell results in the almost ideal carrier concentration for a device with minimum on state voltage and lowest switching losses.
{"title":"The Field Stop IGBT (FS IGBT). A new power device concept with a great improvement potential","authors":"T. Laska, M. Munzer, F. Pfirsch, C. Schaeffer, T. Schmidt","doi":"10.1109/ISPSD.2000.856842","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856842","url":null,"abstract":"By a vertical shrink of the NPT IGBT to a structure with a thin n/sup -/ base and a low doped field stop layer a new IGBT can be realized with drastically reduced overall losses. Especially the combination of the field stop concept with a trench transistor cell results in the almost ideal carrier concentration for a device with minimum on state voltage and lowest switching losses.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125726636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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