Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856813
Shanqi Zhao, J. Sin
This paper describes a new packaging technique for improving the thermal and switching characteristics of high power IGBTs. Two patterned DBC (Direct Bond Copper) substrates are used to contact the top and bottom of an IGBT chip. In this way, heat dissipation can take place on both sides of the device, and the wire-bonding between the emitter pad and the package electrode can be eliminated. Experimental results show that this packaging technique can improve the heat dissipation in an IGBT with approximately 84% increase in current handling capability and 33% decrease in steady-state thermal impedance. The packaging technique can also improve the frequency characteristics of the IGBT. At 10 kHz for example, there is approximately 37% increase in current handling capability. The improvement in switching characteristics is about 10% decrease in turn-off delay time and 20% decrease in fall time.
{"title":"Double-side packaged, high power IGBTs for improved thermal and switching characteristics","authors":"Shanqi Zhao, J. Sin","doi":"10.1109/ISPSD.2000.856813","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856813","url":null,"abstract":"This paper describes a new packaging technique for improving the thermal and switching characteristics of high power IGBTs. Two patterned DBC (Direct Bond Copper) substrates are used to contact the top and bottom of an IGBT chip. In this way, heat dissipation can take place on both sides of the device, and the wire-bonding between the emitter pad and the package electrode can be eliminated. Experimental results show that this packaging technique can improve the heat dissipation in an IGBT with approximately 84% increase in current handling capability and 33% decrease in steady-state thermal impedance. The packaging technique can also improve the frequency characteristics of the IGBT. At 10 kHz for example, there is approximately 37% increase in current handling capability. The improvement in switching characteristics is about 10% decrease in turn-off delay time and 20% decrease in fall time.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128455749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856779
Sang-Gi Kim, Jongdae Kim, J. Koo, K. Nam, K. Cho
A new trench corner rounding technique has been developed by using pull-back and hydrogen annealing process. This technique provides highly controllable trench corner rounding by micro structure transformation of silicon at the corner of the trench, leading to uniform gate oxide, higher breakdown voltage, and lower leakage current.
{"title":"Trench corner rounding technology using hydrogen annealing for highly reliable trench DMOSFETs","authors":"Sang-Gi Kim, Jongdae Kim, J. Koo, K. Nam, K. Cho","doi":"10.1109/ISPSD.2000.856779","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856779","url":null,"abstract":"A new trench corner rounding technique has been developed by using pull-back and hydrogen annealing process. This technique provides highly controllable trench corner rounding by micro structure transformation of silicon at the corner of the trench, leading to uniform gate oxide, higher breakdown voltage, and lower leakage current.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123473964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856765
I. Omura, T. Demon, Toshiyuki Miyanagi, T. Ogura, H. Ohashi
IEGT's (Injection Enhanced Gate transistors) and HV-IGBT's are inherently unstable inducing harmful current crowding and oscillation among paralleled chips or packages. The instability problem has become crucial in device design and application. This paper will describe the mechanism of the instability and propose effective solutions for device and package design against the problem.
{"title":"IEGT design concept against operation instability and its impact to application","authors":"I. Omura, T. Demon, Toshiyuki Miyanagi, T. Ogura, H. Ohashi","doi":"10.1109/ISPSD.2000.856765","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856765","url":null,"abstract":"IEGT's (Injection Enhanced Gate transistors) and HV-IGBT's are inherently unstable inducing harmful current crowding and oscillation among paralleled chips or packages. The instability problem has become crucial in device design and application. This paper will describe the mechanism of the instability and propose effective solutions for device and package design against the problem.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129091265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856784
Ping Li, Yajuan Su, Mengsi You, Xuening Li
Two types of novel power MOS devices with SiGe/Si heterojunctions are proposed and verified for the first time. The SiGe source RMOS has the characteristics of BV/sub ds/=BV/sub ce0/=BV/sub cb0/ which implies that the performance limitation of a Si RMOS can be overcome. The SiGe anode LIGBT has better performance than the SINFET, but does not have the shortcomings of the latter.
{"title":"Novel power MOS devices with SiGe/Si heterojunctions","authors":"Ping Li, Yajuan Su, Mengsi You, Xuening Li","doi":"10.1109/ISPSD.2000.856784","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856784","url":null,"abstract":"Two types of novel power MOS devices with SiGe/Si heterojunctions are proposed and verified for the first time. The SiGe source RMOS has the characteristics of BV/sub ds/=BV/sub ce0/=BV/sub cb0/ which implies that the performance limitation of a Si RMOS can be overcome. The SiGe anode LIGBT has better performance than the SINFET, but does not have the shortcomings of the latter.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121978952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856818
K. Satoh, K. Morishita, Y. Yamaguchi, N. Hirano, H. Iwamoto, A. Kawakami
At present, switching devices with high performance such as GCT (Gate Commutated Turn-off) thyristor and IGBT which had higher operation voltage than about 4.5 kV have been realized. However, as a freewheeling diode which should realize the suitable recovery performance to the turn-on performance of those switching devices is not successful, they were restricted in the turn-on operation for inverter systems. Therefore, advanced diodes with high operation voltage and soft recovery performance are desired in order to improve the system performance.
{"title":"A newly structured high voltage diode highlighting oscillation free function in recovery process","authors":"K. Satoh, K. Morishita, Y. Yamaguchi, N. Hirano, H. Iwamoto, A. Kawakami","doi":"10.1109/ISPSD.2000.856818","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856818","url":null,"abstract":"At present, switching devices with high performance such as GCT (Gate Commutated Turn-off) thyristor and IGBT which had higher operation voltage than about 4.5 kV have been realized. However, as a freewheeling diode which should realize the suitable recovery performance to the turn-on performance of those switching devices is not successful, they were restricted in the turn-on operation for inverter systems. Therefore, advanced diodes with high operation voltage and soft recovery performance are desired in order to improve the system performance.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128397271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856835
A. Moscatelli, A. Merlini, G. Croce, P. Galbiati, C. Contiero
This paper presents the integration approach followed to implement power LDMOS' up to 60 V into a 0.35 /spl mu/m process technology (BCD6) based on a CMOS plus Flash-Memory platform of equivalent lithography generation, built on a P-over P+ substrate. Experimental results on LDMOS' in terms of on-state specific resistance, off and on-state breakdown voltage, frequency behavior will be described analyzing the interactions between low voltage ULSI platform and high voltage power elements.
{"title":"LDMOS implementation in a 0.35 /spl mu/m BCD technology (BCD6)","authors":"A. Moscatelli, A. Merlini, G. Croce, P. Galbiati, C. Contiero","doi":"10.1109/ISPSD.2000.856835","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856835","url":null,"abstract":"This paper presents the integration approach followed to implement power LDMOS' up to 60 V into a 0.35 /spl mu/m process technology (BCD6) based on a CMOS plus Flash-Memory platform of equivalent lithography generation, built on a P-over P+ substrate. Experimental results on LDMOS' in terms of on-state specific resistance, off and on-state breakdown voltage, frequency behavior will be described analyzing the interactions between low voltage ULSI platform and high voltage power elements.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"466 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133004079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856767
T. Fujii, K. Yoshikawa, T. Koga, A. Nishiura, Y. Takahashi, H. Kakiki, M. Ichijyou, Y. Seki
A 4.5 kV-2000 A Power Pack IGBT (Flat-Packaged Reverse Conducting IGBT) has been developed by use of the PT (Punch-Through) type IGBT chip, the uniform chip parallel connection in the square ceramic package and the advanced multi-collector structure. The high turn off capability of 4500 A (@V/sub CC/=2600 V, T/sub j/=125/spl deg/C) and the short circuit capability of over 15 /spl mu/s (@V/sub CC/=3000 V, T/sub j/=125/spl deg/C) are successfully achieved.
{"title":"4.5 kV-2000 A Power Pack IGBT (ultra high power flat-packaged PT type RC-IGBT)","authors":"T. Fujii, K. Yoshikawa, T. Koga, A. Nishiura, Y. Takahashi, H. Kakiki, M. Ichijyou, Y. Seki","doi":"10.1109/ISPSD.2000.856767","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856767","url":null,"abstract":"A 4.5 kV-2000 A Power Pack IGBT (Flat-Packaged Reverse Conducting IGBT) has been developed by use of the PT (Punch-Through) type IGBT chip, the uniform chip parallel connection in the square ceramic package and the advanced multi-collector structure. The high turn off capability of 4500 A (@V/sub CC/=2600 V, T/sub j/=125/spl deg/C) and the short circuit capability of over 15 /spl mu/s (@V/sub CC/=3000 V, T/sub j/=125/spl deg/C) are successfully achieved.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133735427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856819
L. M. Hillkirk, B. Breitholtz, J. Lutz
The physics of fast recovery 3.3 kV Si power diodes radiation induced recombination centers operating under forward bias at large current densities and high temperatures have been studied both experimentally and by means of computer simulations. In the experimental studies the dynamic I-V characteristics, the surface temperature and the surface potential distribution in the n-base have been measured, while the diodes were being subjected to single 1.3 ms half-sine-wave current pulses having a density in the range of 100 to 7200 A/cm/sup 2/. The experimental dynamic I-V characteristic curves obtained are rich in features and determined by the effects that temperature and carrier concentration have on the carrier mobility and lifetime, on the Fermi-Dirac distribution function and on the energy band gap. The experimental results have been used to check the validity of the physical models implemented in the simulation package AVANT! MEDICI. Simulations performed using the standard physical models implemented in MEDICI give an excellent agreement with measurement results up to a peak current density of 1500 Amps/cm/sup 2/, and a reasonable good one up to a peak current density of 2000 Amps/cm/sup 2/. However, the agreement between measurements and simulations is very poor at peak current densities above 2000 Amps/cm/sup 2/.
{"title":"Physical phenomena in Si power diodes operating at high carrier injection levels and high temperature","authors":"L. M. Hillkirk, B. Breitholtz, J. Lutz","doi":"10.1109/ISPSD.2000.856819","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856819","url":null,"abstract":"The physics of fast recovery 3.3 kV Si power diodes radiation induced recombination centers operating under forward bias at large current densities and high temperatures have been studied both experimentally and by means of computer simulations. In the experimental studies the dynamic I-V characteristics, the surface temperature and the surface potential distribution in the n-base have been measured, while the diodes were being subjected to single 1.3 ms half-sine-wave current pulses having a density in the range of 100 to 7200 A/cm/sup 2/. The experimental dynamic I-V characteristic curves obtained are rich in features and determined by the effects that temperature and carrier concentration have on the carrier mobility and lifetime, on the Fermi-Dirac distribution function and on the energy band gap. The experimental results have been used to check the validity of the physical models implemented in the simulation package AVANT! MEDICI. Simulations performed using the standard physical models implemented in MEDICI give an excellent agreement with measurement results up to a peak current density of 1500 Amps/cm/sup 2/, and a reasonable good one up to a peak current density of 2000 Amps/cm/sup 2/. However, the agreement between measurements and simulations is very poor at peak current densities above 2000 Amps/cm/sup 2/.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116502868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856845
J. Onuki, Y. Chonan, T. Komiyama, M. Nihei, R. Saitou, M. Suwa, M. Kitano
A new void free process for the solder joint between a chip mounted AlN substrate and a metal substrate in large-area, high power IGBT modules has been investigated. The following new process consists of two steps. First, Ar/sup +/ ions were used to clean the surface of Ni plated films on the metal and AlN substrates by followed by coating with a thin Ag film, and secondly, 50 wt.% Pb-Sn solder sandwiched between the two substrates was heated in vacuum at 503 K for 5 min. and then cooled in a N/sub 2/ atmosphere. Using this process, the area percentage of voids in a soldering area up to 130/spl times/190 mm/sup 2/ can be reduced to less than 0.2%. The fatigue life time of solder joints made with this new method are found to be about 3 times longer than those by the soldering methods in H/sub 2/ (abbreviated as H/sub 2/ process hereafter).
{"title":"A new void free soldering process in large-area, high power IGBT modules","authors":"J. Onuki, Y. Chonan, T. Komiyama, M. Nihei, R. Saitou, M. Suwa, M. Kitano","doi":"10.1109/ISPSD.2000.856845","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856845","url":null,"abstract":"A new void free process for the solder joint between a chip mounted AlN substrate and a metal substrate in large-area, high power IGBT modules has been investigated. The following new process consists of two steps. First, Ar/sup +/ ions were used to clean the surface of Ni plated films on the metal and AlN substrates by followed by coating with a thin Ag film, and secondly, 50 wt.% Pb-Sn solder sandwiched between the two substrates was heated in vacuum at 503 K for 5 min. and then cooled in a N/sub 2/ atmosphere. Using this process, the area percentage of voids in a soldering area up to 130/spl times/190 mm/sup 2/ can be reduced to less than 0.2%. The fatigue life time of solder joints made with this new method are found to be about 3 times longer than those by the soldering methods in H/sub 2/ (abbreviated as H/sub 2/ process hereafter).","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123762267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856825
M. Tanaka, S. Teramae, Y. Takahashi, T. Takeda, M. Yamaguchi, T. Ogura, T. Tsunoda, S. Nakao
The 600 V Non-Punch Through (NPT) IGBT which has low on-state voltage (V/sub CE/(sat)) has been developed. This device has a fine pitch trench-gate structure at the emitter side and the collector layer with low injection efficiency at collector side. A novel profile has been installed to realize low injection efficiency and low V/sub CE/(sat). By numerical simulation, it has been confirmed that the trade-off relation between V/sub CE/(sat) and turn-off loss of the trench-gate NPT-IGBT is as good as that of the trench-gate punch through (PT-)IGBT. Adopting the novel profile for the collector structure, the low V/sub CE/(sat) of 1.6 V at 180 A/cm/sup 2/ has been realized for the 600 V trench-gate NPT-IGBT.
研制了具有低导通电压(V/sub CE/(sat))的600 V Non-Punch Through (NPT) IGBT。该装置在发射极侧具有细间距沟栅结构，在集电极侧具有低注入效率的集电极层。安装了一种新颖的剖面，以实现低喷射效率和低V/sub CE/(sat)。通过数值模拟，证实了沟栅NPT-IGBT的V/sub CE/(sat)与关断损耗之间的权衡关系与沟栅冲通(PT-)IGBT一样好。采用新颖的集电极结构，实现了600 V槽栅NPT-IGBT在180 A/cm/sup 2/下1.6 V的低V/sub CE/(sat)。
{"title":"600 V trench-gate NPT-IGBT with excellent low on-state voltage","authors":"M. Tanaka, S. Teramae, Y. Takahashi, T. Takeda, M. Yamaguchi, T. Ogura, T. Tsunoda, S. Nakao","doi":"10.1109/ISPSD.2000.856825","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856825","url":null,"abstract":"The 600 V Non-Punch Through (NPT) IGBT which has low on-state voltage (V/sub CE/(sat)) has been developed. This device has a fine pitch trench-gate structure at the emitter side and the collector layer with low injection efficiency at collector side. A novel profile has been installed to realize low injection efficiency and low V/sub CE/(sat). By numerical simulation, it has been confirmed that the trade-off relation between V/sub CE/(sat) and turn-off loss of the trench-gate NPT-IGBT is as good as that of the trench-gate punch through (PT-)IGBT. Adopting the novel profile for the collector structure, the low V/sub CE/(sat) of 1.6 V at 180 A/cm/sup 2/ has been realized for the 600 V trench-gate NPT-IGBT.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128116792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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