Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856791
I. Pagès, B. Baird, J. Wang, T. Sicard, J. Dorkel, P. Dupuy, P. Lance, E. Huynh, Y. Chung
Cost effective automotive applications and the related circuit designs are requiring new SMARTMOS/sup TM/ technology extensions to manage energy capability and metal debiasing in smart power devices. A thick copper metallization scheme, POWER COPPER, has been integrated and characterized in the circuit design of two electronic modules for automotive applications.
{"title":"Advanced power copper technology for SMARTMOS/sup TM/ application designs","authors":"I. Pagès, B. Baird, J. Wang, T. Sicard, J. Dorkel, P. Dupuy, P. Lance, E. Huynh, Y. Chung","doi":"10.1109/ISPSD.2000.856791","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856791","url":null,"abstract":"Cost effective automotive applications and the related circuit designs are requiring new SMARTMOS/sup TM/ technology extensions to manage energy capability and metal debiasing in smart power devices. A thick copper metallization scheme, POWER COPPER, has been integrated and characterized in the circuit design of two electronic modules for automotive applications.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132072042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856771
S. Whiston, D. Bain, A. Deignan, J. Pollard, C. N. Chléirigh, C.M.M. O'Neill
This paper describes a methodology of using multiple implants that are self-aligned to the poly gate edge to form an LDMOS. This allows the implementation of complementary LDMOS devices onto existing CMOS/BiCMOS processes without the addition of any thermal treatments thereby having no effect on the existing CMOS/BiCMOS device performance. This approach gives greater flexibility in controlling the body doping profile in the lateral and vertical directions enabling threshold voltage (Vt) and breakdown voltage (BV) optimization for a wide range of source junctions that exist in many intrinsic and foundry processes.
{"title":"Complementary LDMOS transistors for a CMOS/BiCMOS process","authors":"S. Whiston, D. Bain, A. Deignan, J. Pollard, C. N. Chléirigh, C.M.M. O'Neill","doi":"10.1109/ISPSD.2000.856771","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856771","url":null,"abstract":"This paper describes a methodology of using multiple implants that are self-aligned to the poly gate edge to form an LDMOS. This allows the implementation of complementary LDMOS devices onto existing CMOS/BiCMOS processes without the addition of any thermal treatments thereby having no effect on the existing CMOS/BiCMOS device performance. This approach gives greater flexibility in controlling the body doping profile in the lateral and vertical directions enabling threshold voltage (Vt) and breakdown voltage (BV) optimization for a wide range of source junctions that exist in many intrinsic and foundry processes.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"25 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114115541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856762
H. Matsunami
The progress in SiC crystal growth of bulk and epitaxial layers for power devices is reviewed. Current status in device processes is introduced. Then, the state-of-the-art SiC power devices are described. "On-resistance" in vertical power MOSFETs which determines the power loss is discussed, and recent progress in SiC MOSFET performance is presented by improving channel mobilities.
{"title":"Progress in wide bandgap semiconductor SiC for power devices","authors":"H. Matsunami","doi":"10.1109/ISPSD.2000.856762","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856762","url":null,"abstract":"The progress in SiC crystal growth of bulk and epitaxial layers for power devices is reviewed. Current status in device processes is introduced. Then, the state-of-the-art SiC power devices are described. \"On-resistance\" in vertical power MOSFETs which determines the power loss is discussed, and recent progress in SiC MOSFET performance is presented by improving channel mobilities.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116744248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856844
J. Yedinak, B. Wood, P. Shenoy, G. Dolny, D. Lange, T. Morthorst
In this paper, we analyze the UIS capability of punchthrough (PT) IGBTs both experimentally, and through non-isothermal two-dimensional numerical simulations. It is shown that the UIS failure mechanism is determined by the open-base p-n-p structure inherent in the IGBT. By optimizing the open base p-n-p, avalanche induced second breakdown can be prevented at current densities in excess of 1000 A/cm/sup 2/. A 600 V PT-IGBT with low on-state voltage, fast switching, and >4.5 J/cm/sup 2/ UIS capability at 120 A/cm/sup 2/ is experimentally demonstrated.
本文通过实验和非等温二维数值模拟两种方法分析了冲穿型igbt的UIS性能。结果表明，UIS的失效机制是由IGBT固有的开基p-n-p结构决定的。通过优化开放基极p-n-p，可以在电流密度超过1000 A/cm/sup /时防止雪崩引起的二次击穿。实验证明了600 V PT-IGBT具有低导通电压，快速开关和>4.5 J/cm/sup 2/ UIS的120 A/cm/sup 2/能力。
{"title":"Optimizing 600 V punchthrough IGBT's for unclamped inductive switching (UIS)","authors":"J. Yedinak, B. Wood, P. Shenoy, G. Dolny, D. Lange, T. Morthorst","doi":"10.1109/ISPSD.2000.856844","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856844","url":null,"abstract":"In this paper, we analyze the UIS capability of punchthrough (PT) IGBTs both experimentally, and through non-isothermal two-dimensional numerical simulations. It is shown that the UIS failure mechanism is determined by the open-base p-n-p structure inherent in the IGBT. By optimizing the open base p-n-p, avalanche induced second breakdown can be prevented at current densities in excess of 1000 A/cm/sup 2/. A 600 V PT-IGBT with low on-state voltage, fast switching, and >4.5 J/cm/sup 2/ UIS capability at 120 A/cm/sup 2/ is experimentally demonstrated.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132131558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856806
F. Udrea, A. Popescu, R. Ng, G. Amaratunga
In this paper we report a novel class of semiconductor devices termed 3D devices, based on the application of the RESURF concept to the the third dimension. For the first time we demonstrate devices based on pure three-dimensional on-state/blocking operation with the third-dimension junction acting to enhance the breakdown capability in the voltage blocking mode and provide conductivity modulation in the on-state. A brief discussion of the ideal substrate to enhance breakdown performance is also given.
{"title":"Minority carrier injection across the 3D RESURF junction","authors":"F. Udrea, A. Popescu, R. Ng, G. Amaratunga","doi":"10.1109/ISPSD.2000.856806","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856806","url":null,"abstract":"In this paper we report a novel class of semiconductor devices termed 3D devices, based on the application of the RESURF concept to the the third dimension. For the first time we demonstrate devices based on pure three-dimensional on-state/blocking operation with the third-dimension junction acting to enhance the breakdown capability in the voltage blocking mode and provide conductivity modulation in the on-state. A brief discussion of the ideal substrate to enhance breakdown performance is also given.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134241091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856816
D. Peters, P. Friedrichs, H. Mitlehner, R. Schoerner, U. Weinert, B. Weis, D. Stephani
New results of silicon carbide p-n diodes show a promising performance for high voltage applications. The diodes are characterized by high power ratings, temperature stability, rugged avalanche and fast switching behavior. Significant savings in system cooling equipment seem possible. However, with today's available material the device areas and thereby current ratings which can be fabricated with reasonable yield are restricted to a few square mm resp. a few amps. The SiC p-n diodes are fabricated with implanted p-regions on 39 /spl mu/m thick n-type epitaxial layers with a doping concentration of 2/spl times/10/sup 15/ cm/sup -3/. They exhibit a stable avalanche breakdown at 4800 V and a low leakage current (<20 /spl mu/A/cm/sup 2/) prior to breakdown. The on-state is characterized by a voltage drop of 4.0 V at a current density of 100 A/cm/sup 2/, corresponding to 2.2 A. For current densities above 80 A/cm/sup 2/ lower static losses have been achieved compared to equivalent silicon high voltage diodes. The temperature coefficient is slightly positive guaranteeing a homogeneous current sharing for operation in parallel. The switching performance is characterized by very low dynamic losses. The reverse recovery current peak is considerably lower than the forward current, with a reverse recovery time as short as 30 ns.
{"title":"Characterization of fast 4.5 kV SiC p-n diodes","authors":"D. Peters, P. Friedrichs, H. Mitlehner, R. Schoerner, U. Weinert, B. Weis, D. Stephani","doi":"10.1109/ISPSD.2000.856816","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856816","url":null,"abstract":"New results of silicon carbide p-n diodes show a promising performance for high voltage applications. The diodes are characterized by high power ratings, temperature stability, rugged avalanche and fast switching behavior. Significant savings in system cooling equipment seem possible. However, with today's available material the device areas and thereby current ratings which can be fabricated with reasonable yield are restricted to a few square mm resp. a few amps. The SiC p-n diodes are fabricated with implanted p-regions on 39 /spl mu/m thick n-type epitaxial layers with a doping concentration of 2/spl times/10/sup 15/ cm/sup -3/. They exhibit a stable avalanche breakdown at 4800 V and a low leakage current (<20 /spl mu/A/cm/sup 2/) prior to breakdown. The on-state is characterized by a voltage drop of 4.0 V at a current density of 100 A/cm/sup 2/, corresponding to 2.2 A. For current densities above 80 A/cm/sup 2/ lower static losses have been achieved compared to equivalent silicon high voltage diodes. The temperature coefficient is slightly positive guaranteeing a homogeneous current sharing for operation in parallel. The switching performance is characterized by very low dynamic losses. The reverse recovery current peak is considerably lower than the forward current, with a reverse recovery time as short as 30 ns.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133833780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856763
A. Ludikhuize
RESURF (Reduced Surface Field) technology is one of the most widely-used methods for the design of lateral high-voltage, low on-resistance devices. The technique has allowed the integration of HV devices, ranging from 20 V to 1200 V, with bipolar and MOS transistors. A technical review is given on the technology as developed during the last 20 years. The paper discusses the invention and its application in discrete devices, in Junction-Isolated IC's and SOI, and as Multiple Resurf. It includes an evaluation of topics like breakdown, on-resistance, high-side and high-current effects and reliability.
{"title":"A review of RESURF technology","authors":"A. Ludikhuize","doi":"10.1109/ISPSD.2000.856763","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856763","url":null,"abstract":"RESURF (Reduced Surface Field) technology is one of the most widely-used methods for the design of lateral high-voltage, low on-resistance devices. The technique has allowed the integration of HV devices, ranging from 20 V to 1200 V, with bipolar and MOS transistors. A technical review is given on the technology as developed during the last 20 years. The paper discusses the invention and its application in discrete devices, in Junction-Isolated IC's and SOI, and as Multiple Resurf. It includes an evaluation of topics like breakdown, on-resistance, high-side and high-current effects and reliability.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130313279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856833
M. M. De Souza, O. Spulber, E. M. Sankara Narayanan
A novel, planar, Cool Insulated Base Transistor (IBT) is presented. This is the first MOS-controlled bipolar semiconductor device, which incorporates the super junction concept. The Cool IBT has a current amplification of (/spl beta/+1)* the Cool MOSFET current, where /spl beta/ is the gain of the inherent NPN transistor. Unlike the IGBT, cathode cells of the IBT and MOSFET can be easily paralleled on the same chip. Thus, the device can be turned on at a drain voltage of 0 V, while retaining the low on-resistance of the Cool IBT.
{"title":"A novel 'cool' insulated base transistor","authors":"M. M. De Souza, O. Spulber, E. M. Sankara Narayanan","doi":"10.1109/ISPSD.2000.856833","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856833","url":null,"abstract":"A novel, planar, Cool Insulated Base Transistor (IBT) is presented. This is the first MOS-controlled bipolar semiconductor device, which incorporates the super junction concept. The Cool IBT has a current amplification of (/spl beta/+1)* the Cool MOSFET current, where /spl beta/ is the gain of the inherent NPN transistor. Unlike the IGBT, cathode cells of the IBT and MOSFET can be easily paralleled on the same chip. Thus, the device can be turned on at a drain voltage of 0 V, while retaining the low on-resistance of the Cool IBT.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130401177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856788
T. Reimann, R. Krummer, U. Franke, J. Petzoldt, L. Lorenz
Investigations of the transient chip temperature of IGBT and diode in power modules are presented in this paper. The calculation of chip temperature and power losses occurs on-line in a microcontroller. Advanced practical results achieved in a step down converter are shown at different load cycles and output frequencies with the same average load current. An analysis of results and errors is also shown.
{"title":"Real time calculation of the chip temperature of power modules in PWM inverters using a 16 bit microcontroller","authors":"T. Reimann, R. Krummer, U. Franke, J. Petzoldt, L. Lorenz","doi":"10.1109/ISPSD.2000.856788","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856788","url":null,"abstract":"Investigations of the transient chip temperature of IGBT and diode in power modules are presented in this paper. The calculation of chip temperature and power losses occurs on-line in a microcontroller. Advanced practical results achieved in a step down converter are shown at different load cycles and output frequencies with the same average load current. An analysis of results and errors is also shown.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122514766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856837
Tomohide Terashima, F. Yamamoto, K. Hatasako
This paper describes the multi-voltage device integration technique for BiCMOS and DMOS process and the simple measures to the beta decreasing of 5 V/12 V NPNTr by the lack of heat treatment used for half-micron process. The N well offset gate are used for 30 V HV-NMOS. Moreover, RESURF effect by Buried P+ is applied to 60 V HV-NMOS. Each specific on-resistance (Ron/spl middot/S) reaches sufficiently low value (60 m /spl Omega/ mm2 (BVds=33 V), 127 m /spl Omega/ mm2 (BVds=74 V)). 60 V DMOS structure became to 90 V DMOS by only addition of P well guard ring, and the Ron/spl middot/S is 230 m /spl Omega/ mm2 (BVds=94 V). Using the appropriate length of RESURF formed at N-epitaxial layer; we could optimize 30 V/60 V/90 V NMOS devices and FID (Full Isolation Diode). In the case of PMOS, 30 V/60 V/90 V PMOS has been realized by using the combination of P-LDD (Lightly Doped Drain) and Sinker P region (P body, P well). Using a P+ shield region stabilized the beta of 5 V/12 V NPNTr. Any complicated process step is not needed for various techniques mentioned above.
本文介绍了BiCMOS和DMOS工艺的多电压器件集成技术，以及半微米工艺中5 V/12 V NPNTr不经热处理而降低β的简单措施。N井偏置栅极用于30v高压nmos。此外，埋入的P+对60 V HV-NMOS产生了RESURF效应。每个特定导通电阻(Ron/spl中点/S)达到足够低的值(60 m /spl Omega/ mm2 (BVds=33 V)， 127 m /spl Omega/ mm2 (BVds=74 V))。仅加入P井保护环，60 V DMOS结构变为90 V DMOS, Ron/spl middot/S为230 m /spl Omega/ mm2 (BVds=94 V)。我们可以优化30 V/60 V/90 V NMOS器件和FID(全隔离二极管)。以PMOS为例，采用P- ldd(轻掺杂漏极)和下沉P区(P体、P阱)相结合的方法实现了30 V/60 V/90 V的PMOS。利用P+屏蔽区稳定了5v / 12v NPNTr的β。上述各种技术不需要任何复杂的工艺步骤。
{"title":"Multi-voltage device integration technique for 0.5 /spl mu/m BiCMOS and DMOS process","authors":"Tomohide Terashima, F. Yamamoto, K. Hatasako","doi":"10.1109/ISPSD.2000.856837","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856837","url":null,"abstract":"This paper describes the multi-voltage device integration technique for BiCMOS and DMOS process and the simple measures to the beta decreasing of 5 V/12 V NPNTr by the lack of heat treatment used for half-micron process. The N well offset gate are used for 30 V HV-NMOS. Moreover, RESURF effect by Buried P+ is applied to 60 V HV-NMOS. Each specific on-resistance (Ron/spl middot/S) reaches sufficiently low value (60 m /spl Omega/ mm2 (BVds=33 V), 127 m /spl Omega/ mm2 (BVds=74 V)). 60 V DMOS structure became to 90 V DMOS by only addition of P well guard ring, and the Ron/spl middot/S is 230 m /spl Omega/ mm2 (BVds=94 V). Using the appropriate length of RESURF formed at N-epitaxial layer; we could optimize 30 V/60 V/90 V NMOS devices and FID (Full Isolation Diode). In the case of PMOS, 30 V/60 V/90 V PMOS has been realized by using the combination of P-LDD (Lightly Doped Drain) and Sinker P region (P body, P well). Using a P+ shield region stabilized the beta of 5 V/12 V NPNTr. Any complicated process step is not needed for various techniques mentioned above.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115993036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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