Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920790
Chin Lin Ng, M. Tan
Carbon-based devices such as carbon nanotubes (CNT) and graphene nanoribbon (GNR) have been explored rigorously as the potential successor to conventional metal-oxide-semiconductor field-effect transistors (MOSFET). The limitations of silicon-based devices have catalysed much breakthrough research on carbon-based devices. In this paper, a comprehensive quantum simulation tool based on carbon devices is developed as a graphical user interface (GUI) using MATLAB. It is known as Low Dimensional Simulator (LODISI). This simulation tool allows the user to reach a trade-off between precision and time, as it provides impromptu analysis either by graph or direct calculation values. In addition, the auto generation of the voltage transfer curve from the complementary nanotransistor drain characteristics is one of the significant feature of LODISI.
{"title":"Low dimensional simulator for carbon-based devices","authors":"Chin Lin Ng, M. Tan","doi":"10.1109/SMELEC.2014.6920790","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920790","url":null,"abstract":"Carbon-based devices such as carbon nanotubes (CNT) and graphene nanoribbon (GNR) have been explored rigorously as the potential successor to conventional metal-oxide-semiconductor field-effect transistors (MOSFET). The limitations of silicon-based devices have catalysed much breakthrough research on carbon-based devices. In this paper, a comprehensive quantum simulation tool based on carbon devices is developed as a graphical user interface (GUI) using MATLAB. It is known as Low Dimensional Simulator (LODISI). This simulation tool allows the user to reach a trade-off between precision and time, as it provides impromptu analysis either by graph or direct calculation values. In addition, the auto generation of the voltage transfer curve from the complementary nanotransistor drain characteristics is one of the significant feature of LODISI.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126207492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920868
I. Abdullah, R. Ismail, A. Jalar
Dislocation behavior was occurs when an eutectic solder alloy of SnAgCu experiencing different strain at room temperature that require the further analysis in order to relate the physical and microstructure changes towards the mechanical performance of lead free solder. In this study, nanoindentation technique was applied to determine the hardness and modulus on six variant of strain (0.00015 mms-1, 0.0015 mms-1, 0.015 mms-1, 0.15 mms-1, 1.5 mms-1 and 15 mms-1) after tensile test. The P-h curves and the micromechanical parameter namely hardness and residual modulus through nanoindentation test were conducted. The analysis were obtained strain rate sensitivity (m) and stress exponent (n) from dwell time in order to determine the mechanism of grains. The P-h curve result showed the pop-in event at the ranges of 100 nm to 300 nm. The micromechanical properties were show the increment of values at high strain rates. The dominated discontinuity local will occurrence the pop-in event and will activating dislocation distribution.
当SnAgCu共晶钎料合金在室温下经历不同应变时，会发生位错行为，这需要进一步分析，以便将物理和微观结构变化与无铅钎料的机械性能联系起来。本研究采用纳米压痕技术测定拉伸试验后6种应变(0.00015 mm -1、0.0015 mm -1、0.015 mm -1、0.15 mm -1、1.5 mm -1和15 mm -1)下的硬度和模量。通过纳米压痕测试得到了P-h曲线和显微力学参数硬度和残余模量。为了确定晶粒的形成机理，分析了停留时间的应变率敏感性(m)和应力指数(n)。P-h曲线结果表明，在100 ~ 300 nm范围内出现了弹出事件。在高应变速率下，材料的微观力学性能呈递增趋势。受控制的不连续局部将发生弹出事件并激活位错分布。
{"title":"Strain rate effect on micromechanical properties of SnAgCu solder wire","authors":"I. Abdullah, R. Ismail, A. Jalar","doi":"10.1109/SMELEC.2014.6920868","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920868","url":null,"abstract":"Dislocation behavior was occurs when an eutectic solder alloy of SnAgCu experiencing different strain at room temperature that require the further analysis in order to relate the physical and microstructure changes towards the mechanical performance of lead free solder. In this study, nanoindentation technique was applied to determine the hardness and modulus on six variant of strain (0.00015 mms-1, 0.0015 mms-1, 0.015 mms-1, 0.15 mms-1, 1.5 mms-1 and 15 mms-1) after tensile test. The P-h curves and the micromechanical parameter namely hardness and residual modulus through nanoindentation test were conducted. The analysis were obtained strain rate sensitivity (m) and stress exponent (n) from dwell time in order to determine the mechanism of grains. The P-h curve result showed the pop-in event at the ranges of 100 nm to 300 nm. The micromechanical properties were show the increment of values at high strain rates. The dominated discontinuity local will occurrence the pop-in event and will activating dislocation distribution.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115336575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920896
C. Hsiao, Chun-Xiao Liu, S. Huynh, T. Minh, H. Yu, Hong-Quan Nguyen, J. Maa, S. Chang, E. Chang
The epitaxial growth of GaSb thin film with different V/III ratios on high-lattice-mismatched GaAs (001) substrates by metal organic chemical vapor deposition (MOCVD) was investigated. Under optimal V/III ratio of 2.5, we found that there are many periodic 90° interfacial misfit dislocation (IMF) arrays existing at the GaAs/GaSb interface. The surface roughness is about 3.6nm, 2.2nm, 3.8nm, respectively while different V/III ratios (1.25, 2.5, 5) were adopted. These results demonstrated that the hill-and valley structure on the surface of GaSb/GaAs heterostructure can be effectively improved, and formed smooth surface morphology.
{"title":"Effect of V/III ratios on surface morphology in a GaSb thin film grown on GaAs substrate by MOCVD","authors":"C. Hsiao, Chun-Xiao Liu, S. Huynh, T. Minh, H. Yu, Hong-Quan Nguyen, J. Maa, S. Chang, E. Chang","doi":"10.1109/SMELEC.2014.6920896","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920896","url":null,"abstract":"The epitaxial growth of GaSb thin film with different V/III ratios on high-lattice-mismatched GaAs (001) substrates by metal organic chemical vapor deposition (MOCVD) was investigated. Under optimal V/III ratio of 2.5, we found that there are many periodic 90° interfacial misfit dislocation (IMF) arrays existing at the GaAs/GaSb interface. The surface roughness is about 3.6nm, 2.2nm, 3.8nm, respectively while different V/III ratios (1.25, 2.5, 5) were adopted. These results demonstrated that the hill-and valley structure on the surface of GaSb/GaAs heterostructure can be effectively improved, and formed smooth surface morphology.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115371943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920895
R. Abu Bakar, Ahmad Faiz Mohamad Zohaimi, N. Kamarozaman, N. Shaari, S. M. M. Kasim, S. H. Herman
This work focuses on the resistive switching behavior of sol-gel spin coated zinc oxide (ZnO) thin films on ITO substrate. The deposited ZnO thin films were annealed at various temperatures from 300°C to 500°C in a furnace for 60 minutes in order to study the effect of annealing temperature on the resistive switching behavior of ZnO thin film. The electrical property of the thin film was characterized using 2-point probe current-voltage (I-V) measurement. The surface morphology and film thickness were examined and measured using atomic force microscopy (AFM) and surface profiler respectively. The I-V characteristic showed that the heat treatment on the ZnO thin films at 300 and 400°C resulted in the resistive switching characteristic behavior. Further increasing the temperature up to 500°C on the other hand leads to the formation of asymmetrical hysteresis loop.
{"title":"Annealing temperature dependence of resistive switching behavior for sol-gel spin coated zinc oxide thin films","authors":"R. Abu Bakar, Ahmad Faiz Mohamad Zohaimi, N. Kamarozaman, N. Shaari, S. M. M. Kasim, S. H. Herman","doi":"10.1109/SMELEC.2014.6920895","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920895","url":null,"abstract":"This work focuses on the resistive switching behavior of sol-gel spin coated zinc oxide (ZnO) thin films on ITO substrate. The deposited ZnO thin films were annealed at various temperatures from 300°C to 500°C in a furnace for 60 minutes in order to study the effect of annealing temperature on the resistive switching behavior of ZnO thin film. The electrical property of the thin film was characterized using 2-point probe current-voltage (I-V) measurement. The surface morphology and film thickness were examined and measured using atomic force microscopy (AFM) and surface profiler respectively. The I-V characteristic showed that the heat treatment on the ZnO thin films at 300 and 400°C resulted in the resistive switching characteristic behavior. Further increasing the temperature up to 500°C on the other hand leads to the formation of asymmetrical hysteresis loop.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124300835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920859
Salah Alkurwy, S. M. Md Ali, M. Islam
A Low Power Compressed ROM Look-up table has been presented in this paper to achieve low power consumption of the direct digital frequency synthesizer as well small core size. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The suggested 12-bit compressed ROM designed consists of three 4-bit sub-ROMs based on an angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2:1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz.
{"title":"Implementation of low power compressed ROM for direct digital frequency synthesizer","authors":"Salah Alkurwy, S. M. Md Ali, M. Islam","doi":"10.1109/SMELEC.2014.6920859","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920859","url":null,"abstract":"A Low Power Compressed ROM Look-up table has been presented in this paper to achieve low power consumption of the direct digital frequency synthesizer as well small core size. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The suggested 12-bit compressed ROM designed consists of three 4-bit sub-ROMs based on an angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2:1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116132254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920825
A. Maheran, P. Menon, S. Shaari, T. Kalaivani, Ibrahim Ahmad, Z. A. N. Faizah, P. R. Apte
This paper provides the enhancement of 22nm planar PMOS transistor technology through downscaling, design parameter simulation and optimization process. The scaled down device is optimized for its process parameter variability using Taguchi method. The aim is to find the best combination of fabrication parameters in order to achieve the target value of the threshold voltage (Vth). A combination of high permittivity material (high-k) and metal gate is utilized simultaneously in replacing the conventional SiO2/Poly-Si technology. For this, Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate. The simulation results show that the optimal threshold voltage (Vth) of -0.289 V ± 12.7% is achieved in accordance to the ITRS 2012 specifications. This provides a benchmark towards the fabrication of 22 nm planar PMOS in future work.
{"title":"Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method","authors":"A. Maheran, P. Menon, S. Shaari, T. Kalaivani, Ibrahim Ahmad, Z. A. N. Faizah, P. R. Apte","doi":"10.1109/SMELEC.2014.6920825","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920825","url":null,"abstract":"This paper provides the enhancement of 22nm planar PMOS transistor technology through downscaling, design parameter simulation and optimization process. The scaled down device is optimized for its process parameter variability using Taguchi method. The aim is to find the best combination of fabrication parameters in order to achieve the target value of the threshold voltage (Vth). A combination of high permittivity material (high-k) and metal gate is utilized simultaneously in replacing the conventional SiO2/Poly-Si technology. For this, Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate. The simulation results show that the optimal threshold voltage (Vth) of -0.289 V ± 12.7% is achieved in accordance to the ITRS 2012 specifications. This provides a benchmark towards the fabrication of 22 nm planar PMOS in future work.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123644841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920784
Zonghua Zheng, Lingling Sun, Jun Liu
This paper designs a 20 GHz power amplifier based on a novel model which is the quadratic polynomial expansion of nonlinear scattering function. The novel model is capable of accurately computing the voltage of device under any fundamental and harmonic frequency load impedance changing implemented with Frequency Domain Defined Device (FDD) component in the ADS. Through the new model, it is easy to find out the optimal fundamental and harmonic load impedance. The designed PA achieves a peak power-added efficiency (PAE) of 35.1% and the saturated output power of 21 dBm in PP1010MS EEHEMT operating at 20 GHz.
{"title":"A 20 GHz power amplifier design on novel nonlinear model","authors":"Zonghua Zheng, Lingling Sun, Jun Liu","doi":"10.1109/SMELEC.2014.6920784","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920784","url":null,"abstract":"This paper designs a 20 GHz power amplifier based on a novel model which is the quadratic polynomial expansion of nonlinear scattering function. The novel model is capable of accurately computing the voltage of device under any fundamental and harmonic frequency load impedance changing implemented with Frequency Domain Defined Device (FDD) component in the ADS. Through the new model, it is easy to find out the optimal fundamental and harmonic load impedance. The designed PA achieves a peak power-added efficiency (PAE) of 35.1% and the saturated output power of 21 dBm in PP1010MS EEHEMT operating at 20 GHz.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121056031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920778
A. Khelif
Classical waves, including elastic waves (acoustic waves) and electromagnetic waves (optical waves and microwaves), are described by conventional wave-propagation functions. Elastic waves were the first waveforms to be understood in condensed matter and have a wide range of applications from industry to defense, from healthcare to entertainment. In 1987, the photonic crystal was proposed to describe the propagation of optical waves in refraction index-modulated periodic structures analogous to the propagation of electrons in real crystals. This situation recalls the classical work by Brillouin. Brillouin considered elastic waves in periodic strings, electromagnetic waves in electrical circuits, and electrons in crystals as a system, resulting in some important common concepts, such as the Brillouin zone, band gap, etc., which are generally shared by the various forms of waves: electrons as scalar waves, optical waves as vector waves, and elastic waves as tensor waves. Following on from photonic crystals, the concept of phononic crystals was conceived with elastic waves propagating in periodic structures modulated with periodic elastic moduli and mass densities. These artificially structured materials possess a number of important properties, such as band gaps, band edge states7, and the ability to slow the velocity of sound (slow wave effect). Furthermore, by creating artificially designed structures on a deep subwavelength scale, artificial acoustic `atoms' can be purposely engineered into acoustic metamaterials to dramatically change the excitation and propagation of acoustic waves, and thus give rise to subdiffraction-limited resolution and its related myriad novel effects, such as negative, negative elastic modulus, and negative mass density. Finally, Acoustic metamaterials and phononicc crystal are a newly emerging field, which have inherently abnormal and interesting physical effects that are important to basic research, and offer potential for applications in everyday life that might revolutionize acoustic materials.
{"title":"Acoustic metamaterials and phononic crystals: Towards the total control of the wave propagation","authors":"A. Khelif","doi":"10.1109/SMELEC.2014.6920778","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920778","url":null,"abstract":"Classical waves, including elastic waves (acoustic waves) and electromagnetic waves (optical waves and microwaves), are described by conventional wave-propagation functions. Elastic waves were the first waveforms to be understood in condensed matter and have a wide range of applications from industry to defense, from healthcare to entertainment. In 1987, the photonic crystal was proposed to describe the propagation of optical waves in refraction index-modulated periodic structures analogous to the propagation of electrons in real crystals. This situation recalls the classical work by Brillouin. Brillouin considered elastic waves in periodic strings, electromagnetic waves in electrical circuits, and electrons in crystals as a system, resulting in some important common concepts, such as the Brillouin zone, band gap, etc., which are generally shared by the various forms of waves: electrons as scalar waves, optical waves as vector waves, and elastic waves as tensor waves. Following on from photonic crystals, the concept of phononic crystals was conceived with elastic waves propagating in periodic structures modulated with periodic elastic moduli and mass densities. These artificially structured materials possess a number of important properties, such as band gaps, band edge states7, and the ability to slow the velocity of sound (slow wave effect). Furthermore, by creating artificially designed structures on a deep subwavelength scale, artificial acoustic `atoms' can be purposely engineered into acoustic metamaterials to dramatically change the excitation and propagation of acoustic waves, and thus give rise to subdiffraction-limited resolution and its related myriad novel effects, such as negative, negative elastic modulus, and negative mass density. Finally, Acoustic metamaterials and phononicc crystal are a newly emerging field, which have inherently abnormal and interesting physical effects that are important to basic research, and offer potential for applications in everyday life that might revolutionize acoustic materials.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122563022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920864
K. Ibrahim, M. A. Chik, U. Hashim
Semiconductor wafer manufacturing, being one of the most advanced and complex process, commands high level of utilization of the available tools to ensure maximum productivity. It is also very important to keep the operations as lean as possible to ensure cost effectiveness. In this research we will show that the cost additional capacity is outrages. This is the main reason more and more companies are opting out of fab owners club. Others are scaling down and going fables and fab-light. Capacity utilization and capacity maximization is the key to a successful fab. Fabs continuously look for ways to increase the capacity by improving productivity. Beyond certain productivity level, fabs must spend on purchasing tools. Semiconductor tools are expensive and in many cases there will be a need to spend in the support infrastructure. The escalating cost really brings out the creativity and innovation among the fab engineers. This paper discusses what actions are taken to address or mitigate this issue. The research is based on some available data from SilTerra Malaysia S dn Bhd wafer fab in Kulim.
半导体晶圆制造作为最先进和最复杂的工艺之一，要求对现有工具的高度利用，以确保最大的生产力。保持操作尽可能精简以确保成本效益也是非常重要的。在本研究中，我们将证明额外容量的成本是暴行。这就是越来越多的公司选择退出晶圆厂业主俱乐部的主要原因。其他公司则在缩减规模，采用小工厂和小工厂。产能利用率和产能最大化是晶圆厂成功的关键。晶圆厂不断寻求通过提高生产率来增加产能的方法。超过一定的生产水平，晶圆厂必须花费在购买工具上。半导体工具是昂贵的，在许多情况下，将需要在支持基础设施上花费。不断上升的成本确实激发了晶圆厂工程师的创造力和创新精神。本文讨论了采取什么行动来解决或减轻这个问题。该研究基于位于居林的SilTerra Malaysia S dn Bhd晶圆厂的一些可用数据。
{"title":"Horrendous capacity cost of semiconductor wafer manufacturing","authors":"K. Ibrahim, M. A. Chik, U. Hashim","doi":"10.1109/SMELEC.2014.6920864","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920864","url":null,"abstract":"Semiconductor wafer manufacturing, being one of the most advanced and complex process, commands high level of utilization of the available tools to ensure maximum productivity. It is also very important to keep the operations as lean as possible to ensure cost effectiveness. In this research we will show that the cost additional capacity is outrages. This is the main reason more and more companies are opting out of fab owners club. Others are scaling down and going fables and fab-light. Capacity utilization and capacity maximization is the key to a successful fab. Fabs continuously look for ways to increase the capacity by improving productivity. Beyond certain productivity level, fabs must spend on purchasing tools. Semiconductor tools are expensive and in many cases there will be a need to spend in the support infrastructure. The escalating cost really brings out the creativity and innovation among the fab engineers. This paper discusses what actions are taken to address or mitigate this issue. The research is based on some available data from SilTerra Malaysia S dn Bhd wafer fab in Kulim.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124839641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920886
M. S. Alias, S. Kamaruddin, N. Nafarizal, M. Z. Sahdan
Organic solar cell is one of the fastest improving solar cells nowadays with improved power conversion efficiency approaching 10%. Here, we explore the performance of bulk heterojunction solar cell based on poly(3-hexyl thiophene) [P3HT] and [6,6]-phenyl-C61-butyric acid methyl ester [PCBM] by introducing ZnO nanoparticles buffer layer and appropriately tuning its energy level alignment by using different metal electrodes. The devices performance using two different high work function metal electrodes namely gold and platinum was investigated. The open circuit voltage (Voc) was obviously changed using different metal electrodes. The device with Platinum electrode shows higher Voc (0.2535 V) than the device with gold electrode by a factor of ~2. However, the efficiency was slightly lower than the gold device.
{"title":"Performance of inverted organic solar cell using different metal electrodes","authors":"M. S. Alias, S. Kamaruddin, N. Nafarizal, M. Z. Sahdan","doi":"10.1109/SMELEC.2014.6920886","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920886","url":null,"abstract":"Organic solar cell is one of the fastest improving solar cells nowadays with improved power conversion efficiency approaching 10%. Here, we explore the performance of bulk heterojunction solar cell based on poly(3-hexyl thiophene) [P3HT] and [6,6]-phenyl-C61-butyric acid methyl ester [PCBM] by introducing ZnO nanoparticles buffer layer and appropriately tuning its energy level alignment by using different metal electrodes. The devices performance using two different high work function metal electrodes namely gold and platinum was investigated. The open circuit voltage (Voc) was obviously changed using different metal electrodes. The device with Platinum electrode shows higher Voc (0.2535 V) than the device with gold electrode by a factor of ~2. However, the efficiency was slightly lower than the gold device.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125203538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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