Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920859
Salah Alkurwy, S. M. Md Ali, M. Islam
A Low Power Compressed ROM Look-up table has been presented in this paper to achieve low power consumption of the direct digital frequency synthesizer as well small core size. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The suggested 12-bit compressed ROM designed consists of three 4-bit sub-ROMs based on an angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2:1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz.
{"title":"Implementation of low power compressed ROM for direct digital frequency synthesizer","authors":"Salah Alkurwy, S. M. Md Ali, M. Islam","doi":"10.1109/SMELEC.2014.6920859","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920859","url":null,"abstract":"A Low Power Compressed ROM Look-up table has been presented in this paper to achieve low power consumption of the direct digital frequency synthesizer as well small core size. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The suggested 12-bit compressed ROM designed consists of three 4-bit sub-ROMs based on an angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2:1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116132254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920866
Ching-Hsiang Hsu, Hsun-Jui Chang, H. Yu, Hong-Quan Nguyen, J. Ma, E. Chang
Au-free, fully Cu-metallized InGaP/InGaAs/Ge triple-junction solar cells using Pd/Ge/Cu as front contact and Pt/Ti/Pt/Cu/Cr as back contact were fabricated and the results are reported for the first time. From the specific contact resistance measurement, these Cu-metallized ohmic contacts have low contact resistance in the order of 10-6 Ω-cm2. AES and TEM results clearly show the formation mechanisms of the Cu-metallization ohmic structures, for Pd/Ge/Cu contact, it was due to the formation of Ge diffusion into the GaAs layer, and for the Pt/Ti/Pt/Cu/Cr contact, it was due to high work function of Pt layer, these copper metallized ohmic contacts were quite stable even after 310 °C annealing. The I-V curves of the Cu-metallized InGaP/InGaAs/Ge triple-junction solar cells showed similar electrical characteristics to the solar cells with Au-metallized triple junction solar cell. Overall, the Pd/Ge/Cu and Pt/Ti/Pt/Cu ohmic contacts have been successfully applied to the InGaP/InGaAs/Ge triple-junction solar cells and demonstrated excellent performance.
{"title":"Gold-free Cu-metallized III-V solar cell","authors":"Ching-Hsiang Hsu, Hsun-Jui Chang, H. Yu, Hong-Quan Nguyen, J. Ma, E. Chang","doi":"10.1109/SMELEC.2014.6920866","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920866","url":null,"abstract":"Au-free, fully Cu-metallized InGaP/InGaAs/Ge triple-junction solar cells using Pd/Ge/Cu as front contact and Pt/Ti/Pt/Cu/Cr as back contact were fabricated and the results are reported for the first time. From the specific contact resistance measurement, these Cu-metallized ohmic contacts have low contact resistance in the order of 10-6 Ω-cm2. AES and TEM results clearly show the formation mechanisms of the Cu-metallization ohmic structures, for Pd/Ge/Cu contact, it was due to the formation of Ge diffusion into the GaAs layer, and for the Pt/Ti/Pt/Cu/Cr contact, it was due to high work function of Pt layer, these copper metallized ohmic contacts were quite stable even after 310 °C annealing. The I-V curves of the Cu-metallized InGaP/InGaAs/Ge triple-junction solar cells showed similar electrical characteristics to the solar cells with Au-metallized triple junction solar cell. Overall, the Pd/Ge/Cu and Pt/Ti/Pt/Cu ohmic contacts have been successfully applied to the InGaP/InGaAs/Ge triple-junction solar cells and demonstrated excellent performance.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134258103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920852
N. Iqbal, M. Baqir, P. Choudhury
Electromagnetic behavior of twisted clad optical fiber structure is investigated under the situation of core section being composed of chiral nihility metamaterial. Twists in the fiber clad are introduced in the form of sheath helical conductor loadings at the core-clad interface. The dispersion relation for the fiber structure is deduced and analyzed (considering low-order sustained hybrid modes) in respect of the effect on the dispersion characteristics due to the alterations in helix pitch angle. It have been found that the fiber structure generally shows decrease in normalized propagation constant with the increase normalized frequency parameter. Also, the dispersion behavior is greatly affected due to the variations in the angle of twists in the helix pitch.
{"title":"Dispersion characteristics of twisted clad chiral nihility fibers","authors":"N. Iqbal, M. Baqir, P. Choudhury","doi":"10.1109/SMELEC.2014.6920852","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920852","url":null,"abstract":"Electromagnetic behavior of twisted clad optical fiber structure is investigated under the situation of core section being composed of chiral nihility metamaterial. Twists in the fiber clad are introduced in the form of sheath helical conductor loadings at the core-clad interface. The dispersion relation for the fiber structure is deduced and analyzed (considering low-order sustained hybrid modes) in respect of the effect on the dispersion characteristics due to the alterations in helix pitch angle. It have been found that the fiber structure generally shows decrease in normalized propagation constant with the increase normalized frequency parameter. Also, the dispersion behavior is greatly affected due to the variations in the angle of twists in the helix pitch.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133281014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920786
M. Fathil, M. K. Md Arshad, U. Hashim, A. R. Ruslinda, R. Ayub, A. H. Azman, M. Nurfaiz, M. Z. Kamarudin, M. Aminuddin, A. Munir
This paper deals with minority carrier lifetime and carrier concentration of Cu(In, Ga)Se2 (CIGS)-based thin film solar cells with a ZnS(n)/CIGS(p) heterojunction structure. The structure is simulated in commercial numerical simulation and the impact of minority carrier lifetime in the CIGS absorber layer on the open circuit voltage, short circuit current density, fill factor and efficiency of the CIGS solar cell are investigated. The increase of minority carrier lifetime has also increased the CIGS solar cell performance. Similar effects are also observed at different carrier concentrations of CIGS layer. All these simulated results give a helpful indication for a practical fabrication process.
{"title":"The impact of minority carrier lifetime and carrier concentration on the efficiency of CIGS solar cell","authors":"M. Fathil, M. K. Md Arshad, U. Hashim, A. R. Ruslinda, R. Ayub, A. H. Azman, M. Nurfaiz, M. Z. Kamarudin, M. Aminuddin, A. Munir","doi":"10.1109/SMELEC.2014.6920786","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920786","url":null,"abstract":"This paper deals with minority carrier lifetime and carrier concentration of Cu(In, Ga)Se2 (CIGS)-based thin film solar cells with a ZnS(n)/CIGS(p) heterojunction structure. The structure is simulated in commercial numerical simulation and the impact of minority carrier lifetime in the CIGS absorber layer on the open circuit voltage, short circuit current density, fill factor and efficiency of the CIGS solar cell are investigated. The increase of minority carrier lifetime has also increased the CIGS solar cell performance. Similar effects are also observed at different carrier concentrations of CIGS layer. All these simulated results give a helpful indication for a practical fabrication process.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"77 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128283552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920858
Iffa Binti Sharuddin, L. Lee
An ultra-low power and area efficient successive approximation register (SAR) analog-to-digital converter (ADC) is presented. To achieve ultra-low power performance, a digital-to-analog converter (DAC) architecture is proposed that combined a 4-bit thermometer coded and a 6-bit C-2C array to form a 10-bit DAC. Thereby, power consumption and area of the design are drastically reduced by virtue of lower switching activity and smaller size capacitor array. Add on to that, the architecture also has better linearity. The proposed 10-bit DAC is designed and simulated in a 0.18 μm CMOS process. Simulation results show that it only consumed 1.74 nW at 1.5 V power supply.
{"title":"An ultra-low power and area efficient 10 bit digital to analog converter architecture","authors":"Iffa Binti Sharuddin, L. Lee","doi":"10.1109/SMELEC.2014.6920858","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920858","url":null,"abstract":"An ultra-low power and area efficient successive approximation register (SAR) analog-to-digital converter (ADC) is presented. To achieve ultra-low power performance, a digital-to-analog converter (DAC) architecture is proposed that combined a 4-bit thermometer coded and a 6-bit C-2C array to form a 10-bit DAC. Thereby, power consumption and area of the design are drastically reduced by virtue of lower switching activity and smaller size capacitor array. Add on to that, the architecture also has better linearity. The proposed 10-bit DAC is designed and simulated in a 0.18 μm CMOS process. Simulation results show that it only consumed 1.74 nW at 1.5 V power supply.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129233805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920878
S. T. Ten, U. Hashim, F. Malek, W. Liu, K. L. Foo, C. Voon, F. H. Wee, Y. S. Lee, H. Hisham, A. Sudin, M. S. Nur Humaira
Surface acoustic waves (SAW) devices have been initially developed and used for the high-volume low-cost TV component. Due to the ultra-sensitivity to the surface perturbation, SAW based devices have been modified to be sensors. Initially, SAW based sensors were developed for gas detection and recently they have been moving towards biological detection. Shear horizontal surface acoustic wave (SHSAW), one of the SAW based type is most suitable for the application in liquid based condition. Ultra sensitive pathogen sensors are needed to improve the food security and quality of life as well. Hence, the ultra-high sensitive biosensor has been designed in this research towards the low concentration pathogen detection. One of the main SHSAW components is the interdigital transducer (IDT). Currently, there are variety of techniques to fabricate the accurate size electrodes, Electron beam lithography and X-ray lithography. However, these methods are very costly. Therefore, this paper is presenting the more economical fabrication process which is using complementary metal-oxide-semiconductor method to fabricate inter-digital transducers on 640 YX LiNbO3 piezoelectric substrate. Comparisons were made for the theoretical calculation and fabricated measurement resonant frequency of the 3μm, 8 μm, 12 μm, 25 μm and 20μm width IDTs and the differences obtained are less than 5%.
{"title":"Fabrication of a CMOS-compatible surface acoustic wave device for application in pathogen sensing","authors":"S. T. Ten, U. Hashim, F. Malek, W. Liu, K. L. Foo, C. Voon, F. H. Wee, Y. S. Lee, H. Hisham, A. Sudin, M. S. Nur Humaira","doi":"10.1109/SMELEC.2014.6920878","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920878","url":null,"abstract":"Surface acoustic waves (SAW) devices have been initially developed and used for the high-volume low-cost TV component. Due to the ultra-sensitivity to the surface perturbation, SAW based devices have been modified to be sensors. Initially, SAW based sensors were developed for gas detection and recently they have been moving towards biological detection. Shear horizontal surface acoustic wave (SHSAW), one of the SAW based type is most suitable for the application in liquid based condition. Ultra sensitive pathogen sensors are needed to improve the food security and quality of life as well. Hence, the ultra-high sensitive biosensor has been designed in this research towards the low concentration pathogen detection. One of the main SHSAW components is the interdigital transducer (IDT). Currently, there are variety of techniques to fabricate the accurate size electrodes, Electron beam lithography and X-ray lithography. However, these methods are very costly. Therefore, this paper is presenting the more economical fabrication process which is using complementary metal-oxide-semiconductor method to fabricate inter-digital transducers on 640 YX LiNbO3 piezoelectric substrate. Comparisons were made for the theoretical calculation and fabricated measurement resonant frequency of the 3μm, 8 μm, 12 μm, 25 μm and 20μm width IDTs and the differences obtained are less than 5%.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132594937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920787
Michelle Lim, S. Ali, S. Jahariah, M. Islam
This work involves the modeling of three arbitrary input sources representing Hybrid Energy Harvesters (HEH) using a DC-DC Boost converter. These sources are combined in parallel and targeted at scavenging passive human power, therefore the three suitable ambient sources are motion, thermal and indoor light. Multiple sources mitigate limitations caused by single source harvesters but suffer impedance mismatches which greatly limit the total combined power that could have been harvested. A Boost Converter with suitable parameters has been designed and integrated to the HEH and PSPICE software has been used for both the modeling of arbitrary sources as well as the integration with the Boost Converter. An input source as low as 18 mV to 907 mV was able to be boosted into a 310 mV-27.9 V output when suitable parametric values were selected for the Ultra Low Power (ULP) HEH. A duty ratio of 0.5, with 10 kΩ load, 22 μH inductor as well as a switching frequency of 25 kHz was selected to be slightly above the audio range as well as being high enough to reduce passive component sizes. While VO/ VS of the boost converter is linear, PO/PIN is a function of third order polynomial. Therefore, at the HEH's lowest combined configuration of 1 K temperature difference, 0.25 g of vibration and 100 lux of indoor lighting, a combined 14 μW can be harvested. At its maximum of 10 K heat difference, 1 g vibration and 1000 lux of indoor lighting a combined 187 μW can be harvested. At its minimum, this enables possibility of battery-less applications in powering a quartz watch at 5 μW while at its maximum capacity powering a pace maker of ~50 μW as well as micro devices of ~100 μW solely from passive human activity. Once a 33 mF input capacitor is placed between the sources and converter, an output power of between 9.61 μW-78 mW can be obtained.
{"title":"Modelling of hybrid energy harvester with DC-DC boost converter using arbitary input sources for ultra-low-power micro-devices","authors":"Michelle Lim, S. Ali, S. Jahariah, M. Islam","doi":"10.1109/SMELEC.2014.6920787","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920787","url":null,"abstract":"This work involves the modeling of three arbitrary input sources representing Hybrid Energy Harvesters (HEH) using a DC-DC Boost converter. These sources are combined in parallel and targeted at scavenging passive human power, therefore the three suitable ambient sources are motion, thermal and indoor light. Multiple sources mitigate limitations caused by single source harvesters but suffer impedance mismatches which greatly limit the total combined power that could have been harvested. A Boost Converter with suitable parameters has been designed and integrated to the HEH and PSPICE software has been used for both the modeling of arbitrary sources as well as the integration with the Boost Converter. An input source as low as 18 mV to 907 mV was able to be boosted into a 310 mV-27.9 V output when suitable parametric values were selected for the Ultra Low Power (ULP) HEH. A duty ratio of 0.5, with 10 kΩ load, 22 μH inductor as well as a switching frequency of 25 kHz was selected to be slightly above the audio range as well as being high enough to reduce passive component sizes. While VO/ VS of the boost converter is linear, PO/PIN is a function of third order polynomial. Therefore, at the HEH's lowest combined configuration of 1 K temperature difference, 0.25 g of vibration and 100 lux of indoor lighting, a combined 14 μW can be harvested. At its maximum of 10 K heat difference, 1 g vibration and 1000 lux of indoor lighting a combined 187 μW can be harvested. At its minimum, this enables possibility of battery-less applications in powering a quartz watch at 5 μW while at its maximum capacity powering a pace maker of ~50 μW as well as micro devices of ~100 μW solely from passive human activity. Once a 33 mF input capacitor is placed between the sources and converter, an output power of between 9.61 μW-78 mW can be obtained.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129452060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920819
I. Saad, H. M. Zuhir, C. B. Seng, A. M. Khairul, B. Ghosh, N. Bolong, R. Ismail
This paper venture into prospective ideas of finding viable solution of nanoelectronics device design by an assessment of incorporating vertical impact-ionization MOSFET (IMOS) with strained SiGe technology into a formation of an emerging device structure with elevated performance and reliable outcomes for future bio-based sensor application. Impact Ionization FET biosensors can be extremely promising for applications where ultra-high sensitivity and fast response is desirable. An ultra-low power with low Subthreshold Swing and high breakdown voltage are imperative for ultra-sensitive biosensor. Impact ionization MOSFET (IMOS) is expected to have a subthreshold swing (S) down to 20 mV/dec which is much lower compared to Conventional MOSFET (CMOS). This will eventually enhanced the switching behavior of the transistor and enhancing its electrical performance and response time particularly when scaled down into nanometre regime. However, vertical IMOS experience parasitic bipolar transistors (PBT) effect and low breakdown voltage. Parasitic Bipolar Transistor effect is a phenomenon where the MOSFET act as a minority carrier device like BJT instead of majority carrier device. This is not favorable for any power device or sensor. Dielectric Pocket (DP) is believed to be able to minimize the PBT effect while improving the performance of the device. Eventually, this device will prolong the increase density of transistor in a chip for future application of biosensor nanoelectronics.
{"title":"Characterization of vertical strained SiGe impact ionization MOSFET for ultra-sensitive biosensor application","authors":"I. Saad, H. M. Zuhir, C. B. Seng, A. M. Khairul, B. Ghosh, N. Bolong, R. Ismail","doi":"10.1109/SMELEC.2014.6920819","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920819","url":null,"abstract":"This paper venture into prospective ideas of finding viable solution of nanoelectronics device design by an assessment of incorporating vertical impact-ionization MOSFET (IMOS) with strained SiGe technology into a formation of an emerging device structure with elevated performance and reliable outcomes for future bio-based sensor application. Impact Ionization FET biosensors can be extremely promising for applications where ultra-high sensitivity and fast response is desirable. An ultra-low power with low Subthreshold Swing and high breakdown voltage are imperative for ultra-sensitive biosensor. Impact ionization MOSFET (IMOS) is expected to have a subthreshold swing (S) down to 20 mV/dec which is much lower compared to Conventional MOSFET (CMOS). This will eventually enhanced the switching behavior of the transistor and enhancing its electrical performance and response time particularly when scaled down into nanometre regime. However, vertical IMOS experience parasitic bipolar transistors (PBT) effect and low breakdown voltage. Parasitic Bipolar Transistor effect is a phenomenon where the MOSFET act as a minority carrier device like BJT instead of majority carrier device. This is not favorable for any power device or sensor. Dielectric Pocket (DP) is believed to be able to minimize the PBT effect while improving the performance of the device. Eventually, this device will prolong the increase density of transistor in a chip for future application of biosensor nanoelectronics.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125222746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920891
M. Zakaria, S. R. Kasjoo, A. F. Mahyidin, A. W. Al-Mufti, R. Ayub, U. Hashim
Flash memory is a device that used as a tool to store data electrically without external power supply. The charge-trap such as SONOS structure is the most widely used in flash memory technology fabrication due to the advantages of this device in term of scaling and performance characteristic. Conventional Flash memory with thickness 5nm single oxide shows good performance, but suffer leakage current and data retention. To overcome this problem, a SONOS flash memory was fabricated by using techniques that known as Engineered Tunnel Barrier to replace the conventional single oxide used in conventional flash memory. In this project, the total equivalent thickness oxide for all experiments is set at the 8nm to compare the performances. Thus, it will result in a faster write and erase speed. The analysis results will determine the most preferred structure that improved the programming characteristic.
{"title":"Fabrication of SONOS flash memory device by using engineered tunnel barrier technique","authors":"M. Zakaria, S. R. Kasjoo, A. F. Mahyidin, A. W. Al-Mufti, R. Ayub, U. Hashim","doi":"10.1109/SMELEC.2014.6920891","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920891","url":null,"abstract":"Flash memory is a device that used as a tool to store data electrically without external power supply. The charge-trap such as SONOS structure is the most widely used in flash memory technology fabrication due to the advantages of this device in term of scaling and performance characteristic. Conventional Flash memory with thickness 5nm single oxide shows good performance, but suffer leakage current and data retention. To overcome this problem, a SONOS flash memory was fabricated by using techniques that known as Engineered Tunnel Barrier to replace the conventional single oxide used in conventional flash memory. In this project, the total equivalent thickness oxide for all experiments is set at the 8nm to compare the performances. Thus, it will result in a faster write and erase speed. The analysis results will determine the most preferred structure that improved the programming characteristic.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122442741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920844
M. A. Mohamed, B. Majlis, M. Ani
Electron state transition of deep level point defects in a semiconductor crystal was studied. Low-temperature grown GaAs produced excess antisite As (AsGa) which produces localized spin when doped with Be. A nearly abrupt decrease of 1.7% of the resistance is detected at a temperature around 4 K which is consistent with abrupt decrease of magnetization. These observations are explained as a result of cooperative transition of electron states of AsGa defects. First-principal calculations of the electron state of an AsGa atom with a shallow acceptor Be show that at the transition an AsGa+ ion is displaced to the interstitial site and becomes a neutral atom and finally results in formation of a hole producing enhancement in conductivity.
{"title":"Electronic state transition in cooperatively interacting point-defects in semiconductor crystals","authors":"M. A. Mohamed, B. Majlis, M. Ani","doi":"10.1109/SMELEC.2014.6920844","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920844","url":null,"abstract":"Electron state transition of deep level point defects in a semiconductor crystal was studied. Low-temperature grown GaAs produced excess antisite As (AsGa) which produces localized spin when doped with Be. A nearly abrupt decrease of 1.7% of the resistance is detected at a temperature around 4 K which is consistent with abrupt decrease of magnetization. These observations are explained as a result of cooperative transition of electron states of AsGa defects. First-principal calculations of the electron state of an AsGa atom with a shallow acceptor Be show that at the transition an AsGa+ ion is displaced to the interstitial site and becomes a neutral atom and finally results in formation of a hole producing enhancement in conductivity.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116535142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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