Resistive bridges not only cause a static faulty behavior in CMOS memories, but also lead to several dynamic faulty behaviors which are timing related failures. This paper introduces a new realistic dynamic fault model for random access-memories: the delay coupling fault, which models resistive bridges in the memory array. We show that well-known march tests do not cover delay coupling faults at the memory array. To cover the delay coupling faults, a new and efficient test algorithm (DITEC+) is presented. We have performed inductive fault analysis to validate this novel algorithm and shown a significant improvement on fault coverage. Also, experiment on silicon is carried out to show the existence of such dynamic faults and their detection by implementing DITEC+.
{"title":"A new algorithm for dynamic faults detection in RAMs","authors":"M. Azimane, A. Majhi, G. Gronthoud, M. Lousberg","doi":"10.1109/VTS.2005.9","DOIUrl":"https://doi.org/10.1109/VTS.2005.9","url":null,"abstract":"Resistive bridges not only cause a static faulty behavior in CMOS memories, but also lead to several dynamic faulty behaviors which are timing related failures. This paper introduces a new realistic dynamic fault model for random access-memories: the delay coupling fault, which models resistive bridges in the memory array. We show that well-known march tests do not cover delay coupling faults at the memory array. To cover the delay coupling faults, a new and efficient test algorithm (DITEC+) is presented. We have performed inductive fault analysis to validate this novel algorithm and shown a significant improvement on fault coverage. Also, experiment on silicon is carried out to show the existence of such dynamic faults and their detection by implementing DITEC+.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125386426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The delay variations of a pattern set can come from two sources: (1) Different patterns sensitize different parts of the circuit and result in different delays. (2) The same pattern, applied on different chips, results in different delays because of process variations. For structural delay testing, these pattern variations may result in difficulty for finding an optimal test clock setting, which may significantly impact the defect screening effectiveness. This paper investigates the possibility of applying statistical timing analysis techniques to reduce pattern variations for structural delay testing. We develop an efficient statistical pattern-based timing simulator and devise pattern selection algorithms for reducing such variations. By constructing pattern sets with smaller variations, we show that higher screening effectiveness can be achieved. We present experimental results to demonstrate the advantages of our techniques based on benchmark circuits.
{"title":"Reducing pattern delay variations for screening frequency dependent defects","authors":"Benjamin N. Lee, Li-C. Wang, M. Abadir","doi":"10.1109/VTS.2005.70","DOIUrl":"https://doi.org/10.1109/VTS.2005.70","url":null,"abstract":"The delay variations of a pattern set can come from two sources: (1) Different patterns sensitize different parts of the circuit and result in different delays. (2) The same pattern, applied on different chips, results in different delays because of process variations. For structural delay testing, these pattern variations may result in difficulty for finding an optimal test clock setting, which may significantly impact the defect screening effectiveness. This paper investigates the possibility of applying statistical timing analysis techniques to reduce pattern variations for structural delay testing. We develop an efficient statistical pattern-based timing simulator and devise pattern selection algorithms for reducing such variations. By constructing pattern sets with smaller variations, we show that higher screening effectiveness can be achieved. We present experimental results to demonstrate the advantages of our techniques based on benchmark circuits.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125453092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we have made a complete analysis of the emerging SRAM failure mechanisms due to process variations and mapped them to fault models. We have proposed two efficient test solutions for the process variation related failures in SRAM: (a) modification of March sequence, and (b) a low-overhead DFT circuit to complement the March test for an overall test time reduction of 29%, compared to the existing test technique with similar fault coverage.
{"title":"Modeling and testing of SRAM for new failure mechanisms due to process variations in nanoscale CMOS","authors":"Qikai Chen, H. Mahmoodi, S. Bhunia, K. Roy","doi":"10.1109/VTS.2005.58","DOIUrl":"https://doi.org/10.1109/VTS.2005.58","url":null,"abstract":"In this paper, we have made a complete analysis of the emerging SRAM failure mechanisms due to process variations and mapped them to fault models. We have proposed two efficient test solutions for the process variation related failures in SRAM: (a) modification of March sequence, and (b) a low-overhead DFT circuit to complement the March test for an overall test time reduction of 29%, compared to the existing test technique with similar fault coverage.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132167558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, M. Bastian
In this paper, we present a novel study on data retention faults (DRFs) in SRAM memories. We analyze in detail the electrical origins of these faults, starting from the most common till those that lead to what we have called hard to detect DRFs. In general, DRFs are supposed to be produced by very high resistive-open defects that affect the refreshment loop of the core-cell. We demonstrate that lower values of resistance may produce hard to detect DRFs. Moreover, each resistive-open defect produces a particular faulty behavior of the core-cell that changes for different ranges of the resistive value. We analyze different cases and we propose for each one an efficient test procedure based on March tests. In particular, we propose to stimulate the defective cells in some cases by indirect accesses and in some other cases by emphasizing natural noise phenomenon of SRAM memories (such as the ground bounce).
{"title":"Data retention fault in SRAM memories: analysis and detection procedures","authors":"L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, M. Bastian","doi":"10.1109/VTS.2005.37","DOIUrl":"https://doi.org/10.1109/VTS.2005.37","url":null,"abstract":"In this paper, we present a novel study on data retention faults (DRFs) in SRAM memories. We analyze in detail the electrical origins of these faults, starting from the most common till those that lead to what we have called hard to detect DRFs. In general, DRFs are supposed to be produced by very high resistive-open defects that affect the refreshment loop of the core-cell. We demonstrate that lower values of resistance may produce hard to detect DRFs. Moreover, each resistive-open defect produces a particular faulty behavior of the core-cell that changes for different ranges of the resistive value. We analyze different cases and we propose for each one an efficient test procedure based on March tests. In particular, we propose to stimulate the defective cells in some cases by indirect accesses and in some other cases by emphasizing natural noise phenomenon of SRAM memories (such as the ground bounce).","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128023696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel and pragmatic built-in self test technique provides cost-effective and thorough testing and diagnosis of content addressable memories (CAMS). The method is particularly attractive for write-only CAMS, as neither the presence of a read port nor direct observability of CAM match-lines are required or testing. The underlying test algorithm uniquely exploits little known inherent properties of pseudorandom patterns generated by linear feedback shift registers in a test-time and hardware-efficient BIST implementation.
{"title":"A built-in self-test method for write-only content addressable memories","authors":"D.K. Bhaysar","doi":"10.1109/VTS.2005.7","DOIUrl":"https://doi.org/10.1109/VTS.2005.7","url":null,"abstract":"A novel and pragmatic built-in self test technique provides cost-effective and thorough testing and diagnosis of content addressable memories (CAMS). The method is particularly attractive for write-only CAMS, as neither the presence of a read port nor direct observability of CAM match-lines are required or testing. The underlying test algorithm uniquely exploits little known inherent properties of pseudorandom patterns generated by linear feedback shift registers in a test-time and hardware-efficient BIST implementation.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124033525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. U. Diril, Y. S. Dhillon, A. Chatterjee, A. Singh
Nanometer circuits are highly susceptible to soft errors generated by alpha-particle or atmospheric neutron strikes to circuit nodes. The reasons for the high susceptibility are the reduced node capacitances and noise margins caused by feature size and supply voltage scaling. Static soft error optimization (such as concurrent error detection or gate resizing) can be very expensive in terms of power consumption if the circuit is not always exposed to high flux of particles. This paper proposes a scheme for dynamic control of soft error tolerance in digital circuits that has negligible power and delay overhead when the circuit is in its normal mode of operation. The key objective is to design circuits that can adapt to different radiation conditions with minimal power overhead. The soft error rate of the circuit is monitored by simple on-chip circuitry, and circuit soft error tolerance is controlled by using dynamic supply voltage and threshold voltage modulation together with variable capacitance banks.
{"title":"Design of adaptive nanometer digital systems for effective control of soft error tolerance","authors":"A. U. Diril, Y. S. Dhillon, A. Chatterjee, A. Singh","doi":"10.1109/VTS.2005.40","DOIUrl":"https://doi.org/10.1109/VTS.2005.40","url":null,"abstract":"Nanometer circuits are highly susceptible to soft errors generated by alpha-particle or atmospheric neutron strikes to circuit nodes. The reasons for the high susceptibility are the reduced node capacitances and noise margins caused by feature size and supply voltage scaling. Static soft error optimization (such as concurrent error detection or gate resizing) can be very expensive in terms of power consumption if the circuit is not always exposed to high flux of particles. This paper proposes a scheme for dynamic control of soft error tolerance in digital circuits that has negligible power and delay overhead when the circuit is in its normal mode of operation. The key objective is to design circuits that can adapt to different radiation conditions with minimal power overhead. The soft error rate of the circuit is monitored by simple on-chip circuitry, and circuit soft error tolerance is controlled by using dynamic supply voltage and threshold voltage modulation together with variable capacitance banks.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130837288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we propose a novel buffer scheme that is able to compensate undesired skews between clocks of a synchronous system in a negligible time upon skew occurrence, thus being suitable also for on-line clock-skew correction. Clock signals are aligned one with respect to the other, starting from a reference clock, and moving forward among physically adjacent clock signals, thus creating no problem of reference clock's routing. Our solution is also able to compensate clock duty-cycle variations, which have been shown very likely in case of faults, for instance bridgings, affecting the clock distribution network. Compared to alternate solutions, our proposed scheme enables significant reductions in area overhead and power consumption, and is suitable for on-line compensation. Therefore, it allows clock skew and duty-cycle fault tolerance, thus increasing process yield and system's reliability.
{"title":"Low cost scheme for on-line clock skew compensation","authors":"M. Omaña, Daniele Rossi, C. Metra","doi":"10.1109/VTS.2005.52","DOIUrl":"https://doi.org/10.1109/VTS.2005.52","url":null,"abstract":"In this paper we propose a novel buffer scheme that is able to compensate undesired skews between clocks of a synchronous system in a negligible time upon skew occurrence, thus being suitable also for on-line clock-skew correction. Clock signals are aligned one with respect to the other, starting from a reference clock, and moving forward among physically adjacent clock signals, thus creating no problem of reference clock's routing. Our solution is also able to compensate clock duty-cycle variations, which have been shown very likely in case of faults, for instance bridgings, affecting the clock distribution network. Compared to alternate solutions, our proposed scheme enables significant reductions in area overhead and power consumption, and is suitable for on-line compensation. Therefore, it allows clock skew and duty-cycle fault tolerance, thus increasing process yield and system's reliability.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128043055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Leonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak
Speed path identification is an indispensable step for pushing the design timing wall and for developing the final speed binning strategy in production test. For complex high-performance designs, pre-silicon timing tools have so far not been able to deliver satisfactory results in predicting the actual speed limiting paths on the silicon. The actual speed paths are mostly uncovered through test and silicon debug, where tremendous manual effort is involved. This paper presents a novel approach as the first step for automating the speed path identification process. Our approach is silicon-based, meaning that timing information is extracted through testing of silicon sample chips. We call this step silicon learning. Based on silicon learning, we present an iterative flow for speed path identification. Experimental results are presented to explain the new methodologies and to demonstrate the effectiveness of our techniques.
{"title":"On silicon-based speed path identification","authors":"Leonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak","doi":"10.1109/VTS.2005.61","DOIUrl":"https://doi.org/10.1109/VTS.2005.61","url":null,"abstract":"Speed path identification is an indispensable step for pushing the design timing wall and for developing the final speed binning strategy in production test. For complex high-performance designs, pre-silicon timing tools have so far not been able to deliver satisfactory results in predicting the actual speed limiting paths on the silicon. The actual speed paths are mostly uncovered through test and silicon debug, where tremendous manual effort is involved. This paper presents a novel approach as the first step for automating the speed path identification process. Our approach is silicon-based, meaning that timing information is extracted through testing of silicon sample chips. We call this step silicon learning. Based on silicon learning, we present an iterative flow for speed path identification. Experimental results are presented to explain the new methodologies and to demonstrate the effectiveness of our techniques.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134520201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a pseudo-functional BIST scheme that attempts to minimize the over-testing problem of logic BIST for delay and crosstalk-induced failures. The over-testing problem is evident from the non-trivial number of structurally testable while functionally untestable (ST-FU) faults. Such faults can be detected by some scan/BIST patterns but not by any functional pattern. The goal of this BIST scheme is to allow only functional-like patterns generated from the BIST random test pattern generator (RTPG) as tests. This is done by inserting a Monitor at the output of the RTPG, which indicates whether the current pattern violates some pre-extracted functional constraints. In case of violation, the pattern is skipped. In our implementation, a SAT solver is used to analyze and extract a set of functional constraints from the functional logic. These functional constraints are then implemented in hardware as the Monitor. Even though the extracted functional constraints can not be exhausted, the proposed BIST scheme can detect and filter out, in real-time, a substantial subset of the nonfunctional patterns, and thus minimizing the over-testing problem. We present some experimental results to demonstrate the effectiveness of the proposed BIST scheme.
{"title":"Pseudo-functional scan-based BIST for delay fault","authors":"Yung-Chieh Lin, Feng Lu, K. Cheng","doi":"10.1109/VTS.2005.69","DOIUrl":"https://doi.org/10.1109/VTS.2005.69","url":null,"abstract":"This paper presents a pseudo-functional BIST scheme that attempts to minimize the over-testing problem of logic BIST for delay and crosstalk-induced failures. The over-testing problem is evident from the non-trivial number of structurally testable while functionally untestable (ST-FU) faults. Such faults can be detected by some scan/BIST patterns but not by any functional pattern. The goal of this BIST scheme is to allow only functional-like patterns generated from the BIST random test pattern generator (RTPG) as tests. This is done by inserting a Monitor at the output of the RTPG, which indicates whether the current pattern violates some pre-extracted functional constraints. In case of violation, the pattern is skipped. In our implementation, a SAT solver is used to analyze and extract a set of functional constraints from the functional logic. These functional constraints are then implemented in hardware as the Monitor. Even though the extracted functional constraints can not be exhausted, the proposed BIST scheme can detect and filter out, in real-time, a substantial subset of the nonfunctional patterns, and thus minimizing the over-testing problem. We present some experimental results to demonstrate the effectiveness of the proposed BIST scheme.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131141109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The recent increase in demand within the wireless user community for short-range, very high rate data transmission (data, video) devices has spurred the growth of a new generation of 4G devices, viz. ultra-wideband (UWB). Due to its wide band of operation (3.1-10.6GHz) and non-conventional transmit/receive scheme (using short-duration, narrow baseband pulses), spectral power leakage to outside frequency bands causes interference with other wireless standards. In this paper, we focus on 'out-of-band' interference testing of UWB devices during production test. Due to stringent FCC spectrum regulations and very low power spectral density levels of the associated signals (-41.3dBm/MHz), production testing for interference is a big challenge and can incur significant test time, resulting in increased test cost. We propose a simple, low-cost test methodology for testing UWB devices. Simulation results are presented for a typical home environment. The channel model used can be easily modified and incorporated in any production test environment. Results show that using simple tests, estimates of 'out-of-band' interference can be obtained easily using the proposed test methodology.
{"title":"Production test methods for measuring 'out-of-band' interference of ultra wide band (UWB) devices","authors":"S. Bhattacharya, A. Chatterjee","doi":"10.1109/VTS.2005.67","DOIUrl":"https://doi.org/10.1109/VTS.2005.67","url":null,"abstract":"The recent increase in demand within the wireless user community for short-range, very high rate data transmission (data, video) devices has spurred the growth of a new generation of 4G devices, viz. ultra-wideband (UWB). Due to its wide band of operation (3.1-10.6GHz) and non-conventional transmit/receive scheme (using short-duration, narrow baseband pulses), spectral power leakage to outside frequency bands causes interference with other wireless standards. In this paper, we focus on 'out-of-band' interference testing of UWB devices during production test. Due to stringent FCC spectrum regulations and very low power spectral density levels of the associated signals (-41.3dBm/MHz), production testing for interference is a big challenge and can incur significant test time, resulting in increased test cost. We propose a simple, low-cost test methodology for testing UWB devices. Simulation results are presented for a typical home environment. The channel model used can be easily modified and incorporated in any production test environment. Results show that using simple tests, estimates of 'out-of-band' interference can be obtained easily using the proposed test methodology.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115157195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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