R. Turakhia, B. Benware, R. Madge, Fort Collins, OR Gresham, T. Shannon, Robert Daasch
An I/sub DDQ/ Statistical Post-Processing/spl trade/ (SPP) outlier screen is presented based on the computation of statistically independent sources of variation in the I/sub DDQ/ measurements. I/sub DDQ/ measurements from die passing all other tests are modeled using sources of variation extracted by independent component analysis (ICA). Outliers are separated from the sample population based on residuals computed using these sources and a nearest neighbor spatial signature. An algorithm is presented for applying the proposed technique in production. The screen is demonstrated with 0.18/spl mu/m and 0.11/spl mu/m volume data and shown to effectively identify the outliers at the 0.1 /spl mu/m technology node.
{"title":"Defect screening using independent component analysis on I/sub DDQ/","authors":"R. Turakhia, B. Benware, R. Madge, Fort Collins, OR Gresham, T. Shannon, Robert Daasch","doi":"10.1109/VTS.2005.38","DOIUrl":"https://doi.org/10.1109/VTS.2005.38","url":null,"abstract":"An I/sub DDQ/ Statistical Post-Processing/spl trade/ (SPP) outlier screen is presented based on the computation of statistically independent sources of variation in the I/sub DDQ/ measurements. I/sub DDQ/ measurements from die passing all other tests are modeled using sources of variation extracted by independent component analysis (ICA). Outliers are separated from the sample population based on residuals computed using these sources and a nearest neighbor spatial signature. An algorithm is presented for applying the proposed technique in production. The screen is demonstrated with 0.18/spl mu/m and 0.11/spl mu/m volume data and shown to effectively identify the outliers at the 0.1 /spl mu/m technology node.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114081017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Wohl, J. Waicukauski, Sanjay B. Patel, C. Hay, Emil Gizdarski, B. Mathew
Scan-based tests created by automatic test pattern generators (ATPG) can be efficiently compressed and applied in a deterministic built-in self-test (DBIST) architecture. However, the BIST environment adds significant complexity to failure diagnosis. We present a simple scan-compatible diagnosis solution - streaming DBIST (SDBIST), which is based on a low-overhead hierarchical compactor SDBIST allows continuously monitoring streaming scanout data for reduced-volume expect-data diagnosis, on-line fail-data collection and selective scan cell masking.
{"title":"Hierarchical compactor design for diagnosis in deterministic logic BIST","authors":"P. Wohl, J. Waicukauski, Sanjay B. Patel, C. Hay, Emil Gizdarski, B. Mathew","doi":"10.1109/VTS.2005.48","DOIUrl":"https://doi.org/10.1109/VTS.2005.48","url":null,"abstract":"Scan-based tests created by automatic test pattern generators (ATPG) can be efficiently compressed and applied in a deterministic built-in self-test (DBIST) architecture. However, the BIST environment adds significant complexity to failure diagnosis. We present a simple scan-compatible diagnosis solution - streaming DBIST (SDBIST), which is based on a low-overhead hierarchical compactor SDBIST allows continuously monitoring streaming scanout data for reduced-volume expect-data diagnosis, on-line fail-data collection and selective scan cell masking.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116429728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Baosheng Wang, Yuejian Wu, Josh Yang, A. Ivanov, Y. Zorian
Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typically time-consuming due to the required pause time that needs to be introduced in the test session. This paper proposes a novel technique, referred to as pre-discharge write test mode (PDWTM), that effectively integrates the testing of DRF within "regular" March algorithms such that the rate (speed) of the latter remains unaltered. That is, the PDWTM enables DRF testing without incurring the additional cycles or pauses in the March test execution thereby enabling additional coverage at no expense in terms of overall test time. We show that DRFs can be easily detected by pre-discharging bit lines before a write operation. Here, the PDWTM is evaluated using both high-speed and low power memory cells, representing two extreme cases based on the typical memory design methodologies.
{"title":"SRAM retention testing: zero incremental time integration with March algorithms","authors":"Baosheng Wang, Yuejian Wu, Josh Yang, A. Ivanov, Y. Zorian","doi":"10.1109/VTS.2005.76","DOIUrl":"https://doi.org/10.1109/VTS.2005.76","url":null,"abstract":"Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typically time-consuming due to the required pause time that needs to be introduced in the test session. This paper proposes a novel technique, referred to as pre-discharge write test mode (PDWTM), that effectively integrates the testing of DRF within \"regular\" March algorithms such that the rate (speed) of the latter remains unaltered. That is, the PDWTM enables DRF testing without incurring the additional cycles or pauses in the March test execution thereby enabling additional coverage at no expense in terms of overall test time. We show that DRFs can be easily detected by pre-discharging bit lines before a write operation. Here, the PDWTM is evaluated using both high-speed and low power memory cells, representing two extreme cases based on the typical memory design methodologies.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128766230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Polian, S. Kundu, J. Gallière, P. Engelke, M. Renovell, B. Becker
We present three resistive bridging fault models valid for different CMOS technologies. The models are partitioned into a general framework (which is shared by all three models) and a technology-specific part. The first model is based on Shockley equations and is valid for conventional but not deep submicron CMOS. The second model is obtained by fitting SPICE data. The third resistive bridging fault model uses Berkeley predictive technology model and BSIM4; it is valid for CMOS technologies with feature sizes of 90nm and below, accurately describing non-trivial electrical behavior in that technologies. Experimental results for ISCAS circuits show that the test patterns obtained for the Shockley model are still valid for the fitted model, but lead to coverage loss under the predictive model.
{"title":"Resistive Bridge fault model evolution from conventional to ultra deep submicron","authors":"I. Polian, S. Kundu, J. Gallière, P. Engelke, M. Renovell, B. Becker","doi":"10.1109/VTS.2005.72","DOIUrl":"https://doi.org/10.1109/VTS.2005.72","url":null,"abstract":"We present three resistive bridging fault models valid for different CMOS technologies. The models are partitioned into a general framework (which is shared by all three models) and a technology-specific part. The first model is based on Shockley equations and is valid for conventional but not deep submicron CMOS. The second model is obtained by fitting SPICE data. The third resistive bridging fault model uses Berkeley predictive technology model and BSIM4; it is valid for CMOS technologies with feature sizes of 90nm and below, accurately describing non-trivial electrical behavior in that technologies. Experimental results for ISCAS circuits show that the test patterns obtained for the Shockley model are still valid for the fitted model, but lead to coverage loss under the predictive model.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122014859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we present a novel and accurate method for identifying design for testability (DFT) solutions for register-transfer level (RTL) circuits. In this technique, clauses are generated using a satisfiability (SAT) based automatic test pattern generation (ATPG) tool to represent the control and data flow for a module under test in the given RTL circuit. RTL test generation makes use of the concept of pre-computed test sets for different RTL modules. The generated clauses corresponding to different pre-computed test vectors are then resolved by a SAT solver to obtain the test sequences for that module. In case of an unsatisfiable (UNSAT) solution, recent advances in the field of satisfiability enable us to accurately and efficiently identify clauses that are responsible for unsatisfiability (also known as the unsatisfiable segment). We show that adding DFT elements is equivalent to modifying clauses such that the unsatisfiable segment becomes satisfiable. In order to minimize the number of DFT elements added to a circuit, a greedy algorithm is used to select circuit variables for DFT such that all the unsatisfiable segments become satisfiable. Unlike existing DFT techniques that are either inefficient in terms of the amount of test hardware added or take significant time to identify an efficient solution, the proposed DFT technique is both fast and accurate as it is applicable to RTL and mixed gate-level/RTL circuits and uses UNSAT to identify the DFT solutions. Experimental results on benchmarks show that for RTL circuits, the CPU time required to identify pre-computed test vectors for which the SAT ATPG fails to generate test sequences and to select DFT solutions for such cases is two orders of magnitude smaller than the time required for a single run of a gate-level sequential test generator. The DFT solution has very low area overhead (an average of 1.7%) and results in near-100% fault coverage.
{"title":"Unsatisfiability based efficient design for testability solution for register-transfer level circuits","authors":"L. Lingappan, N. Jha","doi":"10.1109/VTS.2005.88","DOIUrl":"https://doi.org/10.1109/VTS.2005.88","url":null,"abstract":"In this paper, we present a novel and accurate method for identifying design for testability (DFT) solutions for register-transfer level (RTL) circuits. In this technique, clauses are generated using a satisfiability (SAT) based automatic test pattern generation (ATPG) tool to represent the control and data flow for a module under test in the given RTL circuit. RTL test generation makes use of the concept of pre-computed test sets for different RTL modules. The generated clauses corresponding to different pre-computed test vectors are then resolved by a SAT solver to obtain the test sequences for that module. In case of an unsatisfiable (UNSAT) solution, recent advances in the field of satisfiability enable us to accurately and efficiently identify clauses that are responsible for unsatisfiability (also known as the unsatisfiable segment). We show that adding DFT elements is equivalent to modifying clauses such that the unsatisfiable segment becomes satisfiable. In order to minimize the number of DFT elements added to a circuit, a greedy algorithm is used to select circuit variables for DFT such that all the unsatisfiable segments become satisfiable. Unlike existing DFT techniques that are either inefficient in terms of the amount of test hardware added or take significant time to identify an efficient solution, the proposed DFT technique is both fast and accurate as it is applicable to RTL and mixed gate-level/RTL circuits and uses UNSAT to identify the DFT solutions. Experimental results on benchmarks show that for RTL circuits, the CPU time required to identify pre-computed test vectors for which the SAT ATPG fails to generate test sequences and to select DFT solutions for such cases is two orders of magnitude smaller than the time required for a single run of a gate-level sequential test generator. The DFT solution has very low area overhead (an average of 1.7%) and results in near-100% fault coverage.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121918589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. C. Koob, S. A. Ung, Ashwin S. Rao, Daniel A. Leder, Craig S. Joly, K.C. Breen, T. Brandon, M. Hume, B. Cockburn, D. Elliott
Multilevel DRAM (MLDRAM) increases the storage density of DRAMs by using more than two data signal levels in the storage cells. An operational 19200-cell MLDRAM in 1.8-V 0.18-/spl mu/m mixed-signal CMOS is described that allows 1, 1.5, 2, 2.25 and 2.5 bits-per-cell operation using 2, 3, 4, 5 and 6 data signal levels, respectively. The MLDRAM uses reference and data cell signals that are generated in the cell array using charge sharing. The single-step sensing method uses multiple reference signals in parallel. Test chip characterization features include four cell sizes, two sense amplifier sizes, and bitline shields for half of the cells. New tests were developed based on an MLDRAM fault model. These include basic functionality, retention time, multilevel march, inter-bitline coupling, and cell-plate voltage bump tests. Our results show that the data and reference signals are generated correctly and that MLDRAM is possible for up to six signal levels.
多电平DRAM (MLDRAM)通过在存储单元中使用两个以上的数据信号电平来增加DRAM的存储密度。描述了一种可操作的19200单元MLDRAM，采用1.8 v 0.18-/spl mu/m混合信号CMOS，分别使用2、3、4、5和6个数据信号电平，允许1,1.5、2、2.25和2.5位/单元操作。MLDRAM使用在单元阵列中使用电荷共享产生的参考和数据单元信号。单步传感方法采用多个参考信号并联。测试芯片的特性特征包括四种单元尺寸，两种感测放大器尺寸，以及一半单元的位线屏蔽。基于MLDRAM故障模型开发了新的测试方法。这些测试包括基本功能、保持时间、多级行进、位线间耦合和电池板电压碰撞测试。我们的结果表明，数据和参考信号的生成是正确的，并且MLDRAM可以达到6个信号电平。
{"title":"Test and characterization of a variable-capacity multilevel DRAM","authors":"J. C. Koob, S. A. Ung, Ashwin S. Rao, Daniel A. Leder, Craig S. Joly, K.C. Breen, T. Brandon, M. Hume, B. Cockburn, D. Elliott","doi":"10.1109/VTS.2005.82","DOIUrl":"https://doi.org/10.1109/VTS.2005.82","url":null,"abstract":"Multilevel DRAM (MLDRAM) increases the storage density of DRAMs by using more than two data signal levels in the storage cells. An operational 19200-cell MLDRAM in 1.8-V 0.18-/spl mu/m mixed-signal CMOS is described that allows 1, 1.5, 2, 2.25 and 2.5 bits-per-cell operation using 2, 3, 4, 5 and 6 data signal levels, respectively. The MLDRAM uses reference and data cell signals that are generated in the cell array using charge sharing. The single-step sensing method uses multiple reference signals in parallel. Test chip characterization features include four cell sizes, two sense amplifier sizes, and bitline shields for half of the cells. New tests were developed based on an MLDRAM fault model. These include basic functionality, retention time, multilevel march, inter-bitline coupling, and cell-plate voltage bump tests. Our results show that the data and reference signals are generated correctly and that MLDRAM is possible for up to six signal levels.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129036494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gustavo Pereira, A. Andrade, T. Balen, M. Lubaszewski, F. Azaïs, M. Renovell
The test of field programmable analog arrays (FPAA) may be performed based on partitioning these devices in three main parts: I/O cells, interconnection networks and configurable analog blocks. In this work, a scheme for testing the I/O cells and the local and global interconnection networks of FPAAs is proposed, using an adjacency graph model to represent the programmable interconnection and I/O resources, and then devising a set of test configurations (TC) by solving graph coloring problems. The goal is to achieve a near minimum number of TCs ensuring all stuck-open and stuck-on faults in switches, as well as opens and shorts in wires, are covered. Large parametric faults in interconnects are implicitly covered in these TCs by judiciously choosing test stimuli and, in I/O buffers, by means of an oscillation-based test strategy.
{"title":"Testing the interconnect networks and I/O resources of field programmable analog arrays","authors":"Gustavo Pereira, A. Andrade, T. Balen, M. Lubaszewski, F. Azaïs, M. Renovell","doi":"10.1109/VTS.2005.85","DOIUrl":"https://doi.org/10.1109/VTS.2005.85","url":null,"abstract":"The test of field programmable analog arrays (FPAA) may be performed based on partitioning these devices in three main parts: I/O cells, interconnection networks and configurable analog blocks. In this work, a scheme for testing the I/O cells and the local and global interconnection networks of FPAAs is proposed, using an adjacency graph model to represent the programmable interconnection and I/O resources, and then devising a set of test configurations (TC) by solving graph coloring problems. The goal is to achieve a near minimum number of TCs ensuring all stuck-open and stuck-on faults in switches, as well as opens and shorts in wires, are covered. Large parametric faults in interconnects are implicitly covered in these TCs by judiciously choosing test stimuli and, in I/O buffers, by means of an oscillation-based test strategy.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125612813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Hakmi, H. Wunderlich, V. Gherman, Michael Garbers, J. Schlöffel
A method for test resource partitioning is introduced which keeps the design-for-test logic test set independent and moves the test pattern dependent information to an external, programmable chip. The scheme includes a new decompression scheme for a fast and efficient communication between the external test chip and the circuit under test. The hardware costs on chip are significantly lower compared with a deterministic BIST scheme while the test application time is still in the same range. The proposed scheme is fully programmable, flexible and can be reused at board level for testing in the field.
{"title":"Implementing a scheme for external deterministic self-test","authors":"A. Hakmi, H. Wunderlich, V. Gherman, Michael Garbers, J. Schlöffel","doi":"10.1109/VTS.2005.50","DOIUrl":"https://doi.org/10.1109/VTS.2005.50","url":null,"abstract":"A method for test resource partitioning is introduced which keeps the design-for-test logic test set independent and moves the test pattern dependent information to an external, programmable chip. The scheme includes a new decompression scheme for a fast and efficient communication between the external test chip and the circuit under test. The hardware costs on chip are significantly lower compared with a deterministic BIST scheme while the test application time is still in the same range. The proposed scheme is fully programmable, flexible and can be reused at board level for testing in the field.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"1256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115829156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The exponential increase in the number of transistors implemented in integrated circuits in each new generation of CMOS technology is causing an explosion not only in functional power consumption but in test power consumption as well. Although most research has focused mainly on reducing average power or the total energy consumed during test, instantaneous power consumption is also increasing and posing a serious threat for the ability of a chip to be tested in a manufacturing test floor - or worse in field testing using built-in-self test (BIST) where battery-powered applications lack the supply voltage robustness of automated test equipment (ATE). In this paper, a flip-flop design is proposed that is the cornerstone of a novel scan clocking architecture inspired by the need to reduce instantaneous power during scan.
{"title":"Reductions of instantaneous power by ripple scan clocking","authors":"Kirti Joshi, E. MacDonald","doi":"10.1109/VTS.2005.71","DOIUrl":"https://doi.org/10.1109/VTS.2005.71","url":null,"abstract":"The exponential increase in the number of transistors implemented in integrated circuits in each new generation of CMOS technology is causing an explosion not only in functional power consumption but in test power consumption as well. Although most research has focused mainly on reducing average power or the total energy consumed during test, instantaneous power consumption is also increasing and posing a serious threat for the ability of a chip to be tested in a manufacturing test floor - or worse in field testing using built-in-self test (BIST) where battery-powered applications lack the supply voltage robustness of automated test equipment (ATE). In this paper, a flip-flop design is proposed that is the cornerstone of a novel scan clocking architecture inspired by the need to reduce instantaneous power during scan.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127725062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Network-on-chip is the new paradigm in core-based system design. Reuse of the on-chip communication network for NoC test is critical to reduce test cost. However, efficient reuse of the communication network for test of legacy cores is challenging. A mismatch between the NoC channel width and the core test wrapper width can adversely affect test efficiency. In addition, stringent power constraints on today's high-density systems exacerbate the test scheduling problem. In this paper, we propose a method for efficiently utilizing the on-chip network for power-aware test scheduling in NoCs. We make use of on-chip clocking to speed up test data transfer by selectively using faster clocks to test certain cores; other cores receive slower clocks to limit test power consumption. A method is presented to determine the clock rate distribution among cores. Experimental results for the ITC '02 benchmarks show that the new method leads to substantial reduction in overall test application time, while satisfying power constraints.
{"title":"Power-aware test scheduling in network-on-chip using variable-rate on-chip clocking","authors":"Chunsheng Liu, V. Iyengar, Jiangfan Shi, É. Cota","doi":"10.1109/VTS.2005.66","DOIUrl":"https://doi.org/10.1109/VTS.2005.66","url":null,"abstract":"Network-on-chip is the new paradigm in core-based system design. Reuse of the on-chip communication network for NoC test is critical to reduce test cost. However, efficient reuse of the communication network for test of legacy cores is challenging. A mismatch between the NoC channel width and the core test wrapper width can adversely affect test efficiency. In addition, stringent power constraints on today's high-density systems exacerbate the test scheduling problem. In this paper, we propose a method for efficiently utilizing the on-chip network for power-aware test scheduling in NoCs. We make use of on-chip clocking to speed up test data transfer by selectively using faster clocks to test certain cores; other cores receive slower clocks to limit test power consumption. A method is presented to determine the clock rate distribution among cores. Experimental results for the ITC '02 benchmarks show that the new method leads to substantial reduction in overall test application time, while satisfying power constraints.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131407341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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