At low frequencies, alternate testing is based on sampling the test response using an A/D converter and analyzing the digitized response in the external tester. In order to use alternate test at frequencies in the multi-GHz range, where the above is not possible, the test waveforms need to be very simple and the evaluation of the test response needs to be handled by on-chip analog test response "feature extractors". In this work, specialized functions of the output response from an alternate test are computed using built-in feature extraction sensors, which measure a complex function of the response waveform and output a DC signature. Different sensor structures are evaluated based on their performance in the presence of environmental effects and process shifts It is seen that very simple sensing circuitry can predict high quality alternate test for RF components.
{"title":"Built-in test of RF components using mapped feature extraction sensors","authors":"S. S. Akbay, A. Chatterjee","doi":"10.1109/VTS.2005.33","DOIUrl":"https://doi.org/10.1109/VTS.2005.33","url":null,"abstract":"At low frequencies, alternate testing is based on sampling the test response using an A/D converter and analyzing the digitized response in the external tester. In order to use alternate test at frequencies in the multi-GHz range, where the above is not possible, the test waveforms need to be very simple and the evaluation of the test response needs to be handled by on-chip analog test response \"feature extractors\". In this work, specialized functions of the output response from an alternate test are computed using built-in feature extraction sensors, which measure a complex function of the response waveform and output a DC signature. Different sensor structures are evaluated based on their performance in the presence of environmental effects and process shifts It is seen that very simple sensing circuitry can predict high quality alternate test for RF components.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"92 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134205351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a methodology for diagnosing arbitrary defects in digital integrated circuits (ICs). Rather than using one or a set of fault models in a cause-effect or effect-cause approach, our methodology derives defect behavior from, the test set, the circuit and its response, and the physical neighbors that surround a potential defect location. The defect locations themselves are identified using a model-independent stage. The methodology enables accurate identification of defect location and behavior through validation via simulation using passing and additional diagnostic test patterns. A byproduct of our methodology is the distinction that can be made among stuck-fault equivalencies which results in improved diagnostic resolution. Several types of shorts and opens are used to demonstrate the applicability of our approach to the diagnosis of arbitrary defects.
{"title":"Diagnosis of arbitrary defects using neighborhood function extraction","authors":"R. Desineni, R. D. Blanton","doi":"10.1109/VTS.2005.41","DOIUrl":"https://doi.org/10.1109/VTS.2005.41","url":null,"abstract":"We present a methodology for diagnosing arbitrary defects in digital integrated circuits (ICs). Rather than using one or a set of fault models in a cause-effect or effect-cause approach, our methodology derives defect behavior from, the test set, the circuit and its response, and the physical neighbors that surround a potential defect location. The defect locations themselves are identified using a model-independent stage. The methodology enables accurate identification of defect location and behavior through validation via simulation using passing and additional diagnostic test patterns. A byproduct of our methodology is the distinction that can be made among stuck-fault equivalencies which results in improved diagnostic resolution. Several types of shorts and opens are used to demonstrate the applicability of our approach to the diagnosis of arbitrary defects.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122527658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
FPGA-based designs are more susceptible to single-event up-sets (SEUs) compared to ASIC designs, since SEUs in configuration bits of FPGAs result in permanent errors in the mapped design. Moreover, the number of sensitive configuration bits is two orders of magnitude more than user bits in typical FPGA-based circuits. In this paper, we present a high-reliable low-cost mitigation technique which can significantly improve the availability of designs mapped into FPGAs. Experimental results show that, using this technique, the availability of an FPGA mapped design can be increases to more than 99%.
{"title":"Soft error mitigation for SRAM-based FPGAs","authors":"H. Asadi, M. Tahoori","doi":"10.1109/VTS.2005.75","DOIUrl":"https://doi.org/10.1109/VTS.2005.75","url":null,"abstract":"FPGA-based designs are more susceptible to single-event up-sets (SEUs) compared to ASIC designs, since SEUs in configuration bits of FPGAs result in permanent errors in the mapped design. Moreover, the number of sensitive configuration bits is two orders of magnitude more than user bits in typical FPGA-based circuits. In this paper, we present a high-reliable low-cost mitigation technique which can significantly improve the availability of designs mapped into FPGAs. Experimental results show that, using this technique, the availability of an FPGA mapped design can be increases to more than 99%.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"700 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124796566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Darren Aaberge, K. Mockler, Dieu Van Dinh, R. Belleau, Tim Donovan, R. Hewlitt
This paper describes an approach to testing the 1 Gbps Parallel RapidIO/spl reg/ interface specifications. The unique test requirements for this bus require the application of new test techniques as well as new ATE capabilities. ATE performance attributes important for parallel source-synchronous buses will be identified and presented with methods to measure these attributes.
{"title":"Meeting the test challenges of the 1 Gbps parallel RapidIO/spl reg/ interface with new automatic test equipment capabilities","authors":"Darren Aaberge, K. Mockler, Dieu Van Dinh, R. Belleau, Tim Donovan, R. Hewlitt","doi":"10.1109/VTS.2005.55","DOIUrl":"https://doi.org/10.1109/VTS.2005.55","url":null,"abstract":"This paper describes an approach to testing the 1 Gbps Parallel RapidIO/spl reg/ interface specifications. The unique test requirements for this bus require the application of new test techniques as well as new ATE capabilities. ATE performance attributes important for parallel source-synchronous buses will be identified and presented with methods to measure these attributes.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123195482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Yeh, Yan-Ting Lai, Yuan-Yuan Shih, Cheng-Wen Wu, Chien-Hung Ho, Yen-Tai Lin
The objective of this paper is to present a cost-effective fault diagnosis methodology for flash memory. Flash memory is enjoying a rapid market growth. The research for flash memory testing is mainly to reduce the test cost and improve the production yield. In this paper, we propose a fault diagnosis flow for flash memory. We also propose a flexible built-in self-diagnosis (BISD) design with enhanced test mode control, which reduces the test time and diagnostic data shift-out cycles by using parallel programming and erasure and employing a parallel shift-out mechanism. The area overhead of our BISD circuit is only about 0.5% for a 256Mb commodity flash memory chip. Experimental results from industrial chips show that the proposed diagnosis methodology has high accuracy in distinguishing the fault type.
{"title":"Flash memory built-in self-diagnosis with test mode control","authors":"J. Yeh, Yan-Ting Lai, Yuan-Yuan Shih, Cheng-Wen Wu, Chien-Hung Ho, Yen-Tai Lin","doi":"10.1109/VTS.2005.45","DOIUrl":"https://doi.org/10.1109/VTS.2005.45","url":null,"abstract":"The objective of this paper is to present a cost-effective fault diagnosis methodology for flash memory. Flash memory is enjoying a rapid market growth. The research for flash memory testing is mainly to reduce the test cost and improve the production yield. In this paper, we propose a fault diagnosis flow for flash memory. We also propose a flexible built-in self-diagnosis (BISD) design with enhanced test mode control, which reduces the test time and diagnostic data shift-out cycles by using parallel programming and erasure and employing a parallel shift-out mechanism. The area overhead of our BISD circuit is only about 0.5% for a 256Mb commodity flash memory chip. Experimental results from industrial chips show that the proposed diagnosis methodology has high accuracy in distinguishing the fault type.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132038900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jing Wang, Xiang Lu, Wangqi Qiu, Ziding Yue, Steve Fancler, Weiping Shi, D. Walker
Excessive power supply noise can lead to overkill during delay test. A static compaction algorithm is described in this paper that prevents such overkill. A power supply noise estimation tool has been built and integrated into the compaction process. Compaction results for KLPG delay tests for ISCAS89 circuits under different power grid environments are presented.
{"title":"Static compaction of delay tests considering power supply noise","authors":"Jing Wang, Xiang Lu, Wangqi Qiu, Ziding Yue, Steve Fancler, Weiping Shi, D. Walker","doi":"10.1109/VTS.2005.77","DOIUrl":"https://doi.org/10.1109/VTS.2005.77","url":null,"abstract":"Excessive power supply noise can lead to overkill during delay test. A static compaction algorithm is described in this paper that prevents such overkill. A power supply noise estimation tool has been built and integrated into the compaction process. Compaction results for KLPG delay tests for ISCAS89 circuits under different power grid environments are presented.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127006145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the rapid growth in the number, the size, and the density of embedded memories in the current generation of microprocessors, developing high coverage memory built-in self-test (MBIST) engines has become increasingly challenging. The MBIST engine should provide high defect coverage and accurate diagnostic capabilities. Furthermore, MBIST engine should be accessible not only at the tester but also at the system. We present our work to develop a MBIST architecture that fulfils all such requirements and supports various flavors of embedded SRAMs. Extensive utilization of the proposed architecture in our products will result in increased productivity by reducing the development time and the verification and productization effort.
{"title":"Highly configurable programmable built-in self test architecture for high-speed memories","authors":"I. Bayraktaroglu, O. Caty, Yickkei Wong","doi":"10.1109/VTS.2005.49","DOIUrl":"https://doi.org/10.1109/VTS.2005.49","url":null,"abstract":"With the rapid growth in the number, the size, and the density of embedded memories in the current generation of microprocessors, developing high coverage memory built-in self-test (MBIST) engines has become increasingly challenging. The MBIST engine should provide high defect coverage and accurate diagnostic capabilities. Furthermore, MBIST engine should be accessible not only at the tester but also at the system. We present our work to develop a MBIST architecture that fulfils all such requirements and supports various flavors of embedded SRAMs. Extensive utilization of the proposed architecture in our products will result in increased productivity by reducing the development time and the verification and productization effort.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121550827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Tutorials & Education Group of the IEEE Computer Society Test Technology Technical Council (TTTC) organizes in 2005 a comprehensive set of Test Technology Tutorials to be held in conjunction with TTTC sponsored technical meetings and included in the annual and expanding Test Technology Educational Program (TTEP). TTEP intends to serve the test and design professionals offering fundamental education and expert knowledge in state-ofthe- art test technology topics. Participation in TTEP-organized tutorials is credited by TTTC. Each full day tutorial corresponds to four TTEP units. Upon completion of each sixteen TTEP units official accreditation in the form of an "IEEE TTTC Test Technology Certificate" will be presented to the participants. In addition to the tutorials, certified university courses and industrial seminars related to test technology can also be included in TTEP and the participation in these credited similar to TTEP tutorials. For information on TTEP 2005 please visit the TTEP web site http://tab.computer.org/tttc/teg/ttep. The test technology tutorials of the VTS 2005 technical program are part of TTEP 2005.
{"title":"Test technology educational program: Overview of tutorials","authors":"","doi":"10.1109/VTS.2005.83","DOIUrl":"https://doi.org/10.1109/VTS.2005.83","url":null,"abstract":"The Tutorials & Education Group of the IEEE Computer Society Test Technology Technical Council (TTTC) organizes in 2005 a comprehensive set of Test Technology Tutorials to be held in conjunction with TTTC sponsored technical meetings and included in the annual and expanding Test Technology Educational Program (TTEP). TTEP intends to serve the test and design professionals offering fundamental education and expert knowledge in state-ofthe- art test technology topics. Participation in TTEP-organized tutorials is credited by TTTC. Each full day tutorial corresponds to four TTEP units. Upon completion of each sixteen TTEP units official accreditation in the form of an \"IEEE TTTC Test Technology Certificate\" will be presented to the participants. In addition to the tutorials, certified university courses and industrial seminars related to test technology can also be included in TTEP and the participation in these credited similar to TTEP tutorials. For information on TTEP 2005 please visit the TTEP web site http://tab.computer.org/tttc/teg/ttep. The test technology tutorials of the VTS 2005 technical program are part of TTEP 2005.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117317940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Hora, S. Eichenberger, B. Benware, B. Madge, A. Majhi, G. Gronthoud
{"title":"VTS 2004 Best Innovative Practices Session Award","authors":"C. Hora, S. Eichenberger, B. Benware, B. Madge, A. Majhi, G. Gronthoud","doi":"10.1109/VTS.2005.89","DOIUrl":"https://doi.org/10.1109/VTS.2005.89","url":null,"abstract":"","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"1145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121735512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"VTS 2004 Best Paper Award","authors":"Nadir Achouri, L. Anghel","doi":"10.1109/VTS.2005.91","DOIUrl":"https://doi.org/10.1109/VTS.2005.91","url":null,"abstract":"","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121399732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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