Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320944
Sam Kavusi, Kunal Ghosh, K. Fife, A. Gamal
A prototype of a new high dynamic range readout scheme targeted for 3D-IC IR focal plane arrays is described. Dynamic range is extended using synchronous self-reset while high SNR is maintained using few non-uniformly spaced captures and least-squares fit to estimate pixel photocurrent. The prototype comprises of a 16times5 readout pixel array fabricated in a 0.18μmum CMOS process and achieves 138dB dynamic range and 60dB peak SNR at 1000 frames/sec with energy consumption of 25.5nJ per pixel readout.
{"title":"A 0.18μm CMOS 1000 frames/sec, 138dB Dynamic Range Readout Circuit for 3D-IC IR Focal Plane Arrays","authors":"Sam Kavusi, Kunal Ghosh, K. Fife, A. Gamal","doi":"10.1109/CICC.2006.320944","DOIUrl":"https://doi.org/10.1109/CICC.2006.320944","url":null,"abstract":"A prototype of a new high dynamic range readout scheme targeted for 3D-IC IR focal plane arrays is described. Dynamic range is extended using synchronous self-reset while high SNR is maintained using few non-uniformly spaced captures and least-squares fit to estimate pixel photocurrent. The prototype comprises of a 16times5 readout pixel array fabricated in a 0.18μmum CMOS process and achieves 138dB dynamic range and 60dB peak SNR at 1000 frames/sec with energy consumption of 25.5nJ per pixel readout.","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132284997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320946
T. Brown, T. Fiez, Mikko Hakkarainen
A simple to apply designer friendly model is proposed that predicts input frequency dependent harmonic distortion (HD) in first order weakly nonlinear sampling circuits. HD due to steady-state tracking errors typically increases at 20 dB per decade versus input frequency. Application of the model has been simplified to the equivalent of frequency-independent nonlinearity analysis. Analytic expressions of HD for a MOS switch are derived. The first known method quantify the tradeoff between thermally limited signal to noise ratio (SNR) and linearity in the form of spurious free dynamic range (SFDR) for sampling circuits is presented. Measured HD2, HD3, HD4, and HD5 versus input frequency of a sample and hold test chip at 19 MSPS fabricated in a 1P5M 0.25mum CMOS process support the conclusions
{"title":"Prediction and Characterization of Frequency Dependent MOS Switch Linearity and the Design Implications","authors":"T. Brown, T. Fiez, Mikko Hakkarainen","doi":"10.1109/CICC.2006.320946","DOIUrl":"https://doi.org/10.1109/CICC.2006.320946","url":null,"abstract":"A simple to apply designer friendly model is proposed that predicts input frequency dependent harmonic distortion (HD) in first order weakly nonlinear sampling circuits. HD due to steady-state tracking errors typically increases at 20 dB per decade versus input frequency. Application of the model has been simplified to the equivalent of frequency-independent nonlinearity analysis. Analytic expressions of HD for a MOS switch are derived. The first known method quantify the tradeoff between thermally limited signal to noise ratio (SNR) and linearity in the form of spurious free dynamic range (SFDR) for sampling circuits is presented. Measured HD2, HD3, HD4, and HD5 versus input frequency of a sample and hold test chip at 19 MSPS fabricated in a 1P5M 0.25mum CMOS process support the conclusions","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115429435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320920
Chun-Jung Chen, Tai-Ning Yang, Jenn-Dong Sun
This paper proposes a new relaxation-based circuit simulation algorithm that is more robust and efficient than traditional methods such as waveform relaxation (WR) and iterated timing analysis (ITA). The new method employs a brand new strategy to simulate: it simulates by performing depth-first search in the signal flow graph of simulated circuits. The new method flexibly schedules subcircuits for calculating according to converging situations of subcircuits, so it can achieve robustness as well as efficiency in dealing with various types of circuits. A circuit simulation program based on the proposed method has been implemented, and various circuits have been tested to justify its performance
{"title":"The Backward-traversing Relaxation Algorithm for Circuit Simulation","authors":"Chun-Jung Chen, Tai-Ning Yang, Jenn-Dong Sun","doi":"10.1109/CICC.2006.320920","DOIUrl":"https://doi.org/10.1109/CICC.2006.320920","url":null,"abstract":"This paper proposes a new relaxation-based circuit simulation algorithm that is more robust and efficient than traditional methods such as waveform relaxation (WR) and iterated timing analysis (ITA). The new method employs a brand new strategy to simulate: it simulates by performing depth-first search in the signal flow graph of simulated circuits. The new method flexibly schedules subcircuits for calculating according to converging situations of subcircuits, so it can achieve robustness as well as efficiency in dealing with various types of circuits. A circuit simulation program based on the proposed method has been implemented, and various circuits have been tested to justify its performance","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115880569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320899
G. Samson, L. Clark
A PLA using NAND and NOR gates for the AND and OR logic planes, respectively, is described. The circuit design, timing and power advantages are described. Nearly 50% power savings over a conventional PLA design is achieved on a 130 nm process at less than 10% delay cost. The new PLA circuit has been fabricated on a 130 nm low standby power process and tested silicon operates at 905 MHz at VDD = 1.5 V
{"title":"A 0.13 μm Low-power Race-free Programmable Logic Array","authors":"G. Samson, L. Clark","doi":"10.1109/CICC.2006.320899","DOIUrl":"https://doi.org/10.1109/CICC.2006.320899","url":null,"abstract":"A PLA using NAND and NOR gates for the AND and OR logic planes, respectively, is described. The circuit design, timing and power advantages are described. Nearly 50% power savings over a conventional PLA design is achieved on a 130 nm process at less than 10% delay cost. The new PLA circuit has been fabricated on a 130 nm low standby power process and tested silicon operates at 905 MHz at VDD = 1.5 V","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114820706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.321004
Mohankumar N. Somasundaram, D. Ma
This paper presents a new integrated switched-capacitor (SC) power converter with an interleaving regulation scheme. By dividing the original power stage into sub-units and operating each sub-unit in an interleaving way, the converter achieves attractive low ripple voltage and transient performance, without compromising other design parameters. The closed-loop operation ensures accurate voltage regulation at any desired levels. The design was fabricated with 0.35 mum CMOS N-well process. The die area including all pads and power transistors is 3.52 mm2. Measurement results show that, with a supply voltage of 1.5 V and a load current of 250 mA, the output of the converter is well regulated at 2.5 V with only 9-mV ripple. The maximum efficiency of 82.3 % is achieved, when the output power reaches 625 mW
{"title":"Low-Ripple CMOS Switched-Capacitor Power Converter With Closed-Loop Interleaving Regulation","authors":"Mohankumar N. Somasundaram, D. Ma","doi":"10.1109/CICC.2006.321004","DOIUrl":"https://doi.org/10.1109/CICC.2006.321004","url":null,"abstract":"This paper presents a new integrated switched-capacitor (SC) power converter with an interleaving regulation scheme. By dividing the original power stage into sub-units and operating each sub-unit in an interleaving way, the converter achieves attractive low ripple voltage and transient performance, without compromising other design parameters. The closed-loop operation ensures accurate voltage regulation at any desired levels. The design was fabricated with 0.35 mum CMOS N-well process. The die area including all pads and power transistors is 3.52 mm2. Measurement results show that, with a supply voltage of 1.5 V and a load current of 250 mA, the output of the converter is well regulated at 2.5 V with only 9-mV ripple. The maximum efficiency of 82.3 % is achieved, when the output power reaches 625 mW","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122047900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320864
Sang-Min Lee, Hyunsik Park, B. Wooley
A per-pixel floating-point, dual-slope A/D converter (ADC) array for a 16 times 16 long wavelength infrared detector array has been integrated in a 0.18-mum CMOS technology. To achieve a high dynamic range and high frame rate simultaneously, an electronic shutter is combined with an ADC for each pixel. A unique method of comparator offset cancellation, employing an integration capacitor with digital calibration, improves the uniformity of the array. The experimental prototype achieves a 19-bit dynamic range and 8-bit resolution at 3 kfps, with a power consumption of only 7 muW/pixel. Each per-pixel ADC occupies 4000 mum2 and is well-suited to 3-dimensional integration
一种用于16 × 16长波红外探测器阵列的单像素浮点双斜率A/D转换器(ADC)阵列集成在0.18 μ m CMOS技术中。为了同时实现高动态范围和高帧率，电子快门与每个像素的ADC相结合。一种独特的比较器偏移抵消方法，采用带有数字校准的积分电容，提高了阵列的均匀性。实验样机在3 kfps下实现了19位动态范围和8位分辨率，功耗仅为7 muW/pixel。每个逐像素ADC占用4000mm2，非常适合三维集成
{"title":"Per-Pixel Floating-Point ADCs with Electronic Shutters for a High Dynamic Range, High Frame Rate Infrared Focal Plane Array","authors":"Sang-Min Lee, Hyunsik Park, B. Wooley","doi":"10.1109/CICC.2006.320864","DOIUrl":"https://doi.org/10.1109/CICC.2006.320864","url":null,"abstract":"A per-pixel floating-point, dual-slope A/D converter (ADC) array for a 16 times 16 long wavelength infrared detector array has been integrated in a 0.18-mum CMOS technology. To achieve a high dynamic range and high frame rate simultaneously, an electronic shutter is combined with an ADC for each pixel. A unique method of comparator offset cancellation, employing an integration capacitor with digital calibration, improves the uniformity of the array. The experimental prototype achieves a 19-bit dynamic range and 8-bit resolution at 3 kfps, with a power consumption of only 7 muW/pixel. Each per-pixel ADC occupies 4000 mum2 and is well-suited to 3-dimensional integration","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125052391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320901
Sizhong Chen, Fei Sun, Tong Zhang
VLSI implementations of nonlinear MIMO signal detectors are not trivial, particularly for systems with high spectral efficiency. For example, realization of such a detector for 4 times 4 MIMO with 64-QAM still remains missing in open literature. To tackle this challenge, we developed a nonlinear soft-output detector design solution, based on which a detector for up to 4 times 4 MIMO with 64-QAM has been designed using 0.13mum CMOS technology. Above 75 Mbps detection throughput has been verified based on post-layout results
{"title":"Nonlinear Soft-Output Signal Detector Design and Implementation for MIMO Communication Systems with High Spectral Efficiency","authors":"Sizhong Chen, Fei Sun, Tong Zhang","doi":"10.1109/CICC.2006.320901","DOIUrl":"https://doi.org/10.1109/CICC.2006.320901","url":null,"abstract":"VLSI implementations of nonlinear MIMO signal detectors are not trivial, particularly for systems with high spectral efficiency. For example, realization of such a detector for 4 times 4 MIMO with 64-QAM still remains missing in open literature. To tackle this challenge, we developed a nonlinear soft-output detector design solution, based on which a detector for up to 4 times 4 MIMO with 64-QAM has been designed using 0.13mum CMOS technology. Above 75 Mbps detection throughput has been verified based on post-layout results","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125651255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.321010
E. Ibe, S. Chung, S. Wen, H. Yamaguchi, Y. Yahagi, H. Kameyama, Shigehisa Yamamoto, T. Akioka
Recent diversity in multicell upset (MCU) of CMOS SRAMs are reviewed and scaling effects are discussed. Space and time domain automatic classification techniques are developed and applied to single event upsets (SEUs) of 130nm SRAM under quasi-mono energetic neutron irradiation at TSL and CYRIC. Tests show very high dependency of MCU features on data patterns, typically "All `0'/`1'" and checkerboard. Three error propagation categories with 41 modes inherent in device architectures are identified. Novel MCU features, in which errors can be corrected by rewriting but Idd increases stepwise depending on MCU multiplicity, are identified. With "All `0'/`1'" pattern, ratio of double bit error is found to be even higher than that of single bit errors. The majority of the double bit error is in nearest neighborhood (NN) position along word line (WL). Underlining basic mechanism can be either charge collection-diffusion or parasitic bipolar actions. But most features can be elucidated only fully by a novel MCU mechanism MCBI (multi-coupled bipolar interaction) proposed by the authors, giving clues for SEU tolerant sub-100nm design
{"title":"Spreading Diversity in Multi-cell Neutron-Induced Upsets with Device Scaling","authors":"E. Ibe, S. Chung, S. Wen, H. Yamaguchi, Y. Yahagi, H. Kameyama, Shigehisa Yamamoto, T. Akioka","doi":"10.1109/CICC.2006.321010","DOIUrl":"https://doi.org/10.1109/CICC.2006.321010","url":null,"abstract":"Recent diversity in multicell upset (MCU) of CMOS SRAMs are reviewed and scaling effects are discussed. Space and time domain automatic classification techniques are developed and applied to single event upsets (SEUs) of 130nm SRAM under quasi-mono energetic neutron irradiation at TSL and CYRIC. Tests show very high dependency of MCU features on data patterns, typically \"All `0'/`1'\" and checkerboard. Three error propagation categories with 41 modes inherent in device architectures are identified. Novel MCU features, in which errors can be corrected by rewriting but Idd increases stepwise depending on MCU multiplicity, are identified. With \"All `0'/`1'\" pattern, ratio of double bit error is found to be even higher than that of single bit errors. The majority of the double bit error is in nearest neighborhood (NN) position along word line (WL). Underlining basic mechanism can be either charge collection-diffusion or parasitic bipolar actions. But most features can be elucidated only fully by a novel MCU mechanism MCBI (multi-coupled bipolar interaction) proposed by the authors, giving clues for SEU tolerant sub-100nm design","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"561 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132490462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.321013
A. Safarian, Lei Zhou, P. Heydari
This paper presents the design and fabrication of a novel silicon-based distributed RF front-end for ultra wideband (UWB) receivers (RX). The proposed UWB distributed RF front-end, called UWB-DRF, is suitable for UWB IF transceiver architectures. The circuit constitutes of combined low-noise amplifier (LNA) and down-conversion mixer cells distributed along the artificial transmission lines (TLs), to achieve wideband conversion gain, noise figure (NF), and linearity. A 3 stage UWB-DRF was fabricated in a 0.13 mum CMOS process. The prototype UWB-DRF achieves 13.8-15.5 dB gain over the entire UWB frequency range, while exhibiting flat NF of 5.2 dB across the band. The radio-frequency (RF), local-oscillator (LO), and intermediate-frequency (IF) ports are wideband-matched to 50Q. A programmable RF termination allows the UWB-DRF to achieve higher gain of 17.7 dB and lower NF of 3.5 dB, while trading off with few decibels of mismatch at the RF input port
本文介绍了一种新型的硅基分布式射频前端的设计和制造，用于超宽带(UWB)接收机(RX)。提出的UWB分布式射频前端，称为UWB- drf，适用于UWB中频收发器架构。该电路由低噪声放大器(LNA)和沿人工传输线(TLs)分布的下变频混频器单元组成，以实现宽带转换增益、噪声系数(NF)和线性度。采用0.13 μ m CMOS工艺制备了3级UWB-DRF。原型UWB- drf在整个UWB频率范围内实现13.8-15.5 dB增益，同时在整个频带内表现出5.2 dB的平坦NF。射频(RF)、本振(LO)和中频(IF)端口的带宽匹配为50Q。可编程射频终端允许UWB-DRF实现17.7 dB的高增益和3.5 dB的低NF，同时在射频输入端口上进行少量分贝的失配
{"title":"A Distributed RF Front-End for UWB Receivers","authors":"A. Safarian, Lei Zhou, P. Heydari","doi":"10.1109/CICC.2006.321013","DOIUrl":"https://doi.org/10.1109/CICC.2006.321013","url":null,"abstract":"This paper presents the design and fabrication of a novel silicon-based distributed RF front-end for ultra wideband (UWB) receivers (RX). The proposed UWB distributed RF front-end, called UWB-DRF, is suitable for UWB IF transceiver architectures. The circuit constitutes of combined low-noise amplifier (LNA) and down-conversion mixer cells distributed along the artificial transmission lines (TLs), to achieve wideband conversion gain, noise figure (NF), and linearity. A 3 stage UWB-DRF was fabricated in a 0.13 mum CMOS process. The prototype UWB-DRF achieves 13.8-15.5 dB gain over the entire UWB frequency range, while exhibiting flat NF of 5.2 dB across the band. The radio-frequency (RF), local-oscillator (LO), and intermediate-frequency (IF) ports are wideband-matched to 50Q. A programmable RF termination allows the UWB-DRF to achieve higher gain of 17.7 dB and lower NF of 3.5 dB, while trading off with few decibels of mismatch at the RF input port","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132028582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320989
A. Leon, B. Langley, Jinuk Luke Shin
Throughput computing represents a new paradigm in processor design focusing on maximizing overall throughput of commercial workloads while addressing increasing demands for improved power, cooling and reliability in today's datacenters. The first generation of "Niagara" SPARC processors implements a power-efficient chip multithreading (CMT) architecture to deliver high performance and reliability in a low power and thermal envelope. The UltraSPARC T1 processor combines eight 4-threaded 64b cores, a high bandwidth interconnect crossbar, a shared 3MB L2 cache and four double-width DDR2 DRAM interfaces. Implemented in 90nm CMOS technology, the 378mm2 die consumes only 63W at 1.2GHz. Beyond the ability of CMT to optimize throughput performance, this paper highlights the advantages of CMT in the areas of power and thermal control, reliability, RAS, and design robustness, describing key features of the design relevant to each of these topics
{"title":"The UltraSPARC T1 Processor: CMT Reliability","authors":"A. Leon, B. Langley, Jinuk Luke Shin","doi":"10.1109/CICC.2006.320989","DOIUrl":"https://doi.org/10.1109/CICC.2006.320989","url":null,"abstract":"Throughput computing represents a new paradigm in processor design focusing on maximizing overall throughput of commercial workloads while addressing increasing demands for improved power, cooling and reliability in today's datacenters. The first generation of \"Niagara\" SPARC processors implements a power-efficient chip multithreading (CMT) architecture to deliver high performance and reliability in a low power and thermal envelope. The UltraSPARC T1 processor combines eight 4-threaded 64b cores, a high bandwidth interconnect crossbar, a shared 3MB L2 cache and four double-width DDR2 DRAM interfaces. Implemented in 90nm CMOS technology, the 378mm2 die consumes only 63W at 1.2GHz. Beyond the ability of CMT to optimize throughput performance, this paper highlights the advantages of CMT in the areas of power and thermal control, reliability, RAS, and design robustness, describing key features of the design relevant to each of these topics","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125485917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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