Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320930
Y. Ogasahara, Takashi Enami, M. Hashimoto, Takashi Sato, T. Onoye
Power integrity is an crucial design issue in nanometer technologies because of lowered supply voltage and current increase. This paper focuses on gate delay variation due to power/ground noise, and demonstrates measurement results in a 90nm technology. For full-chip simulation, a current model with capacitance and variable resistor is developed to accurately model current dependency on voltage drop. Measurement results are well correlated with simulation, and verify that gate delay depends on average voltage drop
{"title":"Measurement results of delay degradation due to power supply noise well correlated with full-chip simulation","authors":"Y. Ogasahara, Takashi Enami, M. Hashimoto, Takashi Sato, T. Onoye","doi":"10.1109/CICC.2006.320930","DOIUrl":"https://doi.org/10.1109/CICC.2006.320930","url":null,"abstract":"Power integrity is an crucial design issue in nanometer technologies because of lowered supply voltage and current increase. This paper focuses on gate delay variation due to power/ground noise, and demonstrates measurement results in a 90nm technology. For full-chip simulation, a current model with capacitance and variable resistor is developed to accurately model current dependency on voltage drop. Measurement results are well correlated with simulation, and verify that gate delay depends on average voltage drop","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132059252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.321003
Jim Le, Christopher Hanken, Martin Held, M. Hagedorn, K. Mayaram, T. Fiez
A pseudo-random number generator implemented in asynchronous logic generates one-fifth the RMS substrate noise compared to the equivalent design in synchronous logic. An asynchronous 8051 processor generates one-third the RMS substrate noise as the equivalent synchronous design. The SNR of a second order delta-sigma modulator (DSM) is not affected by substrate noise due to an asynchronous processor while it experiences 15 dB degradation when the synchronous 8051 processor is clocked near integer multiples of the DSM sampling frequency
在异步逻辑中实现的伪随机数发生器产生的RMS基板噪声与同步逻辑中的等效设计相比减少了五分之一。异步8051处理器产生的RMS基板噪声是等效同步设计的三分之一。二阶δ - σ调制器(DSM)的信噪比不受异步处理器引起的衬底噪声的影响，而当同步8051处理器的时钟接近DSM采样频率的整数倍时，其信噪比会下降15 dB
{"title":"Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry","authors":"Jim Le, Christopher Hanken, Martin Held, M. Hagedorn, K. Mayaram, T. Fiez","doi":"10.1109/CICC.2006.321003","DOIUrl":"https://doi.org/10.1109/CICC.2006.321003","url":null,"abstract":"A pseudo-random number generator implemented in asynchronous logic generates one-fifth the RMS substrate noise compared to the equivalent design in synchronous logic. An asynchronous 8051 processor generates one-third the RMS substrate noise as the equivalent synchronous design. The SNR of a second order delta-sigma modulator (DSM) is not affected by substrate noise due to an asynchronous processor while it experiences 15 dB degradation when the synchronous 8051 processor is clocked near integer multiples of the DSM sampling frequency","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124311809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.321002
K. Venkataraman, V. Suresh, S. Iyengar, M. Ott, S. R. Kalari, J. Zhi, E. Ruetz, M. Gray, B. Reynov, A. Iqbal
The advent of broadband services requires multi service provisioning platforms (MSPP) to achieve >10Gbps capacity with 1-4 rack unit footprint, power <200W and cost <$10K. Highly integrated SoC using 0.13mu CMOS 19.3times19.3mm die packaged in a 1517 FCBGA affords a unique MSPP solution consisting of 155M-10Gbps SONET/SDH framing, low/high order path processing, grooming, cross-connection up to 22.5Gbps and an embedded processor. A rigorous methodology enabled a production-worthy SoC comprising 9Mgates/14Mbit memory
{"title":"Integrated 155M-10Gbps Framer with 22.5Gbps Low/High Order Cross Connect SoC","authors":"K. Venkataraman, V. Suresh, S. Iyengar, M. Ott, S. R. Kalari, J. Zhi, E. Ruetz, M. Gray, B. Reynov, A. Iqbal","doi":"10.1109/CICC.2006.321002","DOIUrl":"https://doi.org/10.1109/CICC.2006.321002","url":null,"abstract":"The advent of broadband services requires multi service provisioning platforms (MSPP) to achieve >10Gbps capacity with 1-4 rack unit footprint, power <200W and cost <$10K. Highly integrated SoC using 0.13mu CMOS 19.3times19.3mm die packaged in a 1517 FCBGA affords a unique MSPP solution consisting of 155M-10Gbps SONET/SDH framing, low/high order path processing, grooming, cross-connection up to 22.5Gbps and an embedded processor. A rigorous methodology enabled a production-worthy SoC comprising 9Mgates/14Mbit memory","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133810815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.321014
Mohamed Bouhamame, J. Tourret, Luca Lo Coco, S. Toutain, O. Pasquier
A controllable high voltage DC/DC converter has been designed that can generate an output voltage from 0 to 30V with a 2.8V supply voltage. It is suitable for controlling MEMS and high voltage varicap devices in tunable filters. The proposed DC/DC converter uses a novel approach to decrease the output voltage by cascading two Dickson charge pumps (Dickson, 1976). It is operating with a clock frequency of 16MHz and is built in a 0.25mum Bi-CMOS technology
设计了一种可控高压DC/DC变换器，该变换器在2.8V的供电电压下可产生0 ~ 30V的输出电压。它适用于可调谐滤波器中对MEMS和高压可变电容器件的控制。所提出的DC/DC变换器采用了一种新颖的方法，通过级联两个Dickson电荷泵来降低输出电压(Dickson, 1976)。它的时钟频率为16MHz，采用0.25 μ m Bi-CMOS技术
{"title":"A Fully Integrated DC/DC Converter for Tunable RF Filters","authors":"Mohamed Bouhamame, J. Tourret, Luca Lo Coco, S. Toutain, O. Pasquier","doi":"10.1109/CICC.2006.321014","DOIUrl":"https://doi.org/10.1109/CICC.2006.321014","url":null,"abstract":"A controllable high voltage DC/DC converter has been designed that can generate an output voltage from 0 to 30V with a 2.8V supply voltage. It is suitable for controlling MEMS and high voltage varicap devices in tunable filters. The proposed DC/DC converter uses a novel approach to decrease the output voltage by cascading two Dickson charge pumps (Dickson, 1976). It is operating with a clock frequency of 16MHz and is built in a 0.25mum Bi-CMOS technology","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133909895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320894
S. Kawahito
In this paper, low-power design techniques of highspeed A/D converters are reviewed and discussed. Pipeline and parallel-pipeline architectures are treated as these are dominant architectures when required high sampling rate and high resolution with reasonable power dissipation. A power optimization of pipeline and parallel pipeline ADCs based on models of noise analysis and response time of a building block in the multiple-stage pipeline ADC is also presented. Finally, the theoretical minimum of required power in pipeline ADCs is discussed
{"title":"Low-Power Design of Pipeline A/D Converters","authors":"S. Kawahito","doi":"10.1109/CICC.2006.320894","DOIUrl":"https://doi.org/10.1109/CICC.2006.320894","url":null,"abstract":"In this paper, low-power design techniques of highspeed A/D converters are reviewed and discussed. Pipeline and parallel-pipeline architectures are treated as these are dominant architectures when required high sampling rate and high resolution with reasonable power dissipation. A power optimization of pipeline and parallel pipeline ADCs based on models of noise analysis and response time of a building block in the multiple-stage pipeline ADC is also presented. Finally, the theoretical minimum of required power in pipeline ADCs is discussed","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123860691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320867
Erhan Ozalevli, H. Dinç, H. Lo, P. Hasler
We present an implementation of a 4-bit binary-weighted-resistor DAC to be used in quantizers. It is built by using tunable floating-gate CMOS resistors, which exploit the capacitive coupling and voltage storage capabilities of floating-gate transistors and employ scaled-gate linearization technique to suppress the MOSFET nonlinearities. The resistance of these resistors drifts 1.6 middot 10-3% over the period of 10 years at 25degC. By using these resistors, 15-bit accurate DAC is implemented in 0.5mum CMOS process
我们提出了一个用于量化器的4位二进制加权电阻DAC的实现。该电路采用可调浮栅CMOS电阻器，利用浮栅晶体管的电容耦合和电压存储能力，采用标度栅线性化技术抑制MOSFET的非线性。在25℃下，这些电阻的电阻在10年内漂移1.6中点10-3%。通过使用这些电阻，在0.5 μ m CMOS工艺中实现了15位精确的DAC
{"title":"Design of a binary-weighted resistor DAC using tunable linearized floating-gate CMOS resistors","authors":"Erhan Ozalevli, H. Dinç, H. Lo, P. Hasler","doi":"10.1109/CICC.2006.320867","DOIUrl":"https://doi.org/10.1109/CICC.2006.320867","url":null,"abstract":"We present an implementation of a 4-bit binary-weighted-resistor DAC to be used in quantizers. It is built by using tunable floating-gate CMOS resistors, which exploit the capacitive coupling and voltage storage capabilities of floating-gate transistors and employ scaled-gate linearization technique to suppress the MOSFET nonlinearities. The resistance of these resistors drifts 1.6 middot 10-3% over the period of 10 years at 25degC. By using these resistors, 15-bit accurate DAC is implemented in 0.5mum CMOS process","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123921752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320998
R. Staszewski, K. Muhammad, D. Leipold
RF circuits for multi-GHz frequencies have recently migrated to low-cost digital deep-submicron CMOS processes. Unfortunately, this process environment, which is optimized only for digital logic and SRAM memory, is extremely unfriendly for conventional analog and RF designs. We present fundamental techniques recently developed that transform the RF and analog circuit design complexity to digital domain for a wireless RF transceiver, so that it enjoys the benefits of digital approach, such as process node scaling and design automation. All-digital phase locked loop, all-digital control of phase and amplitude of a polar transmitter, and direct RF sampling techniques allow great flexibility in reconfigurable radio design. Digital signal processing concepts are used to help relieve analog design complexity, allowing one to reduce cost and power consumption in a reconfigurable design environment. VHDL hardware description language is universally used throughout this SoC. The ideas presented have been used in Texas Instruments to develop two generations of commercial digital RF processors: a single-chip Bluetooth radio and a single-chip GSM radio
{"title":"Digital RF Processor Techniques for Single-Chip Radios","authors":"R. Staszewski, K. Muhammad, D. Leipold","doi":"10.1109/CICC.2006.320998","DOIUrl":"https://doi.org/10.1109/CICC.2006.320998","url":null,"abstract":"RF circuits for multi-GHz frequencies have recently migrated to low-cost digital deep-submicron CMOS processes. Unfortunately, this process environment, which is optimized only for digital logic and SRAM memory, is extremely unfriendly for conventional analog and RF designs. We present fundamental techniques recently developed that transform the RF and analog circuit design complexity to digital domain for a wireless RF transceiver, so that it enjoys the benefits of digital approach, such as process node scaling and design automation. All-digital phase locked loop, all-digital control of phase and amplitude of a polar transmitter, and direct RF sampling techniques allow great flexibility in reconfigurable radio design. Digital signal processing concepts are used to help relieve analog design complexity, allowing one to reduce cost and power consumption in a reconfigurable design environment. VHDL hardware description language is universally used throughout this SoC. The ideas presented have been used in Texas Instruments to develop two generations of commercial digital RF processors: a single-chip Bluetooth radio and a single-chip GSM radio","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127726451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320839
B. Agrawal, Frank Liu, S. Nassif
Most robust circuit sizing and optimization algorithms require detailed information about the sensitivity of circuit performance to device behavior. Additionally, rapid technology scaling and the introduction of novel device structures to extend CMOS scaling is resulting in the rapid introduction of new models into our simulation infrastructure. This paper presents a novel technique for the efficient computation of circuit performance sensitivity in a model independent manner. The advantage of the method is that it allows rapid deployment of accurate optimization methods even for new or exploratory models. The use of these gradients was demonstrated in circuit optimization to generate an area vs. timing variability trade-off curve for an SRAM cell design in the presence of N and P device threshold voltage variations
{"title":"Circuit Optimization Using Scale Based Sensitivities","authors":"B. Agrawal, Frank Liu, S. Nassif","doi":"10.1109/CICC.2006.320839","DOIUrl":"https://doi.org/10.1109/CICC.2006.320839","url":null,"abstract":"Most robust circuit sizing and optimization algorithms require detailed information about the sensitivity of circuit performance to device behavior. Additionally, rapid technology scaling and the introduction of novel device structures to extend CMOS scaling is resulting in the rapid introduction of new models into our simulation infrastructure. This paper presents a novel technique for the efficient computation of circuit performance sensitivity in a model independent manner. The advantage of the method is that it allows rapid deployment of accurate optimization methods even for new or exploratory models. The use of these gradients was demonstrated in circuit optimization to generate an area vs. timing variability trade-off curve for an SRAM cell design in the presence of N and P device threshold voltage variations","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"254 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121164634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320854
A. Howard, Gu-Yeon Wei, W. Dally, P. Horowitz
PulseNet is a full-custom IC with parallel flash ADC and digital processing that enables an all-sky optical search for extraterrestrial intelligence. It integrates 448 sense amplifiers that digitize 32 analog signals at 1GS/s, and other circuits that filter samples, store candidate signals, and perform astronomical observations. Its ~250,000 CMOS transistors (TSMC 0.25μm) dissipate 1.1W at 400MHz and 2.5V.
{"title":"Pulsenet - A Parallel Flash Sampler and Digital Processor IC for Optical SETI","authors":"A. Howard, Gu-Yeon Wei, W. Dally, P. Horowitz","doi":"10.1109/CICC.2006.320854","DOIUrl":"https://doi.org/10.1109/CICC.2006.320854","url":null,"abstract":"PulseNet is a full-custom IC with parallel flash ADC and digital processing that enables an all-sky optical search for extraterrestrial intelligence. It integrates 448 sense amplifiers that digitize 32 analog signals at 1GS/s, and other circuits that filter samples, store candidate signals, and perform astronomical observations. Its ~250,000 CMOS transistors (TSMC 0.25μm) dissipate 1.1W at 400MHz and 2.5V.","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128438950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320990
Takashi Sato, Yu Matsumoto, K. Hirakimoto, M. Komoda, J. Mano
A time-slicing ring oscillator (TSRO) which captures dynamic delay degradation due to instantaneous voltage drop on a power supply network is proposed. Voltage drop impact on delay is directly measured and time-domain effective voltage drop waveforms is also obtained. The TSRO consists of standard logic cells only hence fits almost anywhere in logic circuits for in-situ measurements. Measurement results of a test chip using 90-nm process successfully proved its concept
{"title":"A Time-Slicing Ring Oscillator for Capturing Instantaneous Delay Degradation and Power Supply Voltage Drop","authors":"Takashi Sato, Yu Matsumoto, K. Hirakimoto, M. Komoda, J. Mano","doi":"10.1109/CICC.2006.320990","DOIUrl":"https://doi.org/10.1109/CICC.2006.320990","url":null,"abstract":"A time-slicing ring oscillator (TSRO) which captures dynamic delay degradation due to instantaneous voltage drop on a power supply network is proposed. Voltage drop impact on delay is directly measured and time-domain effective voltage drop waveforms is also obtained. The TSRO consists of standard logic cells only hence fits almost anywhere in logic circuits for in-situ measurements. Measurement results of a test chip using 90-nm process successfully proved its concept","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115894501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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