Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320898
A. Scholten, R. V. Langevelde, L. Tiemeijer, D. Klaassen
The physical background of the thermal noise equations of the PSP MOSFET model is presented. The PSP thermal noise model is shown to pass a number of proposed benchmark tests for MOSFET thermal noise. Without any fitting parameters, it is shown to predict with great accuracy a collection of experimental data on three modern CMOS technologies. The impact of device layout on noise properties is discussed and demonstrated experimentally
{"title":"Compact modeling of noise in CMOS","authors":"A. Scholten, R. V. Langevelde, L. Tiemeijer, D. Klaassen","doi":"10.1109/CICC.2006.320898","DOIUrl":"https://doi.org/10.1109/CICC.2006.320898","url":null,"abstract":"The physical background of the thermal noise equations of the PSP MOSFET model is presented. The PSP thermal noise model is shown to pass a number of proposed benchmark tests for MOSFET thermal noise. Without any fitting parameters, it is shown to predict with great accuracy a collection of experimental data on three modern CMOS technologies. The impact of device layout on noise properties is discussed and demonstrated experimentally","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127297087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320985
R. Yuen, Marcus van Ierssel, A. Sheikholeslami, W. Walker, H. Tamura
We present a 5Gb/s transmitter that cancels the reflected signals from any impedance discontinuity located at up to 64UI away from the transmitter and spread over 8UI interval. Measured results from our 0.11mum CMOS design reveal a 150mV eye-opening, from a nearly closed eye, when reflection cancellation is activated. The design consumes 510muA for the PLL operation, 60mA for data generation, and 50mA for data transmission, all from a 1.2V supply
我们提出了一种5Gb/s的发射机，可以消除距离发射机64UI处任何阻抗不连续的反射信号，并在8UI间隔内传播。我们的0.11 mm CMOS设计的测量结果显示，当反射抵消被激活时，几乎闭着的眼睛会产生150mV的睁大。该设计用于锁相环工作的功耗为510muA，数据生成功耗为60mA，数据传输功耗为50mA，全部来自1.2V电源
{"title":"A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers","authors":"R. Yuen, Marcus van Ierssel, A. Sheikholeslami, W. Walker, H. Tamura","doi":"10.1109/CICC.2006.320985","DOIUrl":"https://doi.org/10.1109/CICC.2006.320985","url":null,"abstract":"We present a 5Gb/s transmitter that cancels the reflected signals from any impedance discontinuity located at up to 64UI away from the transmitter and spread over 8UI interval. Measured results from our 0.11mum CMOS design reveal a 150mV eye-opening, from a nearly closed eye, when reflection cancellation is activated. The design consumes 510muA for the PLL operation, 60mA for data generation, and 50mA for data transmission, all from a 1.2V supply","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"31 40","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113941301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.321011
A. Maxim, R. Poorfard, R. Johnson, P. Crawley, J. Kao, Z. Dong, M. Chennam, T. Nutt, D. Trager
A digital low-IF fully-integrated dual tuner for DVB-S2 satellite TV applications was realized in 0.11μm CMOS. It provides baseband digital I/Q outputs for a demodulator-on-host back-end processor. A wide bandwidth ring oscillator based frequency synthesizer having a large frequency step was used to down-convert a cluster of channels to a sliding low-IF frequency, while the second down-conversion to baseband was performed in the digital domain. The low-IF architecture allows a discrete AGC loop, while avoiding 1/f noise and DC offset issues. Eliminating the VCO tank inductors minimizes frequency pulling and parasitic coupling to front-end LNA, allowing the integration of a large digital core on the same die with the sensitive RF front-end.
{"title":"A Fully-Integrated 0.11μm CMOS Digital Low-IF DVB-S2 Satellite TV Dual Tuner SOC","authors":"A. Maxim, R. Poorfard, R. Johnson, P. Crawley, J. Kao, Z. Dong, M. Chennam, T. Nutt, D. Trager","doi":"10.1109/CICC.2006.321011","DOIUrl":"https://doi.org/10.1109/CICC.2006.321011","url":null,"abstract":"A digital low-IF fully-integrated dual tuner for DVB-S2 satellite TV applications was realized in 0.11μm CMOS. It provides baseband digital I/Q outputs for a demodulator-on-host back-end processor. A wide bandwidth ring oscillator based frequency synthesizer having a large frequency step was used to down-convert a cluster of channels to a sliding low-IF frequency, while the second down-conversion to baseband was performed in the digital domain. The low-IF architecture allows a discrete AGC loop, while avoiding 1/f noise and DC offset issues. Eliminating the VCO tank inductors minimizes frequency pulling and parasitic coupling to front-end LNA, allowing the integration of a large digital core on the same die with the sensitive RF front-end.","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122707479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320891
S. Shahramian, S. Voinigescu, A. C. Carusone
A 30-GS/sec CMOS track and hold amplifier (THA) is designed and fabricated in a 0.13-μm technology. The chip operates from a 1.8-V supply and consumes 270 mW. The THA employs a low noise TIA input stage and a switched source follower (SSF) track and hold block. The SSF topology overcomes the shortcomings of switched series transistors by eliminating the use of a series switch all together. The measured single-ended S-parameters show an input and output return loss of better than -10 dB up to 35 GHz and 7 GHz of bandwidth when the circuit is operated in track mode. The measured total harmonic distortion of the THA is better than -29 dB.
{"title":"A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology","authors":"S. Shahramian, S. Voinigescu, A. C. Carusone","doi":"10.1109/CICC.2006.320891","DOIUrl":"https://doi.org/10.1109/CICC.2006.320891","url":null,"abstract":"A 30-GS/sec CMOS track and hold amplifier (THA) is designed and fabricated in a 0.13-μm technology. The chip operates from a 1.8-V supply and consumes 270 mW. The THA employs a low noise TIA input stage and a switched source follower (SSF) track and hold block. The SSF topology overcomes the shortcomings of switched series transistors by eliminating the use of a series switch all together. The measured single-ended S-parameters show an input and output return loss of better than -10 dB up to 35 GHz and 7 GHz of bandwidth when the circuit is operated in track mode. The measured total harmonic distortion of the THA is better than -29 dB.","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131322900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320894
S. Kawahito
In this paper, low-power design techniques of highspeed A/D converters are reviewed and discussed. Pipeline and parallel-pipeline architectures are treated as these are dominant architectures when required high sampling rate and high resolution with reasonable power dissipation. A power optimization of pipeline and parallel pipeline ADCs based on models of noise analysis and response time of a building block in the multiple-stage pipeline ADC is also presented. Finally, the theoretical minimum of required power in pipeline ADCs is discussed
{"title":"Low-Power Design of Pipeline A/D Converters","authors":"S. Kawahito","doi":"10.1109/CICC.2006.320894","DOIUrl":"https://doi.org/10.1109/CICC.2006.320894","url":null,"abstract":"In this paper, low-power design techniques of highspeed A/D converters are reviewed and discussed. Pipeline and parallel-pipeline architectures are treated as these are dominant architectures when required high sampling rate and high resolution with reasonable power dissipation. A power optimization of pipeline and parallel pipeline ADCs based on models of noise analysis and response time of a building block in the multiple-stage pipeline ADC is also presented. Finally, the theoretical minimum of required power in pipeline ADCs is discussed","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123860691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320867
Erhan Ozalevli, H. Dinç, H. Lo, P. Hasler
We present an implementation of a 4-bit binary-weighted-resistor DAC to be used in quantizers. It is built by using tunable floating-gate CMOS resistors, which exploit the capacitive coupling and voltage storage capabilities of floating-gate transistors and employ scaled-gate linearization technique to suppress the MOSFET nonlinearities. The resistance of these resistors drifts 1.6 middot 10-3% over the period of 10 years at 25degC. By using these resistors, 15-bit accurate DAC is implemented in 0.5mum CMOS process
我们提出了一个用于量化器的4位二进制加权电阻DAC的实现。该电路采用可调浮栅CMOS电阻器，利用浮栅晶体管的电容耦合和电压存储能力，采用标度栅线性化技术抑制MOSFET的非线性。在25℃下，这些电阻的电阻在10年内漂移1.6中点10-3%。通过使用这些电阻，在0.5 μ m CMOS工艺中实现了15位精确的DAC
{"title":"Design of a binary-weighted resistor DAC using tunable linearized floating-gate CMOS resistors","authors":"Erhan Ozalevli, H. Dinç, H. Lo, P. Hasler","doi":"10.1109/CICC.2006.320867","DOIUrl":"https://doi.org/10.1109/CICC.2006.320867","url":null,"abstract":"We present an implementation of a 4-bit binary-weighted-resistor DAC to be used in quantizers. It is built by using tunable floating-gate CMOS resistors, which exploit the capacitive coupling and voltage storage capabilities of floating-gate transistors and employ scaled-gate linearization technique to suppress the MOSFET nonlinearities. The resistance of these resistors drifts 1.6 middot 10-3% over the period of 10 years at 25degC. By using these resistors, 15-bit accurate DAC is implemented in 0.5mum CMOS process","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123921752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320998
R. Staszewski, K. Muhammad, D. Leipold
RF circuits for multi-GHz frequencies have recently migrated to low-cost digital deep-submicron CMOS processes. Unfortunately, this process environment, which is optimized only for digital logic and SRAM memory, is extremely unfriendly for conventional analog and RF designs. We present fundamental techniques recently developed that transform the RF and analog circuit design complexity to digital domain for a wireless RF transceiver, so that it enjoys the benefits of digital approach, such as process node scaling and design automation. All-digital phase locked loop, all-digital control of phase and amplitude of a polar transmitter, and direct RF sampling techniques allow great flexibility in reconfigurable radio design. Digital signal processing concepts are used to help relieve analog design complexity, allowing one to reduce cost and power consumption in a reconfigurable design environment. VHDL hardware description language is universally used throughout this SoC. The ideas presented have been used in Texas Instruments to develop two generations of commercial digital RF processors: a single-chip Bluetooth radio and a single-chip GSM radio
{"title":"Digital RF Processor Techniques for Single-Chip Radios","authors":"R. Staszewski, K. Muhammad, D. Leipold","doi":"10.1109/CICC.2006.320998","DOIUrl":"https://doi.org/10.1109/CICC.2006.320998","url":null,"abstract":"RF circuits for multi-GHz frequencies have recently migrated to low-cost digital deep-submicron CMOS processes. Unfortunately, this process environment, which is optimized only for digital logic and SRAM memory, is extremely unfriendly for conventional analog and RF designs. We present fundamental techniques recently developed that transform the RF and analog circuit design complexity to digital domain for a wireless RF transceiver, so that it enjoys the benefits of digital approach, such as process node scaling and design automation. All-digital phase locked loop, all-digital control of phase and amplitude of a polar transmitter, and direct RF sampling techniques allow great flexibility in reconfigurable radio design. Digital signal processing concepts are used to help relieve analog design complexity, allowing one to reduce cost and power consumption in a reconfigurable design environment. VHDL hardware description language is universally used throughout this SoC. The ideas presented have been used in Texas Instruments to develop two generations of commercial digital RF processors: a single-chip Bluetooth radio and a single-chip GSM radio","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127726451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320839
B. Agrawal, Frank Liu, S. Nassif
Most robust circuit sizing and optimization algorithms require detailed information about the sensitivity of circuit performance to device behavior. Additionally, rapid technology scaling and the introduction of novel device structures to extend CMOS scaling is resulting in the rapid introduction of new models into our simulation infrastructure. This paper presents a novel technique for the efficient computation of circuit performance sensitivity in a model independent manner. The advantage of the method is that it allows rapid deployment of accurate optimization methods even for new or exploratory models. The use of these gradients was demonstrated in circuit optimization to generate an area vs. timing variability trade-off curve for an SRAM cell design in the presence of N and P device threshold voltage variations
{"title":"Circuit Optimization Using Scale Based Sensitivities","authors":"B. Agrawal, Frank Liu, S. Nassif","doi":"10.1109/CICC.2006.320839","DOIUrl":"https://doi.org/10.1109/CICC.2006.320839","url":null,"abstract":"Most robust circuit sizing and optimization algorithms require detailed information about the sensitivity of circuit performance to device behavior. Additionally, rapid technology scaling and the introduction of novel device structures to extend CMOS scaling is resulting in the rapid introduction of new models into our simulation infrastructure. This paper presents a novel technique for the efficient computation of circuit performance sensitivity in a model independent manner. The advantage of the method is that it allows rapid deployment of accurate optimization methods even for new or exploratory models. The use of these gradients was demonstrated in circuit optimization to generate an area vs. timing variability trade-off curve for an SRAM cell design in the presence of N and P device threshold voltage variations","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"254 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121164634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320854
A. Howard, Gu-Yeon Wei, W. Dally, P. Horowitz
PulseNet is a full-custom IC with parallel flash ADC and digital processing that enables an all-sky optical search for extraterrestrial intelligence. It integrates 448 sense amplifiers that digitize 32 analog signals at 1GS/s, and other circuits that filter samples, store candidate signals, and perform astronomical observations. Its ~250,000 CMOS transistors (TSMC 0.25μm) dissipate 1.1W at 400MHz and 2.5V.
{"title":"Pulsenet - A Parallel Flash Sampler and Digital Processor IC for Optical SETI","authors":"A. Howard, Gu-Yeon Wei, W. Dally, P. Horowitz","doi":"10.1109/CICC.2006.320854","DOIUrl":"https://doi.org/10.1109/CICC.2006.320854","url":null,"abstract":"PulseNet is a full-custom IC with parallel flash ADC and digital processing that enables an all-sky optical search for extraterrestrial intelligence. It integrates 448 sense amplifiers that digitize 32 analog signals at 1GS/s, and other circuits that filter samples, store candidate signals, and perform astronomical observations. Its ~250,000 CMOS transistors (TSMC 0.25μm) dissipate 1.1W at 400MHz and 2.5V.","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128438950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320990
Takashi Sato, Yu Matsumoto, K. Hirakimoto, M. Komoda, J. Mano
A time-slicing ring oscillator (TSRO) which captures dynamic delay degradation due to instantaneous voltage drop on a power supply network is proposed. Voltage drop impact on delay is directly measured and time-domain effective voltage drop waveforms is also obtained. The TSRO consists of standard logic cells only hence fits almost anywhere in logic circuits for in-situ measurements. Measurement results of a test chip using 90-nm process successfully proved its concept
{"title":"A Time-Slicing Ring Oscillator for Capturing Instantaneous Delay Degradation and Power Supply Voltage Drop","authors":"Takashi Sato, Yu Matsumoto, K. Hirakimoto, M. Komoda, J. Mano","doi":"10.1109/CICC.2006.320990","DOIUrl":"https://doi.org/10.1109/CICC.2006.320990","url":null,"abstract":"A time-slicing ring oscillator (TSRO) which captures dynamic delay degradation due to instantaneous voltage drop on a power supply network is proposed. Voltage drop impact on delay is directly measured and time-domain effective voltage drop waveforms is also obtained. The TSRO consists of standard logic cells only hence fits almost anywhere in logic circuits for in-situ measurements. Measurement results of a test chip using 90-nm process successfully proved its concept","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115894501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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