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IEEE Custom Integrated Circuits Conference 2006最新文献

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Electrical Characteristic Fluctuations in Sub-45nm CMOS Devices 45纳米以下CMOS器件的电特性波动
Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320881
Fu-Liang Yang, Jiunn-Ren Hwang, Yiming Li
Random fluctuations of electrical characteristics in sub-45nm CMOS devices introduced by process-parameter variations through severe short channel effects have made the scaling of conventional planar transistors much more difficult than ever before, especially while further reduction of gate dielectric thickness is ambiguous. In this paper, the authors systematically investigate the fluctuations of threshold voltages at varied gate length, considering the effects of channel doping, gate dielectric thickness, and new transistor structures such as thin-buried-oxide SOI and FinFETs. Quantitative analysis is undertaken in terms of three major variation sources: random doping distribution, gate length deviation, and line edge roughness. The analysis also features a low Vt-fluctuation transistor for 16nm node achieved with undoped body, mid-gap metal gate, and nanowire channel
在45纳米以下的CMOS器件中,由于严重的短沟道效应引起的工艺参数变化导致电特性的随机波动,使得传统平面晶体管的缩放比以往更加困难,特别是在栅极介电厚度进一步减小的情况下。在本文中,作者系统地研究了不同栅极长度下阈值电压的波动,考虑了通道掺杂、栅极介电厚度和新型晶体管结构(如薄埋氧化物SOI和finfet)的影响。定量分析了三个主要的变化源:随机掺杂分布、栅极长度偏差和线边缘粗糙度。该分析还介绍了采用无掺杂体、中间隙金属栅极和纳米线通道实现的16nm节点低电压波动晶体管
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引用次数: 33
High-Temperature, High Reliability EEPROM Design For Automotive Applications 高温、高可靠性汽车EEPROM设计
Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320818
J. Walsh, G. Scott
An EEPROM has been developed capable of extreme temperature ranges not currently available in the industry. The memory is expected to handle 100K write cycles, 10K of which can be at 175C. To accommodate the reliable operation at the extreme temperature and write-cycle conditions without adding steps to the base process, several cell and system level design techniques were implemented including a differential bit architecture, time and temperature program voltage shaping
已经开发出一种EEPROM,能够在目前行业中无法提供的极端温度范围内工作。内存预计可以处理100K个写周期,其中10K可以在175C。为了适应在极端温度和写循环条件下的可靠运行,而不增加基本过程的步骤,采用了几种单元和系统级设计技术,包括差分位结构、时间和温度程序电压整形
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引用次数: 1
EDA Challenges in Nano-scale Technology 纳米级技术中的EDA挑战
Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320844
J. Kawa, C. Chiang, R. Camposano
Since the onset of the 90 nm node the challenges associated with further transistor scaling while maintaining a consistently functional, reliable, and yielding design have increased substantially. While those challenges carry across the spectrum of the manufacturing, the EDA, and the design communities, we believe it is the responsibility and the goal of the EDA industry to deal with those issues as thoroughly and as seamlessly as possible to make those challenges transparent to the designer. In this paper we expose and analyze a plurality of those challenges and briefly go over the solutions EDA tools are offering for dealing with them. We also look forward and cover some of the future challenges associated with the integration of the emerging bottoms-up nano-materials flow with the traditional CMOS top-down process flow which has also entered the nano-era
自90纳米节点开始以来,在保持一致的功能、可靠性和产量设计的同时,进一步缩放晶体管的挑战已经大大增加。虽然这些挑战贯穿于制造业、EDA和设计界,但我们相信EDA行业的责任和目标是尽可能彻底和无缝地处理这些问题,使这些挑战对设计师透明。在本文中,我们揭示并分析了其中的许多挑战,并简要介绍了EDA工具为处理这些挑战提供的解决方案。我们还展望并涵盖了与新兴的自下而上的纳米材料流与传统的CMOS自上而下的工艺流集成相关的一些未来挑战,这些工艺流也已进入纳米时代
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引用次数: 18
An Energy Scalable Computational Array for Sensor Signal Processing 用于传感器信号处理的能量可扩展计算阵列
Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320900
Liping Guo, M. Scott, R. Amirtharajah
Harvesting energy from environmental sources can extend wireless sensor network node lifetime beyond the limits of battery technology. However, the output power from an energy harvester is highly variable. We propose a domain-specific computational array which maximizes sensor performance by matching system power consumption to the available scavenged energy through power scalable approximate signal processing. The array consists of distributed arithmetic (DA) based functional units coupled with a reconfigurable interconnect structure. Each unit implements several core linear and nonlinear signal processing functions in an area efficient manner which also minimizes leakage power. Several sensor DSP applications (FIR, IIR, and FFT) have been mapped onto the array. Post-layout simulations confirm that the proposed domain-specific computational array is energy efficient and energy scalable
从环境中收集能量可以延长无线传感器网络节点的寿命,超出电池技术的极限。然而,能量采集器的输出功率是高度可变的。我们提出了一种特定领域的计算阵列,通过功率可扩展的近似信号处理,将系统功耗与可用的清除能量相匹配,从而最大化传感器性能。该阵列由基于分布式算法的功能单元和可重构的互连结构组成。每个单元实现了几个核心的线性和非线性信号处理功能,在一个区域有效的方式,也最大限度地减少泄漏功率。几个传感器DSP应用(FIR, IIR和FFT)已经映射到阵列上。布局后仿真证实了所提出的特定领域计算阵列具有节能和能量可扩展性
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引用次数: 5
A 50-GHz Phase-Locked Loop in 130-nm CMOS 130nm CMOS中的50ghz锁相环
Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320940
C. Cao, Yanping Ding, K. O. Kenneth
A 50-GHz charge pump phase locked loop (PLL) utilizing an LC-oscillator based injection locked divider is fabricated in a 130-nm logic CMOS process. The PLL can be locked from 45.9 to 50.5 GHz and output power level is around -10 dBm. The circuit including buffers consumes 57 mW from 1.5/0.8 V supplies. The phase noise at 50 kHz, 1 MHz and 10 MHz offset from the carrier is -63.5, -72, and -99 dBc/Hz, respectively. The PLL also outputs -22-dBm second order harmonic frequencies between 91.8 and 101 GHz
利用lc振荡器的注入锁相分压器,在130纳米CMOS工艺中制备了50 ghz电荷泵锁相环(PLL)。锁相环可以在45.9至50.5 GHz范围内锁定,输出功率水平约为-10 dBm。包含缓冲器的电路从1.5/0.8 V电源消耗57 mW。在载波偏移量为50khz、1mhz和10mhz时,相位噪声分别为-63.5、-72和-99 dBc/Hz。锁相环还输出- 22dbm的二阶谐波频率,频率范围在91.8和101 GHz之间
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引用次数: 40
A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique 一种100 ms /s 4 mhz带宽77.3 db SNDR ΔΣ三采样ADC
Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320962
Y. Kanazawa, Y. Fujimoto, Pascal Lo Ré, M. Miyamoto
A new ΔΣ ADC architecture using a triple sampling technique and a two-step summation scheme is presented. A 4th-order switched-capacitor ΔΣ ADC with a 4-bit quantizer is designed for a low-power direct-conversion digital TV receiver SoC. It achieves a 77.3-dB SNDR over a 4-MHz bandwidth with a 100-MHz clock frequency. The chip, fabricated in a 0.18-mum CMOS process, occupies 1.57 mm2 and draws 15.3 mA from a 1.8-V supply. It achieves a 0.58-pJ/conversion FOM
提出了一种采用三重采样技术和两步求和的新型ΔΣ ADC结构。设计了一种带4位量化器的4阶开关电容ΔΣ ADC,用于低功耗直接转换数字电视接收器SoC。在100 mhz时钟频率下,在4 mhz带宽上实现77.3 db SNDR。该芯片采用0.18 μ m CMOS工艺制造,占地1.57 mm2,从1.8 v电源输出15.3 mA。它实现了0.58 pj /转换FOM
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引用次数: 12
A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver 采用全差分脉冲接收机的36Gb/s ACCI多通道总线
Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320976
L. Luo, John M. Wilson, S. Mick, Jian Xu, L. Zhang, E. Erickson, P. Franzon
A new differential pulse receiver is demonstrated for AC coupled interconnect (ACCI), which enables the highest data rate, at 6Gb/s/channel (36Gb/s aggregate), for capacitively coupled systems using pulse signaling. The system works across FR4 printed circuit board (PCB) interconnect lengths of up to 30cm with coupling capacitors from 95fF to 165fF, while dissipating only 1.97mW/Gbps for the entire differential transceiver (0.83pJ/bit for the transmitter and 1.23pJ/bit for the receiver)
介绍了一种新型差分脉冲接收器,用于交流耦合互连(ACCI),可为使用脉冲信号的电容耦合系统提供6Gb/s/信道(总计36Gb/s)的最高数据速率。该系统可跨FR4印刷电路板(PCB)互连长度达30cm,耦合电容范围为95fF至165fF,而整个差分收发器的功耗仅为1.97mW/Gbps(发射器0.83pJ/bit,接收器1.23pJ/bit)。
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引用次数: 16
Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End 高IIP3电流模式RF CMOS前端的共门变压器反馈LNA
Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320941
A. Liscidini, Cesare Ghezzi, Emanuele Depaoli, G. Albasini, I. Bietti, R. Castello
A new topology of transformer based low noise amplifier is presented. The structure realizes a low noise input match and a current gain greater than one by a current to current positive feedback closed around a common gate stage. The amplifier is inserted in a high linearity current mode RF front-end receiver working between 4.15-4.4GHz with a NF of 4.2dB, a gain of 24.2dB and an IIP3 of -2dBm
提出了一种新的基于变压器的低噪声放大器拓扑结构。该结构通过闭合在公共栅极级附近的电流对电流正反馈实现了低噪声输入匹配和大于1的电流增益。该放大器插入一个高线性电流模式射频前端接收器,工作在4.15-4.4GHz之间,NF为4.2dB,增益为24.2dB, IIP3为-2dBm
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引用次数: 29
A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOS 基于0.18μm CMOS的10Gbps突发模式CDR电路
Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320828
Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu
A 10Gbps burst-mode clock and data recovery (CDR) circuit has been fabricated in 0.18mum CMOS technology. It recovers the input data and clock within 32 bits by using a gated voltage-controlled oscillator, a quadrature generator and a phase-aligning loop incorporating a half-rate bang-bang phase detector and a digital phase interpolator. The measured peak-to-peak jitter of the recovered clock is 10.44ps. The die area is 1.73 times 2.01 mm2 and draw 200mW from a 1.8V supply.
一个10Gbps突发模式时钟和数据恢复(CDR)电路已制成0.18 μ m CMOS技术。它通过使用一个门控压控振荡器、一个正交发生器和一个包含半速率bang-bang相位检测器和数字相位插补器的相位对准环路来恢复输入数据和32位内的时钟。测量到的恢复时钟的峰对峰抖动为10.44ps。模具面积为1.73乘以2.01 mm2,从1.8V电源吸取200mW。
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引用次数: 20
CMOS Mixed-Signal Circuit Process Variation Sensitivity Characterization for Yield Improvement 提高良率的CMOS混合信号电路工艺变化灵敏度表征
Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320950
Daeik D. Kim, Choongyeun Cho, Jonghae Kim, J. Plouchart, R. Trzcinski, D. Ahlgren
A mixed-signal circuit's performance and yield dependency on process variation are investigated with numerical circuit solution, statistical simulation, and implemented circuit measurement in 65nm partially-depleted silicon-on-insulator CMOS process. Increased relative variation in 65nm process is examined with site-to-site and wafer-to-wafer process variations. A current-controlled oscillator's performance and device threshold voltages are cross-correlated using simulation and RF measurement. Up to 93.9% cross-correlation between oscillation frequency and device threshold voltage is obtained, and strong model-to-hardware correlation is observed through statistical analysis of simulation result and circuit measurement. The yield learning process of design, simulation, measurement, and statistical analysis is proposed
采用数值电路求解、统计仿真和实现电路测量方法,研究了65nm部分耗尽绝缘体上硅CMOS工艺中混合信号电路的性能和良率对工艺变化的依赖关系。65nm制程中增加的相对变化通过点对点和晶圆对晶圆制程的变化来检验。通过仿真和射频测量,将电流控制振荡器的性能与器件阈值电压相互关联。通过对仿真结果和电路测量的统计分析,得出振荡频率与器件阈值电压的相互关系高达93.9%,且模型-硬件相关性强。提出了设计、仿真、测量和统计分析的良率学习过程
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引用次数: 30
期刊
IEEE Custom Integrated Circuits Conference 2006
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