Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320886
C. Hagleitner, A. R. Bonaccio, H. Rothuizen, D. Wiesmann, J. Lienemann, J. Korvink, G. Cherubini, E. Eleftheriou
The paper presents an integrated analog front-end (AFE) for the read-channel of a parallel scanning-probe storage device. The read/write element is based on an array of microfabricated silicon cantilevers equipped with heating elements to form nanometer-sized indentations in a polymer surface using integral atomic-force microscopy (AFM) tips. A detailed model based on a combination of a thermal/electrical lumped-element model and behavioral model of the electrostatic/mechanical part was developed. The behavioral model of the electrostatic/mechanical part is automatically generated from a full finite-element model (FEM). The model is completely implemented in Verilog-A and was used to co-develop the integrated analog front-end circuitry together with the read/write cantilever. The model and the analog front-end were simulated together and the results were experimentally verified. The approach chosen is well suited for system-level simulation and verification/extraction in a design environment based on standard EDA tools
{"title":"Modeling, Design, and Verification for the Analog Front-end of a MEMS-based Parallel Scanning-probe Storage Device","authors":"C. Hagleitner, A. R. Bonaccio, H. Rothuizen, D. Wiesmann, J. Lienemann, J. Korvink, G. Cherubini, E. Eleftheriou","doi":"10.1109/CICC.2006.320886","DOIUrl":"https://doi.org/10.1109/CICC.2006.320886","url":null,"abstract":"The paper presents an integrated analog front-end (AFE) for the read-channel of a parallel scanning-probe storage device. The read/write element is based on an array of microfabricated silicon cantilevers equipped with heating elements to form nanometer-sized indentations in a polymer surface using integral atomic-force microscopy (AFM) tips. A detailed model based on a combination of a thermal/electrical lumped-element model and behavioral model of the electrostatic/mechanical part was developed. The behavioral model of the electrostatic/mechanical part is automatically generated from a full finite-element model (FEM). The model is completely implemented in Verilog-A and was used to co-develop the integrated analog front-end circuitry together with the read/write cantilever. The model and the analog front-end were simulated together and the results were experimentally verified. The approach chosen is well suited for system-level simulation and verification/extraction in a design environment based on standard EDA tools","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126764108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320895
J. Li, Xiao-Qing Zeng, Lei Xie, Jun Chen, Jianyun Zhang, Yawei Guo
This paper describes a 10-bit 30-MS/s subsampling pipelined ADC that is implemented in a 0.18 mum CMOS process. The ADC adopts a power efficient amplifier sharing architecture in which a set of switches is introduced to reduce the influence between the two opamp-sharing successive stages. A new configuration is used in the first stage of the ADC to avoid using a dedicated sample-and-hold amplifier (SHA) circuit at the input and to avoid the matching requirement between the first multiplying digital-to-analog converter (MDAC) and flash input signal paths, which is very strict in a traditional SHA-less architecture. The measured differential and integral nonlinearities of the prototype show less than 0.57 least significant bit (LSB) and 0.8 LSB respectively at full sampling rate. The ADC exhibits higher than 9.1 effective number of bits (ENOB) for input frequencies up to 30 MHz, which is the twofold Nyquist rate (fs/2), at 30 MS/s. The ADC consumes 21.6 mW from a 1.8-V supply and occupies 0.7 mm2, which also includes the bandgap and buffer amplifiers
本文介绍了一种以0.18 μ m CMOS工艺实现的10位30 ms /s次采样流水线ADC。ADC采用功率高效的放大器共享架构，在该架构中引入了一组开关，以减少两个放大器共享级之间的影响。为了避免在输入端使用专用的采样保持放大器(SHA)电路，并避免第一乘法数模转换器(MDAC)和闪存输入信号路径之间的匹配要求，在传统的无SHA架构中，这是非常严格的。在全采样率下，样机的微分非线性和积分非线性分别小于0.57和0.8 LSB。当输入频率高达30 MHz时，ADC的有效位数(ENOB)高于9.1，这是30 MS/s时奈奎斯特速率(fs/2)的两倍。ADC从1.8 v电源消耗21.6 mW，占地0.7 mm2，其中还包括带隙和缓冲放大器
{"title":"A 1.8-V 22-mW 10-bit 30-MS/s Subsampling Pipelined CMOS ADC","authors":"J. Li, Xiao-Qing Zeng, Lei Xie, Jun Chen, Jianyun Zhang, Yawei Guo","doi":"10.1109/CICC.2006.320895","DOIUrl":"https://doi.org/10.1109/CICC.2006.320895","url":null,"abstract":"This paper describes a 10-bit 30-MS/s subsampling pipelined ADC that is implemented in a 0.18 mum CMOS process. The ADC adopts a power efficient amplifier sharing architecture in which a set of switches is introduced to reduce the influence between the two opamp-sharing successive stages. A new configuration is used in the first stage of the ADC to avoid using a dedicated sample-and-hold amplifier (SHA) circuit at the input and to avoid the matching requirement between the first multiplying digital-to-analog converter (MDAC) and flash input signal paths, which is very strict in a traditional SHA-less architecture. The measured differential and integral nonlinearities of the prototype show less than 0.57 least significant bit (LSB) and 0.8 LSB respectively at full sampling rate. The ADC exhibits higher than 9.1 effective number of bits (ENOB) for input frequencies up to 30 MHz, which is the twofold Nyquist rate (fs/2), at 30 MS/s. The ADC consumes 21.6 mW from a 1.8-V supply and occupies 0.7 mm2, which also includes the bandgap and buffer amplifiers","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126247810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320824
K. O. Kenneth, Kihong Kim, B. Floyd, J. Mehta, H. Yoon, C. Hung, D. Bravo, T. Dickson, Xiaoling Guo, Ran Li, N. Trichy, J. Caserta, W. Bomstad, J. Branch, Dong-Jun Yang, J. Bohorquez, Jie Chen, E. Seok, J. Brewer, Li Gao, A. Sugavanam, Jau-Jr Lin, Y. Su, C. Cao, M. Hwang, Yanping Ding, Zhenbiao Li, S.-H. Hwang, H. Wu, S. Sankaran, N. Zhang
The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated. The key challenges including the effects of metal structures associated with integrated circuits, heat removal, packaging, and interaction of transmitted and received signals with nearby circuits appear to be manageable. This technology can potentially be used for intra and inter-chip interconnection, and implementation of true single chip radios, beacons, radars, RFID tags and others, as well as contact-less high frequency testing
{"title":"Silicon Integrated Circuits Incorporating Antennas","authors":"K. O. Kenneth, Kihong Kim, B. Floyd, J. Mehta, H. Yoon, C. Hung, D. Bravo, T. Dickson, Xiaoling Guo, Ran Li, N. Trichy, J. Caserta, W. Bomstad, J. Branch, Dong-Jun Yang, J. Bohorquez, Jie Chen, E. Seok, J. Brewer, Li Gao, A. Sugavanam, Jau-Jr Lin, Y. Su, C. Cao, M. Hwang, Yanping Ding, Zhenbiao Li, S.-H. Hwang, H. Wu, S. Sankaran, N. Zhang","doi":"10.1109/CICC.2006.320824","DOIUrl":"https://doi.org/10.1109/CICC.2006.320824","url":null,"abstract":"The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated. The key challenges including the effects of metal structures associated with integrated circuits, heat removal, packaging, and interaction of transmitted and received signals with nearby circuits appear to be manageable. This technology can potentially be used for intra and inter-chip interconnection, and implementation of true single chip radios, beacons, radars, RFID tags and others, as well as contact-less high frequency testing","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126286198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320964
M. Safi-Harb, G. Roberts
An on-chip digitizer for the transient measurement of digital signal integrity is proposed. Undersampling, combined with single-path time-domain processing is used to perform the embedded measurement in a time-efficient manner. On-chip interconnect crosstalk generation with variable strength is included on chip for characterization, and successfully measured using a prototype chip, implemented in a 0.18 mum CMOS process. The proposed system is easily calibratable, with an estimated static power dissipation of ~3.5 mW. The total active area taken up by the associated test and calibration vehicles is 0.45 mm2
提出了一种用于数字信号完整性瞬态测量的片上数字化仪。欠采样与单路径时域处理相结合，以时间效率的方式进行嵌入式测量。具有可变强度的片上互连串扰生成包括在芯片上进行表征，并使用原型芯片成功测量，在0.18 μ m CMOS工艺中实现。该系统易于校准，估计静态功耗约为3.5 mW。相关测试及校正车辆占用的总活动面积为0.45 mm2
{"title":"A 70-GHz Effective Sampling Rate On-Chip Oscilloscope with Time-Domain Digitization","authors":"M. Safi-Harb, G. Roberts","doi":"10.1109/CICC.2006.320964","DOIUrl":"https://doi.org/10.1109/CICC.2006.320964","url":null,"abstract":"An on-chip digitizer for the transient measurement of digital signal integrity is proposed. Undersampling, combined with single-path time-domain processing is used to perform the embedded measurement in a time-efficient manner. On-chip interconnect crosstalk generation with variable strength is included on chip for characterization, and successfully measured using a prototype chip, implemented in a 0.18 mum CMOS process. The proposed system is easily calibratable, with an estimated static power dissipation of ~3.5 mW. The total active area taken up by the associated test and calibration vehicles is 0.45 mm2","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122822027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1093/ietele/e90-c.6.1241
T. Mitomo, O. Watanabe, R. Fujimoto, S. Kawaguchi
A quadrature demodulator (QDEMOD) for WCDMA direct-conversion receiver using common-base input stage is reported. A common-base input stage is robust to parasitic elements and is suitable for on-chip matching circuits to realize small and low-cost RF front-end modules. However, a common-mode blocker signal, such as the transmitter (TX) leakage signal, degrades the noise performance due to intermodulation distortion of the TX leakage signal and noise. We propose a QDEMOD with a common-base input stage that is capable of suppressing the TX leakage signal using symmetrical inductors. The QDEMOD was fabricated using Si-Ge BiCMOS process with fT of 75 GHz. The measured results show that the NF degradation does not occur until the TX leakage signal input is larger than -13 dBm
{"title":"A Quadrature Demodulator for WCDMA Receiver Using Common-Base Input Stage with Robustness to Transmitter Leakage","authors":"T. Mitomo, O. Watanabe, R. Fujimoto, S. Kawaguchi","doi":"10.1093/ietele/e90-c.6.1241","DOIUrl":"https://doi.org/10.1093/ietele/e90-c.6.1241","url":null,"abstract":"A quadrature demodulator (QDEMOD) for WCDMA direct-conversion receiver using common-base input stage is reported. A common-base input stage is robust to parasitic elements and is suitable for on-chip matching circuits to realize small and low-cost RF front-end modules. However, a common-mode blocker signal, such as the transmitter (TX) leakage signal, degrades the noise performance due to intermodulation distortion of the TX leakage signal and noise. We propose a QDEMOD with a common-base input stage that is capable of suppressing the TX leakage signal using symmetrical inductors. The QDEMOD was fabricated using Si-Ge BiCMOS process with fT of 75 GHz. The measured results show that the NF degradation does not occur until the TX leakage signal input is larger than -13 dBm","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131383283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320970
David A. Yokoyama-Martin, K. Krishna, J. Stonick, Aaron Caffee, E. K. Gamble, Chris Jones, J. Mcneal, J. Parker, Ross Segelken, J. Sonntag, K. Umino, J. Upton, D. Weinlader, Skye Wolfer
A low power, small area transceiver PHY that supports PCIetrade, SATA II, and XAUI was fabricated in TSMC's 90nm dual gate CMOS. Each lane occupies an area of 400mum times 430mum. Operation also requires a clock module of 400mum times 430mum. A 4-lane, wirebond testchip consumes 195mW of power at 3.125Gb/s. The paper focuses on the analog sections of the transmit and receive blocks
{"title":"A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS","authors":"David A. Yokoyama-Martin, K. Krishna, J. Stonick, Aaron Caffee, E. K. Gamble, Chris Jones, J. Mcneal, J. Parker, Ross Segelken, J. Sonntag, K. Umino, J. Upton, D. Weinlader, Skye Wolfer","doi":"10.1109/CICC.2006.320970","DOIUrl":"https://doi.org/10.1109/CICC.2006.320970","url":null,"abstract":"A low power, small area transceiver PHY that supports PCIetrade, SATA II, and XAUI was fabricated in TSMC's 90nm dual gate CMOS. Each lane occupies an area of 400mum times 430mum. Operation also requires a clock module of 400mum times 430mum. A 4-lane, wirebond testchip consumes 195mW of power at 3.125Gb/s. The paper focuses on the analog sections of the transmit and receive blocks","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131443578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320936
L.M. Kalyani-Garimella, A. Garimella, J. Ramírez-Angulo, R. Carvajal, A. López-Martín
A highly versatile general purpose analog/digital/ neural configurable logic block (LVUC) for utilization in the next generation of mixed signal field programmable gate arrays is reported. The cell is a truly universal building block, very compact and has low power, low voltage requirements and operates with rail-to-rail analog and digital signals. It can be easily configured to perform as a digital, analog, analog to digital, digital to analog and neural configurable block. Experimental results of a fabricated test chip are presented that validate the proposed cell operating with rail-to-rail signals from a single supply as low as 1.4V
{"title":"Low-Voltage Universal Cell (LVUC): A Compact Analog/Digital Logic Block for Mixed Signal FPGAs","authors":"L.M. Kalyani-Garimella, A. Garimella, J. Ramírez-Angulo, R. Carvajal, A. López-Martín","doi":"10.1109/CICC.2006.320936","DOIUrl":"https://doi.org/10.1109/CICC.2006.320936","url":null,"abstract":"A highly versatile general purpose analog/digital/ neural configurable logic block (LVUC) for utilization in the next generation of mixed signal field programmable gate arrays is reported. The cell is a truly universal building block, very compact and has low power, low voltage requirements and operates with rail-to-rail analog and digital signals. It can be easily configured to perform as a digital, analog, analog to digital, digital to analog and neural configurable block. Experimental results of a fabricated test chip are presented that validate the proposed cell operating with rail-to-rail signals from a single supply as low as 1.4V","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132553647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320927
B. Mesgarzadeh, A. Alvandpour
This paper presents an analysis of first-harmonic injection locking in CMOS ring oscillators. In this analysis, Adler's equation is proved by using a new analytical approach based on the propagation delay of an inverter stage. Also the behavior of the injection-locked ring oscillators from phase noise point of view is discussed and a closed-form equation for the phase noise of such oscillators is derived. According to the measurement results on a DLL-based frequency multiplier implemented in 0.13-mum CMOS process, good agreement between theoretical prediction and measurements is observed
本文分析了CMOS环形振荡器中一次谐波注入锁紧问题。在分析中，采用一种新的基于逆变器级传播延迟的分析方法证明了Adler方程。从相位噪声的角度讨论了锁注入环振子的特性，并推导了锁注入环振子相位噪声的封闭方程。根据在0.13 μ m CMOS工艺中实现的基于dll的倍频器的测量结果，理论预测与测量结果吻合较好
{"title":"First-Harmonic Injection-Locked Ring Oscillators","authors":"B. Mesgarzadeh, A. Alvandpour","doi":"10.1109/CICC.2006.320927","DOIUrl":"https://doi.org/10.1109/CICC.2006.320927","url":null,"abstract":"This paper presents an analysis of first-harmonic injection locking in CMOS ring oscillators. In this analysis, Adler's equation is proved by using a new analytical approach based on the propagation delay of an inverter stage. Also the behavior of the injection-locked ring oscillators from phase noise point of view is discussed and a closed-form equation for the phase noise of such oscillators is derived. According to the measurement results on a DLL-based frequency multiplier implemented in 0.13-mum CMOS process, good agreement between theoretical prediction and measurements is observed","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133468736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.321008
K. Arimoto, F. Morishita, I. Hayashi, T. Tanizaki, T. Ipposhi, K. Dosaka
We had reported TTRAM (Morishita, 2005) and ET2RAM (Arimoto, 2006) which are high-density capacitor-less SOI-CMOS compatible memory IP's. A platform design methodology becomes the main stream in SoC world because the system integration progress and complexity requires the implementation of many lands of IP's and induces the longer design turn around time and design cost up. This time, we have up-graded ET2RAM with scalable function named SETRAM (scalable enhanced twin-transistor RAM). This memory IP can be applied to the many kinds of applications by the verify control technique with compact ABC (automatic body control) sense amplifier. The scalable functions are, for example, 263MHz high speed random cycle memory to replace the high density on chip SRAM, 79mW/4Mb lower active power dissipation for mobile application, 453MHz data transfer of page/burst mode for cache memory and graphics memory applications and lower stand-by current mode of 5 sec data retention time. These are also supported as the programmable functions. The SETRAM can provide the scalable memory IP's in SoC platform on SOI devices and can improve the performance of many future applications
{"title":"A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI","authors":"K. Arimoto, F. Morishita, I. Hayashi, T. Tanizaki, T. Ipposhi, K. Dosaka","doi":"10.1109/CICC.2006.321008","DOIUrl":"https://doi.org/10.1109/CICC.2006.321008","url":null,"abstract":"We had reported TTRAM (Morishita, 2005) and ET2RAM (Arimoto, 2006) which are high-density capacitor-less SOI-CMOS compatible memory IP's. A platform design methodology becomes the main stream in SoC world because the system integration progress and complexity requires the implementation of many lands of IP's and induces the longer design turn around time and design cost up. This time, we have up-graded ET2RAM with scalable function named SETRAM (scalable enhanced twin-transistor RAM). This memory IP can be applied to the many kinds of applications by the verify control technique with compact ABC (automatic body control) sense amplifier. The scalable functions are, for example, 263MHz high speed random cycle memory to replace the high density on chip SRAM, 79mW/4Mb lower active power dissipation for mobile application, 453MHz data transfer of page/burst mode for cache memory and graphics memory applications and lower stand-by current mode of 5 sec data retention time. These are also supported as the programmable functions. The SETRAM can provide the scalable memory IP's in SoC platform on SOI devices and can improve the performance of many future applications","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134122161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320907
J. Lindeberg, Olli Väänänen, J. Pirkkalaniemi, M. Kosunen, K. Halonen
A digital OFDM modulator with 2048-point IFFT and 83.2 MHz bandwidth is implemented. The modulator consists of IFFT block, upsampling filters and upconversion included in the upsampling operation. Also a clipping unit is implemented before the on-chip D/A-converter in order to efficiently utilise the whole dynamic range of the converter and to maximise the power efficiency of the power amplifier. An inverse sine block is added to compensate the D/A-converter's sine response. The digital IF signal is converted to analog signal by using a 10-bit on-chip D/A-converter with sampling frequency of 819.2 MHz and center frequency of 204.8 MHz. The IFFT block is implemented with FPGA device and the rest of the system is fabricated in a 90 nm CMOS process
{"title":"OFDM modulator with digital IF and on-chip D/A-converter","authors":"J. Lindeberg, Olli Väänänen, J. Pirkkalaniemi, M. Kosunen, K. Halonen","doi":"10.1109/CICC.2006.320907","DOIUrl":"https://doi.org/10.1109/CICC.2006.320907","url":null,"abstract":"A digital OFDM modulator with 2048-point IFFT and 83.2 MHz bandwidth is implemented. The modulator consists of IFFT block, upsampling filters and upconversion included in the upsampling operation. Also a clipping unit is implemented before the on-chip D/A-converter in order to efficiently utilise the whole dynamic range of the converter and to maximise the power efficiency of the power amplifier. An inverse sine block is added to compensate the D/A-converter's sine response. The digital IF signal is converted to analog signal by using a 10-bit on-chip D/A-converter with sampling frequency of 819.2 MHz and center frequency of 204.8 MHz. The IFFT block is implemented with FPGA device and the rest of the system is fabricated in a 90 nm CMOS process","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134243141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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