Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320898
A. Scholten, R. V. Langevelde, L. Tiemeijer, D. Klaassen
The physical background of the thermal noise equations of the PSP MOSFET model is presented. The PSP thermal noise model is shown to pass a number of proposed benchmark tests for MOSFET thermal noise. Without any fitting parameters, it is shown to predict with great accuracy a collection of experimental data on three modern CMOS technologies. The impact of device layout on noise properties is discussed and demonstrated experimentally
{"title":"Compact modeling of noise in CMOS","authors":"A. Scholten, R. V. Langevelde, L. Tiemeijer, D. Klaassen","doi":"10.1109/CICC.2006.320898","DOIUrl":"https://doi.org/10.1109/CICC.2006.320898","url":null,"abstract":"The physical background of the thermal noise equations of the PSP MOSFET model is presented. The PSP thermal noise model is shown to pass a number of proposed benchmark tests for MOSFET thermal noise. Without any fitting parameters, it is shown to predict with great accuracy a collection of experimental data on three modern CMOS technologies. The impact of device layout on noise properties is discussed and demonstrated experimentally","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127297087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320947
M. Hansson, B. Mesgarzadeh, A. Alvandpour
This paper describes a successful experiment of 1.56-GHz on-chip LC-tank resonant clock oscillator, which directly drives 2times896 flip-flops, without intermediate buffers. Detailed power measurements of a test-chip in 130-nm CMOS technology show that the proposed resonant clocking technique results in 57 % lower clock power and 15-30 % lower total chip power compared to the conventional clocking strategy implemented on the same chip. Furthermore, clock jitter measurements show a worst-case peak-to-peak jitter of 28.4 ps (or 14.5 ps using injection locking) across 0-to-80 % data activity in flip-flops and the data-path logic
{"title":"1.56 GHz On-chip Resonant Clocking in 130nm CMOS","authors":"M. Hansson, B. Mesgarzadeh, A. Alvandpour","doi":"10.1109/CICC.2006.320947","DOIUrl":"https://doi.org/10.1109/CICC.2006.320947","url":null,"abstract":"This paper describes a successful experiment of 1.56-GHz on-chip LC-tank resonant clock oscillator, which directly drives 2times896 flip-flops, without intermediate buffers. Detailed power measurements of a test-chip in 130-nm CMOS technology show that the proposed resonant clocking technique results in 57 % lower clock power and 15-30 % lower total chip power compared to the conventional clocking strategy implemented on the same chip. Furthermore, clock jitter measurements show a worst-case peak-to-peak jitter of 28.4 ps (or 14.5 ps using injection locking) across 0-to-80 % data activity in flip-flops and the data-path logic","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125109042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320851
A. Shameli, A. Safarian, A. Rofougaran, M. Rofougaran, F. D. Flaviis
A novel switching power amplifier based on the concept of digital to analog converter (DAC) is presented for polar transmitter architecture. The novel idea in this amplifier is to generate a current proportional to the amplitude modulation signal and the power control bits. The current is then up-converted to the frequency of interest using switching transistors. In this paper, we demonstrate that the performance of the proposed circuit is superior compare to the existing power amplifiers designed for polar transmitter. The measurement results show maximum output power of 27.8dBm with power efficiency of 34%. Moreover, the amplifier exhibits amplitude modulation bandwidth of 4.2MHz and 62dB power control dynamic range. The circuit is fabricated in CMOS 0.18mum process with 3.3V power supply
{"title":"A Novel DAC Based Switching Power Amplifier for Polar Transmitter","authors":"A. Shameli, A. Safarian, A. Rofougaran, M. Rofougaran, F. D. Flaviis","doi":"10.1109/CICC.2006.320851","DOIUrl":"https://doi.org/10.1109/CICC.2006.320851","url":null,"abstract":"A novel switching power amplifier based on the concept of digital to analog converter (DAC) is presented for polar transmitter architecture. The novel idea in this amplifier is to generate a current proportional to the amplitude modulation signal and the power control bits. The current is then up-converted to the frequency of interest using switching transistors. In this paper, we demonstrate that the performance of the proposed circuit is superior compare to the existing power amplifiers designed for polar transmitter. The measurement results show maximum output power of 27.8dBm with power efficiency of 34%. Moreover, the amplifier exhibits amplitude modulation bandwidth of 4.2MHz and 62dB power control dynamic range. The circuit is fabricated in CMOS 0.18mum process with 3.3V power supply","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124058503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320837
J. Watts
The design of an integrated circuit requires the efforts of a large number of people with a wide range of skills. The compact model is a communication tool by which the designer of transistors, resistors and other circuit elements tells the designer of circuits how the circuit elements behave. Without this information the circuit design would be a trial and error process and modern electronics would be impossible. High quality, industry standard compact models enhance the productivity of the industry by enabling precise communication between any device design team, and any circuit design team, anywhere in the world. To be useful for leading edge design the compact model must keep up with the pace of semiconductor technology innovation. This is the great challenge for the Compact Model Council. It is only possible because the CMC creates collaboration between academics, semiconductor foundries, EDA vendors and circuit designers
{"title":"Enhancing Productivity by Continuously Improving Standard Compact Models","authors":"J. Watts","doi":"10.1109/CICC.2006.320837","DOIUrl":"https://doi.org/10.1109/CICC.2006.320837","url":null,"abstract":"The design of an integrated circuit requires the efforts of a large number of people with a wide range of skills. The compact model is a communication tool by which the designer of transistors, resistors and other circuit elements tells the designer of circuits how the circuit elements behave. Without this information the circuit design would be a trial and error process and modern electronics would be impossible. High quality, industry standard compact models enhance the productivity of the industry by enabling precise communication between any device design team, and any circuit design team, anywhere in the world. To be useful for leading edge design the compact model must keep up with the pace of semiconductor technology innovation. This is the great challenge for the Compact Model Council. It is only possible because the CMC creates collaboration between academics, semiconductor foundries, EDA vendors and circuit designers","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121528373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.321012
Gokce Keskin, Xin Li, L. Pileggi
An active on-chip circuit is demonstrated in 130nm CMOS for the suppression of on-chip power supply noise due to power distribution resonance. Testchip measurement results indicate up to 40% reduction in power supply noise during clock/power gating at a 2% power and 6% area overhead cost. Oscillation time is reduced by 50%. Simulation results show that comparable overshoot/undershoot and ringing control via on-chip decoupling would require significantly more area and power due to leakage, particularly at 90nm and below
{"title":"Active On-Die Suppression of Power Supply Noise","authors":"Gokce Keskin, Xin Li, L. Pileggi","doi":"10.1109/CICC.2006.321012","DOIUrl":"https://doi.org/10.1109/CICC.2006.321012","url":null,"abstract":"An active on-chip circuit is demonstrated in 130nm CMOS for the suppression of on-chip power supply noise due to power distribution resonance. Testchip measurement results indicate up to 40% reduction in power supply noise during clock/power gating at a 2% power and 6% area overhead cost. Oscillation time is reduced by 50%. Simulation results show that comparable overshoot/undershoot and ringing control via on-chip decoupling would require significantly more area and power due to leakage, particularly at 90nm and below","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114897220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320848
A. Jerng, C. Sodini
A low power, wideband transmitter architecture utilizing ΔΣ direct digital modulation of an RF carrier is presented. Spurious signals associated with direct digital-RF conversion are eliminated through integration of a self-tuned passive LC bandpass filter. The digital-RF modulator is intended for OFDM systems and can provide data rates greater than 1 Gb/s using a bandwidth of 200 MHz centered at 5.25 GHz. Measured results show that the largest modulator spur is -44 dBc. The transmitter, including LO quadrature generator, quadrature digital-RF converter, and filter circuitry, consumes 50 mW and occupies a die area of 0.56 mm2 in a 0.13μm SiGe BiCMOS process.
{"title":"A Wideband ΔΣ Digital-RF Modulator With Self-Tuned RF Bandpass Reconstruction Filter","authors":"A. Jerng, C. Sodini","doi":"10.1109/CICC.2006.320848","DOIUrl":"https://doi.org/10.1109/CICC.2006.320848","url":null,"abstract":"A low power, wideband transmitter architecture utilizing ΔΣ direct digital modulation of an RF carrier is presented. Spurious signals associated with direct digital-RF conversion are eliminated through integration of a self-tuned passive LC bandpass filter. The digital-RF modulator is intended for OFDM systems and can provide data rates greater than 1 Gb/s using a bandwidth of 200 MHz centered at 5.25 GHz. Measured results show that the largest modulator spur is -44 dBc. The transmitter, including LO quadrature generator, quadrature digital-RF converter, and filter circuitry, consumes 50 mW and occupies a die area of 0.56 mm2 in a 0.13μm SiGe BiCMOS process.","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116689972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320948
P. Mercier, S. R. Singh, K. Iniewski, B. Moore, P. O'Shea
It has been shown that stacking a set of known good dice into a 3D chip array may be beneficial in terms of system performance and footprint area. This paper demonstrates that, in the general sense, it is also beneficial to arrange chips into a 3D stack from yield and cost perspectives. It is shown that an optimal point occurs where cost is minimized by stacking an appropriate amount of dice into a single system
{"title":"Yield and Cost Modeling for 3D Chip Stack Technologies","authors":"P. Mercier, S. R. Singh, K. Iniewski, B. Moore, P. O'Shea","doi":"10.1109/CICC.2006.320948","DOIUrl":"https://doi.org/10.1109/CICC.2006.320948","url":null,"abstract":"It has been shown that stacking a set of known good dice into a 3D chip array may be beneficial in terms of system performance and footprint area. This paper demonstrates that, in the general sense, it is also beneficial to arrange chips into a 3D stack from yield and cost perspectives. It is shown that an optimal point occurs where cost is minimized by stacking an appropriate amount of dice into a single system","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116831034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320987
Y. Yamagata, H. Shirai, H. Sugimura, S. Arai, T. Wake, Ken Inoue, T. Sakoh, M. Sakao, T. Tanigawa
This paper presents embedded DRAM device technology utilizing stacked MIM(metal-insulator-metal) capacitor. Targeted for high random-access performance as well as low-power data-streaming applications, original structure named "full metal DRAM" has been devised and implemented from 150nm generation. This features reduced parasitic resistance of DRAM cell and fully-compatible CMOS Trs. characteristics with that of leading-edge CMOS. In 90nm generation, ZrO 2 is introduced as capacitor dielectric material for cell size reduction. For the next generation of 55nm, high-k gate dielectric(HfSiON) will be introduced in CMOS platform, which can be effectively exploited for embedded DRAM scaling and performance improvement
{"title":"Device Technology for embedded DRAM utilizing stacked MIM(Metal-Insulator-Metal) Capacitor","authors":"Y. Yamagata, H. Shirai, H. Sugimura, S. Arai, T. Wake, Ken Inoue, T. Sakoh, M. Sakao, T. Tanigawa","doi":"10.1109/CICC.2006.320987","DOIUrl":"https://doi.org/10.1109/CICC.2006.320987","url":null,"abstract":"This paper presents embedded DRAM device technology utilizing stacked MIM(metal-insulator-metal) capacitor. Targeted for high random-access performance as well as low-power data-streaming applications, original structure named \"full metal DRAM\" has been devised and implemented from 150nm generation. This features reduced parasitic resistance of DRAM cell and fully-compatible CMOS Trs. characteristics with that of leading-edge CMOS. In 90nm generation, ZrO 2 is introduced as capacitor dielectric material for cell size reduction. For the next generation of 55nm, high-k gate dielectric(HfSiON) will be introduced in CMOS platform, which can be effectively exploited for embedded DRAM scaling and performance improvement","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132219160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320977
Mike P. Li
We reviewed the roles that jitter and signaling plays in a high speed communication link. We then discuss the testing and verification methods for the link components of transmitter, receiver, medium, and reference clock. The latest statistical plus system transfer function based jitter and signaling test methods are introduced. In the end, we will introduce specific jitter and signaling testing requirements and associated testing methods for high speed communication standards such as PCI Express (PCIe), fibre channel (FC), and Giga Bit Ethernet (GBE)
{"title":"Jitter And Signaling Test For High-Speed Links","authors":"Mike P. Li","doi":"10.1109/CICC.2006.320977","DOIUrl":"https://doi.org/10.1109/CICC.2006.320977","url":null,"abstract":"We reviewed the roles that jitter and signaling plays in a high speed communication link. We then discuss the testing and verification methods for the link components of transmitter, receiver, medium, and reference clock. The latest statistical plus system transfer function based jitter and signaling test methods are introduced. In the end, we will introduce specific jitter and signaling testing requirements and associated testing methods for high speed communication standards such as PCI Express (PCIe), fibre channel (FC), and Giga Bit Ethernet (GBE)","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134104650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320968
Junyoung Park, M. Flynn
Capacitive coupling improves both phase noise and phase accuracy in coupled LC oscillators since the coupling current is in phase with the regeneration current. A prototype 3 GHz PLL with four LC oscillator stages and capacitive coupling is fabricated in 0.13mum CMOS. The long term measured RMS jitter of the buffered clock from the PLL is 1.61ps and the pk-pk jitter is 13.33ps
电容耦合提高了耦合LC振荡器的相位噪声和相位精度，因为耦合电流与再生电流是同相的。在0.13 μ m CMOS上制作了一个具有4级LC振荡器和电容耦合的3ghz锁相环原型。来自锁相环的缓冲时钟的长期测量有效值抖动为1.61ps, pk-pk抖动为13.33ps
{"title":"A Low Jitter Multi-Phase PLL with Capacitive Coupling","authors":"Junyoung Park, M. Flynn","doi":"10.1109/CICC.2006.320968","DOIUrl":"https://doi.org/10.1109/CICC.2006.320968","url":null,"abstract":"Capacitive coupling improves both phase noise and phase accuracy in coupled LC oscillators since the coupling current is in phase with the regeneration current. A prototype 3 GHz PLL with four LC oscillator stages and capacitive coupling is fabricated in 0.13mum CMOS. The long term measured RMS jitter of the buffered clock from the PLL is 1.61ps and the pk-pk jitter is 13.33ps","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134277955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：