Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320928
A. Mirzaei, M. E. Heidari, A. Abidi
Using the hard-limiting characteristics of transconductors, a new model for injection-locking, applicable for any strong and weak injection, is proposed. Backed by simulations, examples of the powerfulness of this new model are enumerated as proof of the concept.
{"title":"Analysis of Oscillators Locked by Large Injection Signals: Generalized Adler's Equation and Geometrical Interpretation","authors":"A. Mirzaei, M. E. Heidari, A. Abidi","doi":"10.1109/CICC.2006.320928","DOIUrl":"https://doi.org/10.1109/CICC.2006.320928","url":null,"abstract":"Using the hard-limiting characteristics of transconductors, a new model for injection-locking, applicable for any strong and weak injection, is proposed. Backed by simulations, examples of the powerfulness of this new model are enumerated as proof of the concept.","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134252406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320965
Ting Mei, J. Roychowdhury
In this paper, the authors present a simple but rigorous nonlinear analysis for understanding and predicting steady-state operation and injection locking in two-port nonlinear negative-resistance oscillators (such as the Colpitts, Pierce, etc., topologies commonly used in RFICs). Key advances of our approach include the use of vector-based nonlinear feedback analysis and treatment of amplitude and frequency components in a coupled way. The authors develop rigorous and insightful graphical approaches for output voltage estimation and injection lock range prediction. The authors validate the analytical approach against transient and harmonic balance simulations
{"title":"Rigorous Analytical/Graphical Injection Locking Analysis of Two-Port Negative Resistance Oscillators","authors":"Ting Mei, J. Roychowdhury","doi":"10.1109/CICC.2006.320965","DOIUrl":"https://doi.org/10.1109/CICC.2006.320965","url":null,"abstract":"In this paper, the authors present a simple but rigorous nonlinear analysis for understanding and predicting steady-state operation and injection locking in two-port nonlinear negative-resistance oscillators (such as the Colpitts, Pierce, etc., topologies commonly used in RFICs). Key advances of our approach include the use of vector-based nonlinear feedback analysis and treatment of amplitude and frequency components in a coupled way. The authors develop rigorous and insightful graphical approaches for output voltage estimation and injection lock range prediction. The authors validate the analytical approach against transient and harmonic balance simulations","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"118 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133356211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320871
Jing Cao, Haiqing Lin, Y. Xiang, Chun-Fu Kao, K. Dyer
A 90 nm CMOS 10-bit 1 GS/s current-steering D/A converter is presented. It is designed and optimized for next generation high-speed digital communication SoCs. With only five power/ground pins and a 10-bit architecture, 72 dB SFDR and 9.2 ENOB are measured with a full-scale 41.3 MHz input at 800 MS/s. At 1.05 GS/s, 68 dB SFDR is achieved for a full-scale 54.3 MHz input. It dissipates a core power of 49 mW, the lowest power consumption reported at this performance level, and occupies a die area of merely 0.36 mm2. The monolithic DAC is fabricated in TSMC 1P9M 90nm CMOS process
提出了一种90 nm CMOS 10位1gs /s电流转向数模转换器。它是为下一代高速数字通信soc而设计和优化的。仅使用5个电源/接地引脚和10位架构，在800 MS/s的41.3 MHz全尺寸输入下测量72 dB SFDR和9.2 ENOB。在1.05 GS/s下，满量程54.3 MHz输入可实现68 dB SFDR。它的核心功耗为49兆瓦，是该性能水平下报告的最低功耗，并且占据的芯片面积仅为0.36 mm2。单片DAC采用台积电1P9M 90nm CMOS工艺制造
{"title":"A 10-bit 1GSample/s DAC in 90nm CMOS for Embedded Applications","authors":"Jing Cao, Haiqing Lin, Y. Xiang, Chun-Fu Kao, K. Dyer","doi":"10.1109/CICC.2006.320871","DOIUrl":"https://doi.org/10.1109/CICC.2006.320871","url":null,"abstract":"A 90 nm CMOS 10-bit 1 GS/s current-steering D/A converter is presented. It is designed and optimized for next generation high-speed digital communication SoCs. With only five power/ground pins and a 10-bit architecture, 72 dB SFDR and 9.2 ENOB are measured with a full-scale 41.3 MHz input at 800 MS/s. At 1.05 GS/s, 68 dB SFDR is achieved for a full-scale 54.3 MHz input. It dissipates a core power of 49 mW, the lowest power consumption reported at this performance level, and occupies a die area of merely 0.36 mm2. The monolithic DAC is fabricated in TSMC 1P9M 90nm CMOS process","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124509880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320947
M. Hansson, B. Mesgarzadeh, A. Alvandpour
This paper describes a successful experiment of 1.56-GHz on-chip LC-tank resonant clock oscillator, which directly drives 2times896 flip-flops, without intermediate buffers. Detailed power measurements of a test-chip in 130-nm CMOS technology show that the proposed resonant clocking technique results in 57 % lower clock power and 15-30 % lower total chip power compared to the conventional clocking strategy implemented on the same chip. Furthermore, clock jitter measurements show a worst-case peak-to-peak jitter of 28.4 ps (or 14.5 ps using injection locking) across 0-to-80 % data activity in flip-flops and the data-path logic
{"title":"1.56 GHz On-chip Resonant Clocking in 130nm CMOS","authors":"M. Hansson, B. Mesgarzadeh, A. Alvandpour","doi":"10.1109/CICC.2006.320947","DOIUrl":"https://doi.org/10.1109/CICC.2006.320947","url":null,"abstract":"This paper describes a successful experiment of 1.56-GHz on-chip LC-tank resonant clock oscillator, which directly drives 2times896 flip-flops, without intermediate buffers. Detailed power measurements of a test-chip in 130-nm CMOS technology show that the proposed resonant clocking technique results in 57 % lower clock power and 15-30 % lower total chip power compared to the conventional clocking strategy implemented on the same chip. Furthermore, clock jitter measurements show a worst-case peak-to-peak jitter of 28.4 ps (or 14.5 ps using injection locking) across 0-to-80 % data activity in flip-flops and the data-path logic","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125109042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320930
Y. Ogasahara, Takashi Enami, M. Hashimoto, Takashi Sato, T. Onoye
Power integrity is an crucial design issue in nanometer technologies because of lowered supply voltage and current increase. This paper focuses on gate delay variation due to power/ground noise, and demonstrates measurement results in a 90nm technology. For full-chip simulation, a current model with capacitance and variable resistor is developed to accurately model current dependency on voltage drop. Measurement results are well correlated with simulation, and verify that gate delay depends on average voltage drop
{"title":"Measurement results of delay degradation due to power supply noise well correlated with full-chip simulation","authors":"Y. Ogasahara, Takashi Enami, M. Hashimoto, Takashi Sato, T. Onoye","doi":"10.1109/CICC.2006.320930","DOIUrl":"https://doi.org/10.1109/CICC.2006.320930","url":null,"abstract":"Power integrity is an crucial design issue in nanometer technologies because of lowered supply voltage and current increase. This paper focuses on gate delay variation due to power/ground noise, and demonstrates measurement results in a 90nm technology. For full-chip simulation, a current model with capacitance and variable resistor is developed to accurately model current dependency on voltage drop. Measurement results are well correlated with simulation, and verify that gate delay depends on average voltage drop","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132059252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320968
Junyoung Park, M. Flynn
Capacitive coupling improves both phase noise and phase accuracy in coupled LC oscillators since the coupling current is in phase with the regeneration current. A prototype 3 GHz PLL with four LC oscillator stages and capacitive coupling is fabricated in 0.13mum CMOS. The long term measured RMS jitter of the buffered clock from the PLL is 1.61ps and the pk-pk jitter is 13.33ps
电容耦合提高了耦合LC振荡器的相位噪声和相位精度，因为耦合电流与再生电流是同相的。在0.13 μ m CMOS上制作了一个具有4级LC振荡器和电容耦合的3ghz锁相环原型。来自锁相环的缓冲时钟的长期测量有效值抖动为1.61ps, pk-pk抖动为13.33ps
{"title":"A Low Jitter Multi-Phase PLL with Capacitive Coupling","authors":"Junyoung Park, M. Flynn","doi":"10.1109/CICC.2006.320968","DOIUrl":"https://doi.org/10.1109/CICC.2006.320968","url":null,"abstract":"Capacitive coupling improves both phase noise and phase accuracy in coupled LC oscillators since the coupling current is in phase with the regeneration current. A prototype 3 GHz PLL with four LC oscillator stages and capacitive coupling is fabricated in 0.13mum CMOS. The long term measured RMS jitter of the buffered clock from the PLL is 1.61ps and the pk-pk jitter is 13.33ps","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134277955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320977
Mike P. Li
We reviewed the roles that jitter and signaling plays in a high speed communication link. We then discuss the testing and verification methods for the link components of transmitter, receiver, medium, and reference clock. The latest statistical plus system transfer function based jitter and signaling test methods are introduced. In the end, we will introduce specific jitter and signaling testing requirements and associated testing methods for high speed communication standards such as PCI Express (PCIe), fibre channel (FC), and Giga Bit Ethernet (GBE)
{"title":"Jitter And Signaling Test For High-Speed Links","authors":"Mike P. Li","doi":"10.1109/CICC.2006.320977","DOIUrl":"https://doi.org/10.1109/CICC.2006.320977","url":null,"abstract":"We reviewed the roles that jitter and signaling plays in a high speed communication link. We then discuss the testing and verification methods for the link components of transmitter, receiver, medium, and reference clock. The latest statistical plus system transfer function based jitter and signaling test methods are introduced. In the end, we will introduce specific jitter and signaling testing requirements and associated testing methods for high speed communication standards such as PCI Express (PCIe), fibre channel (FC), and Giga Bit Ethernet (GBE)","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134104650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.321002
K. Venkataraman, V. Suresh, S. Iyengar, M. Ott, S. R. Kalari, J. Zhi, E. Ruetz, M. Gray, B. Reynov, A. Iqbal
The advent of broadband services requires multi service provisioning platforms (MSPP) to achieve >10Gbps capacity with 1-4 rack unit footprint, power <200W and cost <$10K. Highly integrated SoC using 0.13mu CMOS 19.3times19.3mm die packaged in a 1517 FCBGA affords a unique MSPP solution consisting of 155M-10Gbps SONET/SDH framing, low/high order path processing, grooming, cross-connection up to 22.5Gbps and an embedded processor. A rigorous methodology enabled a production-worthy SoC comprising 9Mgates/14Mbit memory
{"title":"Integrated 155M-10Gbps Framer with 22.5Gbps Low/High Order Cross Connect SoC","authors":"K. Venkataraman, V. Suresh, S. Iyengar, M. Ott, S. R. Kalari, J. Zhi, E. Ruetz, M. Gray, B. Reynov, A. Iqbal","doi":"10.1109/CICC.2006.321002","DOIUrl":"https://doi.org/10.1109/CICC.2006.321002","url":null,"abstract":"The advent of broadband services requires multi service provisioning platforms (MSPP) to achieve >10Gbps capacity with 1-4 rack unit footprint, power <200W and cost <$10K. Highly integrated SoC using 0.13mu CMOS 19.3times19.3mm die packaged in a 1517 FCBGA affords a unique MSPP solution consisting of 155M-10Gbps SONET/SDH framing, low/high order path processing, grooming, cross-connection up to 22.5Gbps and an embedded processor. A rigorous methodology enabled a production-worthy SoC comprising 9Mgates/14Mbit memory","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133810815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320987
Y. Yamagata, H. Shirai, H. Sugimura, S. Arai, T. Wake, Ken Inoue, T. Sakoh, M. Sakao, T. Tanigawa
This paper presents embedded DRAM device technology utilizing stacked MIM(metal-insulator-metal) capacitor. Targeted for high random-access performance as well as low-power data-streaming applications, original structure named "full metal DRAM" has been devised and implemented from 150nm generation. This features reduced parasitic resistance of DRAM cell and fully-compatible CMOS Trs. characteristics with that of leading-edge CMOS. In 90nm generation, ZrO 2 is introduced as capacitor dielectric material for cell size reduction. For the next generation of 55nm, high-k gate dielectric(HfSiON) will be introduced in CMOS platform, which can be effectively exploited for embedded DRAM scaling and performance improvement
{"title":"Device Technology for embedded DRAM utilizing stacked MIM(Metal-Insulator-Metal) Capacitor","authors":"Y. Yamagata, H. Shirai, H. Sugimura, S. Arai, T. Wake, Ken Inoue, T. Sakoh, M. Sakao, T. Tanigawa","doi":"10.1109/CICC.2006.320987","DOIUrl":"https://doi.org/10.1109/CICC.2006.320987","url":null,"abstract":"This paper presents embedded DRAM device technology utilizing stacked MIM(metal-insulator-metal) capacitor. Targeted for high random-access performance as well as low-power data-streaming applications, original structure named \"full metal DRAM\" has been devised and implemented from 150nm generation. This features reduced parasitic resistance of DRAM cell and fully-compatible CMOS Trs. characteristics with that of leading-edge CMOS. In 90nm generation, ZrO 2 is introduced as capacitor dielectric material for cell size reduction. For the next generation of 55nm, high-k gate dielectric(HfSiON) will be introduced in CMOS platform, which can be effectively exploited for embedded DRAM scaling and performance improvement","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132219160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.321014
Mohamed Bouhamame, J. Tourret, Luca Lo Coco, S. Toutain, O. Pasquier
A controllable high voltage DC/DC converter has been designed that can generate an output voltage from 0 to 30V with a 2.8V supply voltage. It is suitable for controlling MEMS and high voltage varicap devices in tunable filters. The proposed DC/DC converter uses a novel approach to decrease the output voltage by cascading two Dickson charge pumps (Dickson, 1976). It is operating with a clock frequency of 16MHz and is built in a 0.25mum Bi-CMOS technology
设计了一种可控高压DC/DC变换器，该变换器在2.8V的供电电压下可产生0 ~ 30V的输出电压。它适用于可调谐滤波器中对MEMS和高压可变电容器件的控制。所提出的DC/DC变换器采用了一种新颖的方法，通过级联两个Dickson电荷泵来降低输出电压(Dickson, 1976)。它的时钟频率为16MHz，采用0.25 μ m Bi-CMOS技术
{"title":"A Fully Integrated DC/DC Converter for Tunable RF Filters","authors":"Mohamed Bouhamame, J. Tourret, Luca Lo Coco, S. Toutain, O. Pasquier","doi":"10.1109/CICC.2006.321014","DOIUrl":"https://doi.org/10.1109/CICC.2006.321014","url":null,"abstract":"A controllable high voltage DC/DC converter has been designed that can generate an output voltage from 0 to 30V with a 2.8V supply voltage. It is suitable for controlling MEMS and high voltage varicap devices in tunable filters. The proposed DC/DC converter uses a novel approach to decrease the output voltage by cascading two Dickson charge pumps (Dickson, 1976). It is operating with a clock frequency of 16MHz and is built in a 0.25mum Bi-CMOS technology","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133909895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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