Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221186
Chung-Yu Wu, C. Chou
A 5-GHz CMOS double-quadrature front-end receiver for Wireless-LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals and an active polyphase filter is designed to reject image signals. It has the advantages of low power dissipation, small chip area, and low sensitivity to parasitic components. Implemented in 0.18 um CMOS technology, the receiver chip can achieve 50.6 dB image-rejection with the power dissipation of 22.4 mW at 1.8-V voltage supply.
提出了一种适用于无线局域网的5ghz CMOS双正交前端接收机。在接收机中，采用一级RLC移相器产生正交射频信号，设计有源多相滤波器抑制图像信号。它具有功耗低、芯片面积小、对寄生元件的灵敏度低等优点。该接收器芯片采用0.18 um CMOS技术，在1.8 v电压下可实现50.6 dB的图像抑制，功耗为22.4 mW。
{"title":"A 5-GHz CMOS double-quadrature receiver for IEEE 802.11a applications","authors":"Chung-Yu Wu, C. Chou","doi":"10.1109/VLSIC.2003.1221186","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221186","url":null,"abstract":"A 5-GHz CMOS double-quadrature front-end receiver for Wireless-LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals and an active polyphase filter is designed to reject image signals. It has the advantages of low power dissipation, small chip area, and low sensitivity to parasitic components. Implemented in 0.18 um CMOS technology, the receiver chip can achieve 50.6 dB image-rejection with the power dissipation of 22.4 mW at 1.8-V voltage supply.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115834041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221183
Ren-Chieh Liu, Chin-Shen Lin, K. Deng, Huei Wang
A 0.5-14-GHz distributed amplifier (DA) using 0.18-/spl mu/m CMOS technology has been presented. It demonstrates the highest gain bandwidth product reported for a CMOS amplifier using a standard Si-based IC process. This DA chip achieves measured results of 10.6/spl plusmn/0.9 dB gain, NF between 3.4 and 5.4 dB with good return losses better than from 0.5 to 14 GHz. The measured output IP3 and P/sub ldB/ are +20 dBm and +10 dBm, respectively, from 2 to 10 GHz.
{"title":"A 0.5-14-GHz 10.6-dB CMOS cascode distributed amplifier","authors":"Ren-Chieh Liu, Chin-Shen Lin, K. Deng, Huei Wang","doi":"10.1109/VLSIC.2003.1221183","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221183","url":null,"abstract":"A 0.5-14-GHz distributed amplifier (DA) using 0.18-/spl mu/m CMOS technology has been presented. It demonstrates the highest gain bandwidth product reported for a CMOS amplifier using a standard Si-based IC process. This DA chip achieves measured results of 10.6/spl plusmn/0.9 dB gain, NF between 3.4 and 5.4 dB with good return losses better than from 0.5 to 14 GHz. The measured output IP3 and P/sub ldB/ are +20 dBm and +10 dBm, respectively, from 2 to 10 GHz.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122515996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221209
I. Nam, Young Jin Kim, Kwyro Lee
RF characteristics of the parasitic vertical NPN bipolar junction transistor (BJT) available in 0.18 /spl mu/m foundry deep n-well CMOS technology are reported for the first time. The experimental results show that the vertical NPN BJT has about 20 of current gain, 7 V of collector-emitter breakdown voltage, 20 V of collector-base breakdown voltage, 40 V of early voltage, 2.3 GHz of cutoff frequency, and 3.5 GHz of maximum oscillation frequency at room temperature. The corner frequency of flicker noise is lower than 4 kHz at 0.5 mA. Double balanced RF mixer using V-NPN shows almost free 1/f noise as well as order of magnitude smaller DC offset with other characteristics comparable with CMOS one and 12 dB flat up to the cutoff frequency, opening the possibility of high performance direct conversion receiver implementation in CMOS technology.
{"title":"Low 1/f noise and DC offset RF mixer for direct conversion receiver using parasitic vertical NPN bipolar transistor in deep n-well CMOS technology","authors":"I. Nam, Young Jin Kim, Kwyro Lee","doi":"10.1109/VLSIC.2003.1221209","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221209","url":null,"abstract":"RF characteristics of the parasitic vertical NPN bipolar junction transistor (BJT) available in 0.18 /spl mu/m foundry deep n-well CMOS technology are reported for the first time. The experimental results show that the vertical NPN BJT has about 20 of current gain, 7 V of collector-emitter breakdown voltage, 20 V of collector-base breakdown voltage, 40 V of early voltage, 2.3 GHz of cutoff frequency, and 3.5 GHz of maximum oscillation frequency at room temperature. The corner frequency of flicker noise is lower than 4 kHz at 0.5 mA. Double balanced RF mixer using V-NPN shows almost free 1/f noise as well as order of magnitude smaller DC offset with other characteristics comparable with CMOS one and 12 dB flat up to the cutoff frequency, opening the possibility of high performance direct conversion receiver implementation in CMOS technology.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121073443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221220
Kenichi Osada, Ken Yamaguchi, Yoshikazu Saitoh, Takuyuki Kawahara
This paper describes an investigation of cosmic-ray-induced multi-cell error (MCE) behavior in SRAMs through device- and circuit-level simulation methods developed on the basis that a parasitic bipolar effect is responsible for such errors. The first demonstration that the maximum number of cell errors per cosmic-ray strike depends on the number of cells between well contacts (Nc) is presented. The results are applied in an error checking and correction (ECC) design guideline for the handling of cosmic-ray-induced multi-cell errors. A new architecture is proposed, in which matching of addresses to memory cells is consideration of the Nc. This architecture reduced soft error rate (SER) for an SRAM fabricated by using 0.13-/spl mu/m CMOS technology by 88%.
{"title":"Cosmic-ray multi-error immunity for SRAM, based on analysis of the parasitic bipolar effect","authors":"Kenichi Osada, Ken Yamaguchi, Yoshikazu Saitoh, Takuyuki Kawahara","doi":"10.1109/VLSIC.2003.1221220","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221220","url":null,"abstract":"This paper describes an investigation of cosmic-ray-induced multi-cell error (MCE) behavior in SRAMs through device- and circuit-level simulation methods developed on the basis that a parasitic bipolar effect is responsible for such errors. The first demonstration that the maximum number of cell errors per cosmic-ray strike depends on the number of cells between well contacts (Nc) is presented. The results are applied in an error checking and correction (ECC) design guideline for the handling of cosmic-ray-induced multi-cell errors. A new architecture is proposed, in which matching of addresses to memory cells is consideration of the Nc. This architecture reduced soft error rate (SER) for an SRAM fabricated by using 0.13-/spl mu/m CMOS technology by 88%.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124773912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221224
Ron Ho, Ken Mai, Mark Horowitz
We present circuits for a high-efficiency low-swing interconnect scheme suitable for the Smart Memories reconfigurable architecture. By using a separate supply, global clocking, and differential signaling, we reduce design complexity; and by using overdrive circuits, equalization techniques, and sense-amplifiers we retain high performance. A testchip built in a 1.8 V 0.18-/spl mu/m technology consumed <1pJ/bit for a 10 mm bus at 1 GHz, a power savings over full-swing signaling of up to 10 x, and demonstrated amplifier input offset voltages of under 100 mV.
提出了一种适用于智能存储器可重构结构的高效低摆幅互连方案。通过使用单独的电源、全局时钟和差分信号，我们降低了设计的复杂性;通过使用超速驱动电路、均衡技术和传感器放大器，我们保持了高性能。采用1.8 V 0.18-/spl mu/m技术的测试芯片，在1ghz下，10mm总线的功耗<1pJ/bit，与全摆幅信号相比，功耗节省高达10倍，并且放大器输入偏置电压低于100 mV。
{"title":"Efficient on-chip global interconnects","authors":"Ron Ho, Ken Mai, Mark Horowitz","doi":"10.1109/VLSIC.2003.1221224","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221224","url":null,"abstract":"We present circuits for a high-efficiency low-swing interconnect scheme suitable for the Smart Memories reconfigurable architecture. By using a separate supply, global clocking, and differential signaling, we reduce design complexity; and by using overdrive circuits, equalization techniques, and sense-amplifiers we retain high performance. A testchip built in a 1.8 V 0.18-/spl mu/m technology consumed <1pJ/bit for a 10 mm bus at 1 GHz, a power savings over full-swing signaling of up to 10 x, and demonstrated amplifier input offset voltages of under 100 mV.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124878408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221207
A. Bette, J. DeBrosse, D. Gogl, H. Hoenigschmid, R. Robertazzi, C. Arndt, D. Braun, D. Casarotto, R. Havreluk, S. Lammers, W. Obermaier, W. Reohr, H. Viehmann, W. Gallagher, G. Muller
A 128 Kb MRAM (Magnetic Random Access Memory) test chip has been fabricated utilizing for the first time a 0.18 /spl mu/m, VDD=1.8 V, logic process technology with Cu backend of line. The presented design uses a 1.4 /spl mu/m/sup 2/ ITIMTJ (1-Transistor/1-Magnetic Tunnel Junction) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5 ns random array read access time and random write operations with <5 ns write pulse width.
{"title":"A high-speed 128 Kbit MRAM core for future universal memory applications","authors":"A. Bette, J. DeBrosse, D. Gogl, H. Hoenigschmid, R. Robertazzi, C. Arndt, D. Braun, D. Casarotto, R. Havreluk, S. Lammers, W. Obermaier, W. Reohr, H. Viehmann, W. Gallagher, G. Muller","doi":"10.1109/VLSIC.2003.1221207","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221207","url":null,"abstract":"A 128 Kb MRAM (Magnetic Random Access Memory) test chip has been fabricated utilizing for the first time a 0.18 /spl mu/m, VDD=1.8 V, logic process technology with Cu backend of line. The presented design uses a 1.4 /spl mu/m/sup 2/ ITIMTJ (1-Transistor/1-Magnetic Tunnel Junction) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5 ns random array read access time and random write operations with <5 ns write pulse width.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128254305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221187
Y. Oike, M. Ikeda, K. Asada
In this paper, we present the first real-time range finder with the capability of VGA (640/spl times/480) resolution based on a light-section method. We propose an adaptive thresholding circuit and column-parallel time-domain approximate ADCs to realize high-speed readout for real-time range finding. Sub-pixel position calculation based on intensity profile by the readout scheme achieves high-accuracy range finding. A column-parallel position detector suppresses redundant data transmission for a real-time measurement system.
{"title":"640/spl times/480 Real-time range finder using high-speed readout scheme and column-parallel position detector","authors":"Y. Oike, M. Ikeda, K. Asada","doi":"10.1109/VLSIC.2003.1221187","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221187","url":null,"abstract":"In this paper, we present the first real-time range finder with the capability of VGA (640/spl times/480) resolution based on a light-section method. We propose an adaptive thresholding circuit and column-parallel time-domain approximate ADCs to realize high-speed readout for real-time range finding. Sub-pixel position calculation based on intensity profile by the readout scheme achieves high-accuracy range finding. A column-parallel position detector suppresses redundant data transmission for a real-time measurement system.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116696897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221188
D. Barrettino, M. Graf, S. Taschini, M. Zimmermann, C. Hagleitner, A. Hierlemann, H. Baltes
A single-chip conductometric gas sensor system fabricated in industrial CMOS-technology with post-CMOS micromachining is presented, which comprises a tin dioxide-covered microhotplate, a digital temperature controller (200-350/spl deg/C/spl plusmn/2/spl deg/C), a logarithmic converter for the tin dioxide resistor and a serial interface. All necessary driving circuitry and A/D conversion units were realized on chip. The chip communication is handled with an I2C digital standard interface. Gas tests evidenced a detection limit below 1 ppm for carbon monoxide.
{"title":"Hotplate-based conductometric monolithic CMOS gas sensor system","authors":"D. Barrettino, M. Graf, S. Taschini, M. Zimmermann, C. Hagleitner, A. Hierlemann, H. Baltes","doi":"10.1109/VLSIC.2003.1221188","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221188","url":null,"abstract":"A single-chip conductometric gas sensor system fabricated in industrial CMOS-technology with post-CMOS micromachining is presented, which comprises a tin dioxide-covered microhotplate, a digital temperature controller (200-350/spl deg/C/spl plusmn/2/spl deg/C), a logarithmic converter for the tin dioxide resistor and a serial interface. All necessary driving circuitry and A/D conversion units were realized on chip. The chip communication is handled with an I2C digital standard interface. Gas tests evidenced a detection limit below 1 ppm for carbon monoxide.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133949838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221216
T. Shimada, H. Notani, Y. Nakase, H. Makino, S. Iwade
We proposed a push-pull output buffer that maintains the data transmission rate for lower supply voltages. It operates at an internal supply voltage (VDD) of 0.7-1.6 V and an interface supply voltage (VDDX) of 1.0-3.6 V. In low VDDX operation, the output buffer utilizes parasitic bipolar transistors instead of MOS transistors to maintain drivability. Furthermore forward body bias control is provided for the level converter in low VDD operation. We fabricated a test chip with a standard 0.15 /spl mu/m CMOS process. Measurement results indicate that the proposed output buffer achieves 200 Mbps operation at VDD of 0.7 V and VDDX of 1.0 V.
{"title":"A wide range 1.0 V-3.6 V 200 Mbps, push-pull output buffer using parasitic bipolar transistors","authors":"T. Shimada, H. Notani, Y. Nakase, H. Makino, S. Iwade","doi":"10.1109/VLSIC.2003.1221216","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221216","url":null,"abstract":"We proposed a push-pull output buffer that maintains the data transmission rate for lower supply voltages. It operates at an internal supply voltage (VDD) of 0.7-1.6 V and an interface supply voltage (VDDX) of 1.0-3.6 V. In low VDDX operation, the output buffer utilizes parasitic bipolar transistors instead of MOS transistors to maintain drivability. Furthermore forward body bias control is provided for the level converter in low VDD operation. We fabricated a test chip with a standard 0.15 /spl mu/m CMOS process. Measurement results indicate that the proposed output buffer achieves 200 Mbps operation at VDD of 0.7 V and VDDX of 1.0 V.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130380421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221230
J. Sim, Young-Gu Gang, K. Lim, Joong-Yong Choi, Sang-Keun Kwak, K. Chun, Jei-Hwan Yoo, D.I. Seo, Sooin Cho
A 256 Mb SDRAM is implemented with a 0.12 /spl mu/m technology to verify two circuit schemes suitable for mobile application. A charge transferred presensing is proposed to achieve fast low-voltage sensing and robust operation. With a precharge disabler for productivity, new negative word-line scheme is also proposed to bypass the majority of discharging current to VSS without switching control.
{"title":"Charge-transferred presensing and efficiently precharged negative word-line schemes for low-voltage DRAMs","authors":"J. Sim, Young-Gu Gang, K. Lim, Joong-Yong Choi, Sang-Keun Kwak, K. Chun, Jei-Hwan Yoo, D.I. Seo, Sooin Cho","doi":"10.1109/VLSIC.2003.1221230","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221230","url":null,"abstract":"A 256 Mb SDRAM is implemented with a 0.12 /spl mu/m technology to verify two circuit schemes suitable for mobile application. A charge transferred presensing is proposed to achieve fast low-voltage sensing and robust operation. With a precharge disabler for productivity, new negative word-line scheme is also proposed to bypass the majority of discharging current to VSS without switching control.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122181683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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