Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221169
B. Ji, S. Munetoh, Chorng-Lii Hwang, M. Wordeman, T. Kirihata
This paper describes a novel random access memory system. The system is based on a destructive-read memory buffered by a destructive-read memory cache for hidden write back. SRAM comparable random access cycle time (tRC) is achieved, as tRC of the architecture is limited only by the destructive-read time of the memory array. By using a DRAM array as cache, the silicon area is reduced by about 25% from SRAM-cache system. Write back algorithms have been proved by mathematical models, and confirmed by simulations.
{"title":"Destructive-read random access memory system buffered with destructive-read memory cache for SoC applications","authors":"B. Ji, S. Munetoh, Chorng-Lii Hwang, M. Wordeman, T. Kirihata","doi":"10.1109/VLSIC.2003.1221169","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221169","url":null,"abstract":"This paper describes a novel random access memory system. The system is based on a destructive-read memory buffered by a destructive-read memory cache for hidden write back. SRAM comparable random access cycle time (tRC) is achieved, as tRC of the architecture is limited only by the destructive-read time of the memory array. By using a DRAM array as cache, the silicon area is reduced by about 25% from SRAM-cache system. Write back algorithms have been proved by mathematical models, and confirmed by simulations.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126924291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221210
E. Klumperink, S. Louwsma, G. Wienk, B. Nauta
A new CMOS mixer topology can operate at low supply voltages by using switches connected only to the supplies. Mixing is achieved exploiting two cross-coupled transconductors, which are alternatingly activated by the switches. A down conversion mixer prototype with 12 dB conversion gain was designed and realized in standard 0.18 /spl mu/m CMOS. It achieves satisfactory mixer performance up to 4 GHz, at a supply voltage of 1 Volt. Moreover, the mixer topology features a fundamental high frequency noise figure benefit.
{"title":"A 1 Volt switched transconductor mixer in 0.18 /spl mu/m CMOS","authors":"E. Klumperink, S. Louwsma, G. Wienk, B. Nauta","doi":"10.1109/VLSIC.2003.1221210","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221210","url":null,"abstract":"A new CMOS mixer topology can operate at low supply voltages by using switches connected only to the supplies. Mixing is achieved exploiting two cross-coupled transconductors, which are alternatingly activated by the switches. A down conversion mixer prototype with 12 dB conversion gain was designed and realized in standard 0.18 /spl mu/m CMOS. It achieves satisfactory mixer performance up to 4 GHz, at a supply voltage of 1 Volt. Moreover, the mixer topology features a fundamental high frequency noise figure benefit.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121895990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221150
E. Fayneh, E. Knoll
This clock generation and distribution scheme enables Intel's first mobile-specific micro-architecture of Banias microprocessor. It employs four phase-locked loops, three of them cascaded, to generate the required clock frequencies, provide low skew and jitter and support the next-generation Intel SpeedStep/spl reg/ technology. The core clock distribution is implemented as two grids with an active continuous de-skewing mechanism. The debug capabilities of this clocking scheme provide easy observability and testing, enabling rapid time to market.
{"title":"Clock generation and distribution for intel Banias mobile microprocessor","authors":"E. Fayneh, E. Knoll","doi":"10.1109/VLSIC.2003.1221150","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221150","url":null,"abstract":"This clock generation and distribution scheme enables Intel's first mobile-specific micro-architecture of Banias microprocessor. It employs four phase-locked loops, three of them cascaded, to generate the required clock frequencies, provide low skew and jitter and support the next-generation Intel SpeedStep/spl reg/ technology. The core clock distribution is implemented as two grids with an active continuous de-skewing mechanism. The debug capabilities of this clocking scheme provide easy observability and testing, enabling rapid time to market.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131487566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221147
M. Lundstrom
Examines CMOS technology at the scaling limit and the role that new, molecular devices may play in future electronics systems. Advanced simulation techniques that capture quantum effects and atomistic structure allow realistic projections of ultimate CMOS. The same techniques allow us to explore unconventional devices such as carbon nanotube FETs, two-terminal molecular devices, and spintronic devices. The role of such devices in future heterogeneous systems will be considered. The talk will conclude with some general thoughts on the important role of the VLSI design community for electronics beyond the gigascale.
{"title":"A top-down look at bottom-up electronics","authors":"M. Lundstrom","doi":"10.1109/VLSIC.2003.1221147","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221147","url":null,"abstract":"Examines CMOS technology at the scaling limit and the role that new, molecular devices may play in future electronics systems. Advanced simulation techniques that capture quantum effects and atomistic structure allow realistic projections of ultimate CMOS. The same techniques allow us to explore unconventional devices such as carbon nanotube FETs, two-terminal molecular devices, and spintronic devices. The role of such devices in future heterogeneous systems will be considered. The talk will conclude with some general thoughts on the important role of the VLSI design community for electronics beyond the gigascale.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129501659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221217
K. Nii, Y. Tenoh, T. Yoshizawa, S. Imaoka, Y. Tsukamoto, Y. Yamagami, T. Suzuki, A. Shibayama, H. Makino, S. Iwade
In sub 100 nm generation, gate tunneling leak current increases and dominates total standby leak current of LSI based on decreasing gate oxide thickness. We propose reducing gate leak current in SRAM using Local DC Level Control (LDLC) and an Automatic Gate Leakage Suppression Driver to reduce gate leak current in the peripheral circuit. We designed and fabricated a 32 KB 1-port SRAM using 90 nm CMOS technology. The 6T-SRAM-cell size is 1.25 /spl mu/m/sup 2/. Evaluation showed that the standby current of 32 KB SRAM is 1.2 /spl mu/A at 1.2 V and room temperature. It is reduced to 7.5% of conventional SRAM.
{"title":"A 90 nm low power 32 K-byte embedded SRAM with gate leakage suppression circuit for mobile applications","authors":"K. Nii, Y. Tenoh, T. Yoshizawa, S. Imaoka, Y. Tsukamoto, Y. Yamagami, T. Suzuki, A. Shibayama, H. Makino, S. Iwade","doi":"10.1109/VLSIC.2003.1221217","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221217","url":null,"abstract":"In sub 100 nm generation, gate tunneling leak current increases and dominates total standby leak current of LSI based on decreasing gate oxide thickness. We propose reducing gate leak current in SRAM using Local DC Level Control (LDLC) and an Automatic Gate Leakage Suppression Driver to reduce gate leak current in the peripheral circuit. We designed and fabricated a 32 KB 1-port SRAM using 90 nm CMOS technology. The 6T-SRAM-cell size is 1.25 /spl mu/m/sup 2/. Evaluation showed that the standby current of 32 KB SRAM is 1.2 /spl mu/A at 1.2 V and room temperature. It is reduced to 7.5% of conventional SRAM.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130991003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221165
Kye-Shin Lee, F. Maloberti
A 1.8 V, 1 MS/s, 85 dB SNR 2+2 mash /spl Sigma//spl Delta/ modulator with /spl plusmn/0.9 V reference voltage is realized by using the swing reduction structure. This structure limits the output swing of all the integrators within half the reference voltage. Thus, low voltage and high speed operation is possible with even high reference voltage without degrading the performance of the modulator. The circuit is fabricated in CMOS 0.35 /spl mu/m process with chip size of 2.5/spl times/2.5 mm/sup 2/.
{"title":"A 1.8 V, 1 MS/s, 85 dB SNR 2+2 mash /spl Sigma//spl Delta/ modulator with /spl plusmn/0.9 V reference voltage","authors":"Kye-Shin Lee, F. Maloberti","doi":"10.1109/VLSIC.2003.1221165","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221165","url":null,"abstract":"A 1.8 V, 1 MS/s, 85 dB SNR 2+2 mash /spl Sigma//spl Delta/ modulator with /spl plusmn/0.9 V reference voltage is realized by using the swing reduction structure. This structure limits the output swing of all the integrators within half the reference voltage. Thus, low voltage and high speed operation is possible with even high reference voltage without degrading the performance of the modulator. The circuit is fabricated in CMOS 0.35 /spl mu/m process with chip size of 2.5/spl times/2.5 mm/sup 2/.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127087138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221190
I. Hehemann, W. Brockherde, H. Hofmann, A. Kemna, B. Hosticka
In this paper a new fully integrated detector architecture for pick-up units in optical storage systems is presented. Apart from a special diode constellation for data recovery it features a 5/spl times/5 diode matrix for determination of the average spatial light power distribution across the detector. The chip, fabricated in a standard 0.6 /spl mu/m CMOS process, operates at a 3.3 V power supply and occupies 1.78/spl times/1.58 mm/sup 2/. It includes six high frequency readout and one low frequency readout paths.
本文提出了一种用于光存储系统中拾取单元的全集成检测器结构。除了用于数据恢复的特殊二极管星座外，它还具有5/spl倍/5二极管矩阵，用于确定探测器的平均空间光功率分布。该芯片采用标准的0.6 /spl μ m CMOS工艺制造，工作在3.3 V电源下，占用1.78/spl次/1.58 mm/sup 2/。它包括六个高频读出路径和一个低频读出路径。
{"title":"A new single chip optical CMOS detector for next generation optical storage systems","authors":"I. Hehemann, W. Brockherde, H. Hofmann, A. Kemna, B. Hosticka","doi":"10.1109/VLSIC.2003.1221190","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221190","url":null,"abstract":"In this paper a new fully integrated detector architecture for pick-up units in optical storage systems is presented. Apart from a special diode constellation for data recovery it features a 5/spl times/5 diode matrix for determination of the average spatial light power distribution across the detector. The chip, fabricated in a standard 0.6 /spl mu/m CMOS process, operates at a 3.3 V power supply and occupies 1.78/spl times/1.58 mm/sup 2/. It includes six high frequency readout and one low frequency readout paths.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121225112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221151
Charles E. Dike, nasser. a. kurd, Priyadarsan Patra, J. Barkatullah, nasser. a. kurd, J. Barkatullah
Unintentional clock skews between clock domains represent an increasing and costly overhead in high-performance VLSI chips. We describe a novel yet easy-to-implement design that reduces skew between local clock domains dynamically or statically by sensing clock-delay differences and then tuning the clock of each domain relative to its neighbors. Lowering local clock skew is accomplished without compromising worst-case global skew.
{"title":"A design for digital, dynamic clock deskew","authors":"Charles E. Dike, nasser. a. kurd, Priyadarsan Patra, J. Barkatullah, nasser. a. kurd, J. Barkatullah","doi":"10.1109/VLSIC.2003.1221151","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221151","url":null,"abstract":"Unintentional clock skews between clock domains represent an increasing and costly overhead in high-performance VLSI chips. We describe a novel yet easy-to-implement design that reduces skew between local clock domains dynamically or statically by sensing clock-delay differences and then tuning the clock of each domain relative to its neighbors. Lowering local clock skew is accomplished without compromising worst-case global skew.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122454373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221152
T. Ohnakado, S. Yamakawa, T. Murakami, A. Furukawa, E. Taniguchi, H. Ueda, N. Suematsu, T. Oomori
This paper reports for the first time an over-20 dBm power-handling 5 GHz transmit/receive (T/R) CMOS switch. The Depletion-layer-Extended Transistor (DET), which possesses high effective substrate resistance, enables the voltage division effect of the stacked transistor configuration to work in CMOS, thus realizing this high power-handling capability. Furthermore, despite insertion-loss (I/sub L/) degradation due to double on-resistance with the stacked transistor configuration, a receive-mode I/sub L/ (I/sub L/@RX) of as low as 1.44 dB at 5 GHz is accomplished with the benefit of the I/sub L/ improvement effects in the DET, in addition to a very low transmit-mode I/sub L/ (I/sub L/@TX) of 0.95 dB at 5 GHz.
{"title":"21.5 dBm power-handling 5 GHz transmit/receive CMOS switch realized by voltage division effect of stacked transistor configuration with Depletion-layer-Extended Transistors (DETs)","authors":"T. Ohnakado, S. Yamakawa, T. Murakami, A. Furukawa, E. Taniguchi, H. Ueda, N. Suematsu, T. Oomori","doi":"10.1109/VLSIC.2003.1221152","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221152","url":null,"abstract":"This paper reports for the first time an over-20 dBm power-handling 5 GHz transmit/receive (T/R) CMOS switch. The Depletion-layer-Extended Transistor (DET), which possesses high effective substrate resistance, enables the voltage division effect of the stacked transistor configuration to work in CMOS, thus realizing this high power-handling capability. Furthermore, despite insertion-loss (I/sub L/) degradation due to double on-resistance with the stacked transistor configuration, a receive-mode I/sub L/ (I/sub L/@RX) of as low as 1.44 dB at 5 GHz is accomplished with the benefit of the I/sub L/ improvement effects in the DET, in addition to a very low transmit-mode I/sub L/ (I/sub L/@TX) of 0.95 dB at 5 GHz.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123015893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221199
S. Verma, Junfeng Xu, T. Lee
A frequency-synthesis technique which extracts the N/sup th/ harmonic from an N-stage oscillator is presented. The maximum achievable voltage swing from such an oscillator is estimated. To study this technique, a multiply-by-3 circuit with two 180/spl deg/-coupled, single-ended three-stage ring oscillators has been fabricated in 0.24 /spl mu/m CMOS, designed to work in the 902-928 MHz ISM band (US and Canada). It provides two outputs: one at the normal operating frequency of the oscillator, and another at three times that frequency. The circuit can work at voltages as low as 1.3 V, while consuming 210 /spl mu/A of current.
{"title":"A multiply-by-3 coupled-ring oscillator for low-power frequency synthesis","authors":"S. Verma, Junfeng Xu, T. Lee","doi":"10.1109/VLSIC.2003.1221199","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221199","url":null,"abstract":"A frequency-synthesis technique which extracts the N/sup th/ harmonic from an N-stage oscillator is presented. The maximum achievable voltage swing from such an oscillator is estimated. To study this technique, a multiply-by-3 circuit with two 180/spl deg/-coupled, single-ended three-stage ring oscillators has been fabricated in 0.24 /spl mu/m CMOS, designed to work in the 902-928 MHz ISM band (US and Canada). It provides two outputs: one at the normal operating frequency of the oscillator, and another at three times that frequency. The circuit can work at voltages as low as 1.3 V, while consuming 210 /spl mu/A of current.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121508472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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