Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221196
Hsiang-Hui Chang, C. Sun, Shen-Iuan Liu
The low jitter Butterworth delay-locked loops (DLLs) are presented in this paper. The proposed Butterworth DLLs can suppress both the jitters generated by the input noise and the voltage-controlled delay line (VCDL) noise without stability considerations. Theoretically, the proposed Butterworth 2/sup nd/-order DLL and 3/sup rd/-order one could reduce the rms jitter due to the VCDL by a factor of /spl radic/2 and 2, respectively. In addition, a technique called dynamic bandwidth-adjusting scheme (DBAS) is adopted to shorten the lock time without compromising the jitter performance. The conventional DLL and the proposed ones are simultaneously fabricated at the same die in a CMOS 0.35-um one-poly four-metal process. Compared with the conventional DLL, the measured rms jitters of the proposed DLLs can be improved by a factor of 1.40 and 1.95, respectively, with an input frequency of 125 MHz. The maximum power consumption of the proposed DLLs is 32 mW.
{"title":"Low jitter Butterworth delay-locked loops","authors":"Hsiang-Hui Chang, C. Sun, Shen-Iuan Liu","doi":"10.1109/VLSIC.2003.1221196","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221196","url":null,"abstract":"The low jitter Butterworth delay-locked loops (DLLs) are presented in this paper. The proposed Butterworth DLLs can suppress both the jitters generated by the input noise and the voltage-controlled delay line (VCDL) noise without stability considerations. Theoretically, the proposed Butterworth 2/sup nd/-order DLL and 3/sup rd/-order one could reduce the rms jitter due to the VCDL by a factor of /spl radic/2 and 2, respectively. In addition, a technique called dynamic bandwidth-adjusting scheme (DBAS) is adopted to shorten the lock time without compromising the jitter performance. The conventional DLL and the proposed ones are simultaneously fabricated at the same die in a CMOS 0.35-um one-poly four-metal process. Compared with the conventional DLL, the measured rms jitters of the proposed DLLs can be improved by a factor of 1.40 and 1.95, respectively, with an input frequency of 125 MHz. The maximum power consumption of the proposed DLLs is 32 mW.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132376681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221179
M. Ugajin, A. Yamagishi, J. Kodate, M. Harada, T. Tsukahara
A Bluetooth RF transceiver in 0.2-/spl mu/m CMOS/SOI achieves 1-V operation and paves the way for further system-size reduction by using a small NiH battery. The transceiver integrates a T/R switch, an image-reject mixer, a quadrature demodulator, gm-C filters, an LC-tank voltage-controlled oscillator, a PLL, and a power amplifier. The phase shifter in the quadrature demodulator is tuned dynamically to deal with carrier-frequency drift. A gm cell in the filters uses depletion-mode PMOS transistors and has a folded structure. The transceiver shows -77-dBm sensitivity at 0.1% BER.
{"title":"A 1-V CMOS/SOI bluetooth RF transceiver for compact mobile applications","authors":"M. Ugajin, A. Yamagishi, J. Kodate, M. Harada, T. Tsukahara","doi":"10.1109/VLSIC.2003.1221179","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221179","url":null,"abstract":"A Bluetooth RF transceiver in 0.2-/spl mu/m CMOS/SOI achieves 1-V operation and paves the way for further system-size reduction by using a small NiH battery. The transceiver integrates a T/R switch, an image-reject mixer, a quadrature demodulator, gm-C filters, an LC-tank voltage-controlled oscillator, a PLL, and a power amplifier. The phase shifter in the quadrature demodulator is tuned dynamically to deal with carrier-frequency drift. A gm cell in the filters uses depletion-mode PMOS transistors and has a folded structure. The transceiver shows -77-dBm sensitivity at 0.1% BER.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130039507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221149
E. Takahashi, Y. Kasai, M. Murakawa, T. Higuchi
A post-silicon clock timing adjustment architecture utilizing genetic algorithms (GA) is proposed, which has three advantages: (1) enhanced clock frequency leading to improved operating yields, (2) lower power supply voltages while maintaining operating yield, and (3) reductions in design times. Experiments with two different developed LSI chips and a design experiment demonstrated these advantages with a clock frequency enhancement of 25% (max), a power supply voltage reduction of 33%, and 21% shorter design times.
{"title":"A post-silicon clock timing adjustment using genetic algorithms","authors":"E. Takahashi, Y. Kasai, M. Murakawa, T. Higuchi","doi":"10.1109/VLSIC.2003.1221149","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221149","url":null,"abstract":"A post-silicon clock timing adjustment architecture utilizing genetic algorithms (GA) is proposed, which has three advantages: (1) enhanced clock frequency leading to improved operating yields, (2) lower power supply voltages while maintaining operating yield, and (3) reductions in design times. Experiments with two different developed LSI chips and a design experiment demonstrated these advantages with a clock frequency enhancement of 25% (max), a power supply voltage reduction of 33%, and 21% shorter design times.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134133766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221222
Cheng-Chung Hsu, Jieh-Tsorng Wu
A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 /spl mu/m CMOS technology, the SHA achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp output at 100 MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm/sup 2/ and dissipates 33 mW from a single 2.5 V supply.
{"title":"A CMOS 33-mW 100-MHz 80-dB SFDR sample-and-hold amplifier","authors":"Cheng-Chung Hsu, Jieh-Tsorng Wu","doi":"10.1109/VLSIC.2003.1221222","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221222","url":null,"abstract":"A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 /spl mu/m CMOS technology, the SHA achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp output at 100 MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm/sup 2/ and dissipates 33 mW from a single 2.5 V supply.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114959493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221219
K. Zhang, U. Bhattacharya, L. Ma, Y. Ng, B. Zheng, M. Bohr, S. Thompson
A 50 Mb SRAM chip is designed and fabricated on an industry leading 90 nm CMOS technology that features a 1 /spl mu/m/sup 2/ SRAM cell and 50 nm gate length transistors with strained silicon. The SRAM chip is formed with 100/spl times/512 Kb subarrays that have 2.5 GHz nominal operating frequency, 75% area efficiency, and fully synchronized internal timing along with efficient local power-down feature. And the design can be easily re-configured to form large high-density on-die cache memory for high-speed logic applications such as CPUs.
{"title":"A fully synchronized, pipelined, and re-configurable 50 Mb SRAM on 90 nm CMOS technology for logic applications","authors":"K. Zhang, U. Bhattacharya, L. Ma, Y. Ng, B. Zheng, M. Bohr, S. Thompson","doi":"10.1109/VLSIC.2003.1221219","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221219","url":null,"abstract":"A 50 Mb SRAM chip is designed and fabricated on an industry leading 90 nm CMOS technology that features a 1 /spl mu/m/sup 2/ SRAM cell and 50 nm gate length transistors with strained silicon. The SRAM chip is formed with 100/spl times/512 Kb subarrays that have 2.5 GHz nominal operating frequency, 75% area efficiency, and fully synchronized internal timing along with efficient local power-down feature. And the design can be easily re-configured to form large high-density on-die cache memory for high-speed logic applications such as CPUs.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116167121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221191
K. Oikawa, D. Takashima, S. Shiratake, K. Hoya, H. Joachim
This paper proposes the new bitline/plateline operation scheme for 32 Mb chainFeRAM, which overcomes these two problems and also overcomes the problem of large array current due to the grounded bitline precharge scheme used for FeRAM.
{"title":"Bitline/plateline reference-level-precharge scheme for high-density chainFeRAM","authors":"K. Oikawa, D. Takashima, S. Shiratake, K. Hoya, H. Joachim","doi":"10.1109/VLSIC.2003.1221191","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221191","url":null,"abstract":"This paper proposes the new bitline/plateline operation scheme for 32 Mb chainFeRAM, which overcomes these two problems and also overcomes the problem of large array current due to the grounded bitline precharge scheme used for FeRAM.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129022084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221212
B. Zeydel, V. Oklobdzija, S. Mathew, R. Krishnamurthy, S. Borkar
This paper describes a static 16/spl times/16-bit 2's complement wireless baseband multiplier testchip in 1.2 V, 90 nm dual-Vt CMOS technology. One-hot Booth encoding, sum/delay difference optimized 3:2 compressor tree, and signal-profile optimized final adder schemes are employed to achieve 1 GHz, 22 mW operation at 1.2 V, scalable to 500 MHz, 3 mW at 0.8 V.
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221154
T. Tsang, M. El-Gamal
A structure that extends the tuning range of MEMS capacitors by at least a factor of eight, compared to recently reported devices fabricated in the same polysilicon surface micromachining MUMPs process, is proposed. A 0.2 pF capacitor has a 325% tuning range, and a Q-factor of 90 at 2.4 GHz. A variation of the same structure has a 0.6 pF capacitance and a 433% tuning range, compared to 238% and 253% for state-of-the-art MEMS and CMOS devices, respectively. The self-resonance frequencies of both devices are beyond 4 GHz.
{"title":"Very wide tuning range micro-electromechanical capacitors in the MUMPs process for RF applications","authors":"T. Tsang, M. El-Gamal","doi":"10.1109/VLSIC.2003.1221154","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221154","url":null,"abstract":"A structure that extends the tuning range of MEMS capacitors by at least a factor of eight, compared to recently reported devices fabricated in the same polysilicon surface micromachining MUMPs process, is proposed. A 0.2 pF capacitor has a 325% tuning range, and a Q-factor of 90 at 2.4 GHz. A variation of the same structure has a 0.6 pF capacitance and a 433% tuning range, compared to 238% and 253% for state-of-the-art MEMS and CMOS devices, respectively. The self-resonance frequencies of both devices are beyond 4 GHz.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126438968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We have developed a 5000 ppm spread spectrum Serializer/Deserializer (SerDes) physical layer (PHY) chip compliant with Serial AT Attachment (ATA). The chip was fabricated with a 0.15 /spl mu/m 1.5 V CMOS process and includes a self-running spread spectrum carrier generator to provide both transmit and receive block, a self-running phase interpolator to recover the +/-5000 ppm spread spectrum receive (RX) clock and data.
我们开发了一个5000 ppm的扩频序列化/反序列化(SerDes)物理层(PHY)芯片，符合串行AT附件(ATA)。该芯片采用0.15 /spl mu/m 1.5 V CMOS工艺制造，包括一个自运行扩频载波发生器，提供发射和接收块，一个自运行相位插补器，恢复+/-5000 ppm扩频接收(RX)时钟和数据。
{"title":"3 Gbps, 5000 ppm spread spectrum SerDes PHY with frequency tracking phase interpolator for serial ATA","authors":"Morishige Aoyama, Kazuo Ogasawara, Mitsutoshi Sugawara, Terukazu Ishibashi, Takashi Ishibashi, S. Shimoyama, Kouichi Yamaguchi, Tomonori Yanagita, Toshihiro Noma","doi":"10.1109/VLSIC.2003.1221175","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221175","url":null,"abstract":"We have developed a 5000 ppm spread spectrum Serializer/Deserializer (SerDes) physical layer (PHY) chip compliant with Serial AT Attachment (ATA). The chip was fabricated with a 0.15 /spl mu/m 1.5 V CMOS process and includes a self-running spread spectrum carrier generator to provide both transmit and receive block, a self-running phase interpolator to recover the +/-5000 ppm spread spectrum receive (RX) clock and data.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121261058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221226
T. Ohkawa, T. Nozawa, M. Fujibayashi, N. Miyamoto, K. Leo, S. Kita, K. Kotani, T. Ohmi
A dynamically reconfigurable logic array, i.e., the Flexible Processor, suitable for single chip emulation system is developed. It demonstrates the sequential execution of sub-circuits divided from original circuit, by newly developed Temporal Communication Module (TCM). In order to accelerate emulation speed, a logic element, which can reduce configuration data by 30% as compared to conventional Look-Up-Table, is implemented. The chip (3.9/spl times/3.9 mm/sup 2/) fabricated with 0.6 /spl mu/m CMOS technology operates at 33 MHz with 5.0 V power supply.
{"title":"The Flexible Processor-dynamically reconfigurable logic array for personal-use emulation system","authors":"T. Ohkawa, T. Nozawa, M. Fujibayashi, N. Miyamoto, K. Leo, S. Kita, K. Kotani, T. Ohmi","doi":"10.1109/VLSIC.2003.1221226","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221226","url":null,"abstract":"A dynamically reconfigurable logic array, i.e., the Flexible Processor, suitable for single chip emulation system is developed. It demonstrates the sequential execution of sub-circuits divided from original circuit, by newly developed Temporal Communication Module (TCM). In order to accelerate emulation speed, a logic element, which can reduce configuration data by 30% as compared to conventional Look-Up-Table, is implemented. The chip (3.9/spl times/3.9 mm/sup 2/) fabricated with 0.6 /spl mu/m CMOS technology operates at 33 MHz with 5.0 V power supply.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"5 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114011053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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