Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221227
Jong-Tae Kwak, Chang-Ki Kwon, Kwan-Weon Kim, Seong-Hoon Lee, J. Kih
A low cost high performance register-controlled digital delay-locked loop (DLL) that has novel resolution-enhancing structure with inherent duty cycle correction capability was developed for 1 Gbps/spl times/32 DDR SDRAM. Experimental results in a 0.13 /spl mu/m 4 M/spl times/32 DDR SDRAM show <25 ps peak-to-peak jitter with quiet supply,
{"title":"A low cost high performance register-controlled digital DLL for 1 Gbps/spl times/32 DDR SDRAM","authors":"Jong-Tae Kwak, Chang-Ki Kwon, Kwan-Weon Kim, Seong-Hoon Lee, J. Kih","doi":"10.1109/VLSIC.2003.1221227","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221227","url":null,"abstract":"A low cost high performance register-controlled digital delay-locked loop (DLL) that has novel resolution-enhancing structure with inherent duty cycle correction capability was developed for 1 Gbps/spl times/32 DDR SDRAM. Experimental results in a 0.13 /spl mu/m 4 M/spl times/32 DDR SDRAM show <25 ps peak-to-peak jitter with quiet supply, </spl plusmn/2% duty correction from external duty error of /spl plusmn/7%, <150 cycle lock-time, 24 mW at 1.8 V/400 MHz, 60 mW at 2.5 V/500 MHz, and a wide locking range from 66 MHz to over 500 MHz.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134118852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221173
K.L. Wong, M. Mansuri, H. Hatamkhani, C. Yang
This paper describes a 3.6-Gbps 27-mW transceiver for chip-to-chip applications. A novel data receiving and timing recovery technique are presented with very low power penalties while maintaining high signal integrity. The input comparator filters noise with built-in bandwidth control and digital offset compensation while consuming 300 uW. Static phase offset introduced onto the charge-pump permits phase recovery with no additional power. The entire design occupies 0.2 mm/sup 2/ in a 0.18-/spl mu/m 1.8-V CMOS technology.
本文介绍了一种用于片对片应用的3.6 gbps 27mw收发器。提出了一种新的数据接收和定时恢复技术，在保持高信号完整性的同时，功耗损失很小。输入比较器通过内置带宽控制和数字偏移补偿过滤噪声，同时消耗300 uW。引入电荷泵的静态相位偏移允许相位恢复，而不需要额外的功率。整个设计占地0.2 mm/sup / /，采用0.18-/spl mu/m的1.8 v CMOS技术。
{"title":"A 27-mW 3.6-Gb/s I/O transceiver","authors":"K.L. Wong, M. Mansuri, H. Hatamkhani, C. Yang","doi":"10.1109/VLSIC.2003.1221173","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221173","url":null,"abstract":"This paper describes a 3.6-Gbps 27-mW transceiver for chip-to-chip applications. A novel data receiving and timing recovery technique are presented with very low power penalties while maintaining high signal integrity. The input comparator filters noise with built-in bandwidth control and digital offset compensation while consuming 300 uW. Static phase offset introduced onto the charge-pump permits phase recovery with no additional power. The entire design occupies 0.2 mm/sup 2/ in a 0.18-/spl mu/m 1.8-V CMOS technology.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130490155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221180
W. Hioe, K. Maio, T. Ooshima, Y. Shibahara, T. Doi
Two circuits for improving the performance of a Bluetooth CMOS RFIC are described. A RF amplifier gain calibration circuit uses a dummy amplifier to calibrate voltage gain and output voltage swing. The dummy amplifier's and a target RF amplifier share the bias circuit, thereby allowing accurate RF gain control against temperature, bias and process variations. A 0.18 /spl mu/m CMOS calibration circuit achieved gain control within +/-0.5 dB. The second circuit, an interleafed multi-stage filter and IF amplifier for use in a low-IF receiver, has an AGC circuit with a novel feedforward control that allows rapid convergence of the amplifier gain. When applied to a Bluetooth signal, convergence was achieved within 5 /spl mu/s even in the worst case blocking signal condition.
{"title":"Gain calibration and feedforward automatic gain control for CMOS radio-frequency ICs","authors":"W. Hioe, K. Maio, T. Ooshima, Y. Shibahara, T. Doi","doi":"10.1109/VLSIC.2003.1221180","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221180","url":null,"abstract":"Two circuits for improving the performance of a Bluetooth CMOS RFIC are described. A RF amplifier gain calibration circuit uses a dummy amplifier to calibrate voltage gain and output voltage swing. The dummy amplifier's and a target RF amplifier share the bias circuit, thereby allowing accurate RF gain control against temperature, bias and process variations. A 0.18 /spl mu/m CMOS calibration circuit achieved gain control within +/-0.5 dB. The second circuit, an interleafed multi-stage filter and IF amplifier for use in a low-IF receiver, has an AGC circuit with a novel feedforward control that allows rapid convergence of the amplifier gain. When applied to a Bluetooth signal, convergence was achieved within 5 /spl mu/s even in the worst case blocking signal condition.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134560650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221189
Akio Tanaka, Y. Tanaka, T. Endoh, K. Okuyama, K. Kawano
We propose a non-uniformity correction scheme that employs analog buses connecting readout channels to correct the variation of the bias current in uncooled infrared detectors prior to amplification. One analog voltage is selected from an analog bus to adjust the bias voltage of the detectors. We have fabricated 320/spl times/240-pixels sensor with 160 readout channels by using two 16-level analog buses. The variation in the bias current for this sensor decreased to 1/38 (5.2-bit), which helps to improve the sensor's temperature stability. An application of this approach in a flush ADC is also discussed.
{"title":"A non-uniformity correction scheme using multiple analog buses for an uncooled infrared sensor","authors":"Akio Tanaka, Y. Tanaka, T. Endoh, K. Okuyama, K. Kawano","doi":"10.1109/VLSIC.2003.1221189","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221189","url":null,"abstract":"We propose a non-uniformity correction scheme that employs analog buses connecting readout channels to correct the variation of the bias current in uncooled infrared detectors prior to amplification. One analog voltage is selected from an analog bus to adjust the bias voltage of the detectors. We have fabricated 320/spl times/240-pixels sensor with 160 readout channels by using two 16-level analog buses. The variation in the bias current for this sensor decreased to 1/38 (5.2-bit), which helps to improve the sensor's temperature stability. An application of this approach in a flush ADC is also discussed.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129804170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221148
S. Tam, U. Desai, R. Limaye
The clock generation and distribution system for the third generation Itanium/spl reg/ processor operates at 1.5 GHz with a skew of 24 ps. Clock optimization fuses enable post-silicon speed path balancing for higher performance.
{"title":"Clock generation and distribution for the third generation Itanium/spl reg/ processor","authors":"S. Tam, U. Desai, R. Limaye","doi":"10.1109/VLSIC.2003.1221148","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221148","url":null,"abstract":"The clock generation and distribution system for the third generation Itanium/spl reg/ processor operates at 1.5 GHz with a skew of 24 ps. Clock optimization fuses enable post-silicon speed path balancing for higher performance.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125363051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221206
M. Pasotti, G. De Sandre, D. Iezzi, D. Lena, G. Muzzi, M. Poles, P. Rolandi
A 8 Mb application-specific embeddable flash memory is presented. It features 3 content-specific I/O ports, delivers a peak read throughput of 1.2 GB/S, and, combined with a special automatic programming gate voltage ramp generator circuit, a programming rate of 1Mbyte/s for non-volatile storage of code, data and embedded FPGA bit stream configurations. The test chip has been designed using a NOR type 0.18 /spl mu/m flash embedded technology with 1.8 V power supply, 2 poly, 6 metal and memory cell size of 0.35 /spl mu/m/sup 2/.
{"title":"An application specific embeddable flash memory system for non-volatile storage of code, data and bit-streams for embedded FPGA configurations","authors":"M. Pasotti, G. De Sandre, D. Iezzi, D. Lena, G. Muzzi, M. Poles, P. Rolandi","doi":"10.1109/VLSIC.2003.1221206","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221206","url":null,"abstract":"A 8 Mb application-specific embeddable flash memory is presented. It features 3 content-specific I/O ports, delivers a peak read throughput of 1.2 GB/S, and, combined with a special automatic programming gate voltage ramp generator circuit, a programming rate of 1Mbyte/s for non-volatile storage of code, data and embedded FPGA bit stream configurations. The test chip has been designed using a NOR type 0.18 /spl mu/m flash embedded technology with 1.8 V power supply, 2 poly, 6 metal and memory cell size of 0.35 /spl mu/m/sup 2/.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"246 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116711404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221155
Chia-Hsin Wu, Chun-Yi Kuo, Shen-Iuan Liu
For a planar inductor, the maximal quality factor, Q/sub max/, is located at the specified frequency, f/sub Qmax/. In this paper, a method called selective metal parallel shunting (SMPS) is proposed to move f/sub Qmax/ onto the desired frequency without additional processing steps. For a given planar inductor, a customized program is developed to find all the possible SMPS inductors and predict their Q/sub max/ and f/sub max/. Three sets of planar, all metal parallel shunting (AMPS), and SMPS inductors have been implemented in a 1P4M 0.35 /spl mu/m CMOS process to verify the proposed method. The prediction errors of Q/sub max/ and f/sub Qmax/ are less than 13% and 10%, respectively, between the simulated and measured ones. Moreover, three 2.3-2.4 GHz VCOs using planar, AMPS, and SMPS inductors, respectively, have also been realized. The phase noise of the VCO using SMPS inductors can be improved by 9.3 dB and 6 dB, respectively, compared to the VCOs using planar and AMPS inductors at 100 KHz offset frequency. The figure-of-merit (FOM) performance of the VCO using SMPS inductors can be comparable to the state-of-the-art publications.
{"title":"Selective metal parallel shunting inductor and its VCO application","authors":"Chia-Hsin Wu, Chun-Yi Kuo, Shen-Iuan Liu","doi":"10.1109/VLSIC.2003.1221155","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221155","url":null,"abstract":"For a planar inductor, the maximal quality factor, Q/sub max/, is located at the specified frequency, f/sub Qmax/. In this paper, a method called selective metal parallel shunting (SMPS) is proposed to move f/sub Qmax/ onto the desired frequency without additional processing steps. For a given planar inductor, a customized program is developed to find all the possible SMPS inductors and predict their Q/sub max/ and f/sub max/. Three sets of planar, all metal parallel shunting (AMPS), and SMPS inductors have been implemented in a 1P4M 0.35 /spl mu/m CMOS process to verify the proposed method. The prediction errors of Q/sub max/ and f/sub Qmax/ are less than 13% and 10%, respectively, between the simulated and measured ones. Moreover, three 2.3-2.4 GHz VCOs using planar, AMPS, and SMPS inductors, respectively, have also been realized. The phase noise of the VCO using SMPS inductors can be improved by 9.3 dB and 6 dB, respectively, compared to the VCOs using planar and AMPS inductors at 100 KHz offset frequency. The figure-of-merit (FOM) performance of the VCO using SMPS inductors can be comparable to the state-of-the-art publications.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128692633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221203
Chris H. Kim, Kaushik Roy, S. Hsu, A. Alvandpour, R. Krishnamurthy, S. Borkar
A process variation compensating technique for dynamic circuits is described for sub-90 nm technologies where leakage variation is severe. A keeper whose effective strength is optimally programmable based on die leakage enables 10% faster performance, 35% reduction in delay variation, and 5x reduction in robustness failing dies over conventional static keeper design in 90 nm dual-V/sub t/ CMOS.
{"title":"A process variation compensating technique for sub-90 nm dynamic circuits","authors":"Chris H. Kim, Kaushik Roy, S. Hsu, A. Alvandpour, R. Krishnamurthy, S. Borkar","doi":"10.1109/VLSIC.2003.1221203","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221203","url":null,"abstract":"A process variation compensating technique for dynamic circuits is described for sub-90 nm technologies where leakage variation is severe. A keeper whose effective strength is optimally programmable based on die leakage enables 10% faster performance, 35% reduction in delay variation, and 5x reduction in robustness failing dies over conventional static keeper design in 90 nm dual-V/sub t/ CMOS.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122263526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T-Engine is a standard architecture for next generation real-time embedded systems for ubiquitous computing system to improve software productivity of these systems. This paper introduces the basic design philosophy of T-Engine, and overview of its standard hardware and software specifications. By now, several computer vendors have released more than ten hardware systems based on the T-Engine architecture. Upon these, software vendors are developing major middleware components for embedded systems such as Java, Linux, and mobile phone profiles.
{"title":"T-engine: the open, real-time embedded-systems platform for ubiquitous computing","authors":"K. Sakamura, N. Koshizuka","doi":"10.1109/MM.2002.1134343","DOIUrl":"https://doi.org/10.1109/MM.2002.1134343","url":null,"abstract":"T-Engine is a standard architecture for next generation real-time embedded systems for ubiquitous computing system to improve software productivity of these systems. This paper introduces the basic design philosophy of T-Engine, and overview of its standard hardware and software specifications. By now, several computer vendors have released more than ten hardware systems based on the T-Engine architecture. Upon these, software vendors are developing major middleware components for embedded systems such as Java, Linux, and mobile phone profiles.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127528179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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