Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221181
Yonk-Sik Youn, Jang-Hong Choi, Min-Hyung Cho, Seon‐Ho Han, M. Park
A prototype IF transceiver has been integrated in 0.35 /spl mu/m CMOS technology. The chip includes VGAs and mixers for IMT-2000. The VGAs are controlled continuously in linear dB by using a proposed quasi-exponential gain control method. Measurements show that both VGAs have over 90 dB dynamic range and 9.5 dB NF in receiver. The -3 dB frequencies of the receiver and transmitter are 250 MHz and 430 MHz, respectively. Thus, the transceiver can adapt to PCS as well as IMT-2000 for potential dual-band application. With a single 3.0 V power supply, the VGAs and mixers consume 16 mA and 6 mA, respectively.
一个原型中频收发器已集成在0.35 /spl μ m CMOS技术。该芯片包括用于IMT-2000的VGAs和混频器。采用拟指数增益控制方法在线性dB内连续控制VGAs。测量结果表明，两种VGAs的动态范围均超过90 dB，接收机的NF值均超过9.5 dB。接收机和发射机的- 3db频率分别为250mhz和430mhz。因此，收发器可以适应PCS以及IMT-2000潜在的双频应用。使用单个3.0 V电源时，vga和混频器分别消耗16ma和6ma。
{"title":"A CMOS IF transceiver with 90 dB linear control VGA for IMT-2000 application","authors":"Yonk-Sik Youn, Jang-Hong Choi, Min-Hyung Cho, Seon‐Ho Han, M. Park","doi":"10.1109/VLSIC.2003.1221181","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221181","url":null,"abstract":"A prototype IF transceiver has been integrated in 0.35 /spl mu/m CMOS technology. The chip includes VGAs and mixers for IMT-2000. The VGAs are controlled continuously in linear dB by using a proposed quasi-exponential gain control method. Measurements show that both VGAs have over 90 dB dynamic range and 9.5 dB NF in receiver. The -3 dB frequencies of the receiver and transmitter are 250 MHz and 430 MHz, respectively. Thus, the transceiver can adapt to PCS as well as IMT-2000 for potential dual-band application. With a single 3.0 V power supply, the VGAs and mixers consume 16 mA and 6 mA, respectively.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121905619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221164
D. Chang, G. Ahn, U. Moon
A low-voltage two-stage algorithmic ADC incorporating the Opamp-Reset Switching Technique (ORST) is presented. The low-voltage digital CMOS process compatible operation is achieved without the clock boosting/bootstrapping or switched-opamp. The ADC employs a highly linear input sampling circuit at the front-end, and the digital output is calibrated using a radix-based scheme. The prototype was fabricated in a 0.18-/spl mu/m CMOS technology and the active die area is 1.2 mm/spl times/1.2 mm. The calibrated ADC demonstrates 75 dB SFDR at 0.9 V and 80 dB SFDR at 1.2 V. The total power consumption of the ADC is 9 mW at the clock frequency of 7 MHz (1MSPS).
{"title":"A 0.9 V 9 mW 1MSPS digitally calibrated ADC with 75 dB SFDR","authors":"D. Chang, G. Ahn, U. Moon","doi":"10.1109/VLSIC.2003.1221164","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221164","url":null,"abstract":"A low-voltage two-stage algorithmic ADC incorporating the Opamp-Reset Switching Technique (ORST) is presented. The low-voltage digital CMOS process compatible operation is achieved without the clock boosting/bootstrapping or switched-opamp. The ADC employs a highly linear input sampling circuit at the front-end, and the digital output is calibrated using a radix-based scheme. The prototype was fabricated in a 0.18-/spl mu/m CMOS technology and the active die area is 1.2 mm/spl times/1.2 mm. The calibrated ADC demonstrates 75 dB SFDR at 0.9 V and 80 dB SFDR at 1.2 V. The total power consumption of the ADC is 9 mW at the clock frequency of 7 MHz (1MSPS).","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128296064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221172
H. Hatamkhani, Koon-Lun Jackie Wong, R. Drost, C. Yang
This paper describes a low-power self-terminated transmitter. A novel architecture is proposed to perform impedance matching and channel equalization with low power consumption. The test chip is fabricated using 0.18-/spl mu/m digital CMOS process with 1.8-V supply. The transmitter operates at 3.6 Gbps and consumes 9.66 mW. The total transmitter area is 0.072 mm/sup 2/.
{"title":"A 10-mW 3.6-Gbps I/O transmitter","authors":"H. Hatamkhani, Koon-Lun Jackie Wong, R. Drost, C. Yang","doi":"10.1109/VLSIC.2003.1221172","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221172","url":null,"abstract":"This paper describes a low-power self-terminated transmitter. A novel architecture is proposed to perform impedance matching and channel equalization with low power consumption. The test chip is fabricated using 0.18-/spl mu/m digital CMOS process with 1.8-V supply. The transmitter operates at 3.6 Gbps and consumes 9.66 mW. The total transmitter area is 0.072 mm/sup 2/.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122595566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221205
T. Tanaka, H. Tanikawa, T. Yamaki, Y. Umemoto, A. Kato, Y. Shinagawa, M. Hiraki
We present a 512 kB MONOS type flash memory module embedded in a microcontroller fabricated with a 0.18 /spl mu/m CMOS process. Our new memory cell structure enables the whole read path in the module to be composed of low voltage transistors that are the same as those used in the CPU core, and therefore achieves compact layout of peripheral circuits. The module achieves 34 MHz random access read operation. The measured program time and erase time for a 64 kB block were less than 4 ms and less than 11 ms, respectively. The area of the 512 kB module is 5.4 mm/sup 2/.
{"title":"A 512 kB MONOS type flash memory module embedded in a microcontroller","authors":"T. Tanaka, H. Tanikawa, T. Yamaki, Y. Umemoto, A. Kato, Y. Shinagawa, M. Hiraki","doi":"10.1109/VLSIC.2003.1221205","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221205","url":null,"abstract":"We present a 512 kB MONOS type flash memory module embedded in a microcontroller fabricated with a 0.18 /spl mu/m CMOS process. Our new memory cell structure enables the whole read path in the module to be composed of low voltage transistors that are the same as those used in the CPU core, and therefore achieves compact layout of peripheral circuits. The module achieves 34 MHz random access read operation. The measured program time and erase time for a 64 kB block were less than 4 ms and less than 11 ms, respectively. The area of the 512 kB module is 5.4 mm/sup 2/.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130672152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221208
F. Tillman, H. Sjoland
A bootstrapping technique for passive mixers has been implemented in a fully integrated 1V CMOS front-end. The idea is to improve the linearity of the mixer by making the switching instants independent of the IF output signal. The technique reduces the intermodulation distortion without degradation of the conversion gain or the noise figure. The measured IIP/sub 3/ of the front-end was increased by 5 dB resulting in an increased dynamic range, which is critical for low supply voltages.
{"title":"A bootstrapping technique to improve the linearity of CMOS passive mixers","authors":"F. Tillman, H. Sjoland","doi":"10.1109/VLSIC.2003.1221208","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221208","url":null,"abstract":"A bootstrapping technique for passive mixers has been implemented in a fully integrated 1V CMOS front-end. The idea is to improve the linearity of the mixer by making the switching instants independent of the IF output signal. The technique reduces the intermodulation distortion without degradation of the conversion gain or the noise figure. The measured IIP/sub 3/ of the front-end was increased by 5 dB resulting in an increased dynamic range, which is critical for low supply voltages.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"427 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131885659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221194
H. McAdams, R. Acklin, T. Blake, J. Fong, D. Liu, S. Madan, T. Moise, S. Natarajan, N. Qian, Y. Qui, J. Roscher, A. Seshadri, S. Summerfelt, X. Du, J. Eliason, W. Kraus, R. Lanham, F. Li, C. Pietrzyk, J. Rickes
A low-voltage (1.3V), 64 Mbit Ferroelectric Random Access Memory using a 1-transistor, 1-capacitor (1T1C) cell is demonstrated. This is the largest FRAM memory demonstrated to date. The memory is constructed using a state-of-the-art 130 nm transistor and a five-level Cu/FSG interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate oxide, low-voltage logic process. Address access time for the memory is less than 30 ns while consuming 0.57 mW/MHz at 1.37 V. An eFRAM density of 1.13 Mb/mm/sup 2/ is achieved with a cell size of 0.54 /spl mu/m/sup 2/ and capacitor size of 0.25 /spl mu/m/sup 2/.
{"title":"A 64 Mbit embedded FeRAM utilizing a 130 nm, 5LM Cu/FSG logic process","authors":"H. McAdams, R. Acklin, T. Blake, J. Fong, D. Liu, S. Madan, T. Moise, S. Natarajan, N. Qian, Y. Qui, J. Roscher, A. Seshadri, S. Summerfelt, X. Du, J. Eliason, W. Kraus, R. Lanham, F. Li, C. Pietrzyk, J. Rickes","doi":"10.1109/VLSIC.2003.1221194","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221194","url":null,"abstract":"A low-voltage (1.3V), 64 Mbit Ferroelectric Random Access Memory using a 1-transistor, 1-capacitor (1T1C) cell is demonstrated. This is the largest FRAM memory demonstrated to date. The memory is constructed using a state-of-the-art 130 nm transistor and a five-level Cu/FSG interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate oxide, low-voltage logic process. Address access time for the memory is less than 30 ns while consuming 0.57 mW/MHz at 1.37 V. An eFRAM density of 1.13 Mb/mm/sup 2/ is achieved with a cell size of 0.54 /spl mu/m/sup 2/ and capacitor size of 0.25 /spl mu/m/sup 2/.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133147126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221193
T. Chandler, A. Sheikholeslami, S. Masui, M. Oura
A reference time, instead of a reference voltage, is generated used to compare stored "0" and "1" in a race of bitlines towards reaching a threshold voltage in a 1T1C FeRAM. The reference time is adaptive, tracking process variations, aging, and fatigue of ferroelectric capacitors. This scheme is implemented in a 256/spl times/128-bit testchip in a 0.35 /spl mu/m ferroelectric process and achieves a 40 ns access time at 3 V.
{"title":"An adaptive reference generation scheme for 1T1C FeRAMs","authors":"T. Chandler, A. Sheikholeslami, S. Masui, M. Oura","doi":"10.1109/VLSIC.2003.1221193","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221193","url":null,"abstract":"A reference time, instead of a reference voltage, is generated used to compare stored \"0\" and \"1\" in a race of bitlines towards reaching a threshold voltage in a 1T1C FeRAM. The reference time is adaptive, tracking process variations, aging, and fatigue of ferroelectric capacitors. This scheme is implemented in a 256/spl times/128-bit testchip in a 0.35 /spl mu/m ferroelectric process and achieves a 40 ns access time at 3 V.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129359984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221198
M. Toyama, S. Dosho, N. Yanagisawa
This paper describes a design of a compact active loop filter for Phase-Locked-Loop (PLL) with adaptive biasing technique. Using the new loop filter, the PLL can automatically adjust the loop bandwidth and damping factor to the frequency of the reference clock. Moreover, the new LPF can decrease the capacitance value to 1/10-1/20 of conventional one. A test chip was fabricated in 0.15 /spl mu/m-CMOS process. The total chip area of the PLL is reduced to 1/2 of previous one. The jitter performance is almost equal to conventionally biased PLL.
{"title":"A design of a compact 2 GHz-PLL with a new adaptive active loop filter circuit","authors":"M. Toyama, S. Dosho, N. Yanagisawa","doi":"10.1109/VLSIC.2003.1221198","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221198","url":null,"abstract":"This paper describes a design of a compact active loop filter for Phase-Locked-Loop (PLL) with adaptive biasing technique. Using the new loop filter, the PLL can automatically adjust the loop bandwidth and damping factor to the frequency of the reference clock. Moreover, the new LPF can decrease the capacitance value to 1/10-1/20 of conventional one. A test chip was fabricated in 0.15 /spl mu/m-CMOS process. The total chip area of the PLL is reduced to 1/2 of previous one. The jitter performance is almost equal to conventionally biased PLL.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131161893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221184
A. Ravi, K. Soumyanath, R. Bishop, B. Bloechel, L. Carley
We present a 5 GHz, voltage controlled quadrature oscillator, based on transformer coupling between the quadrature components. The oscillator is fabricated in a 0.18 /spl mu/m, low voltage digital CMOS process with a lossy substrate (/spl rho//spl sim/10mohm-cm) and thin, high resistivity metallization. Fully integrated low Q (/spl sim/4) spirals form the transformer windings in the resonators. The coupling has been optimized to obtain quadrature accuracy with minimum phase noise degradation. The VCO achieves a tuning range of /spl sim/1 GHz, and a phase noise of up to -123 dBc/Hz at a 1 MHz offset, while drawing 7.5 mA at 1.6 V. An image reject receiver built using the onwafer quadrature signals, provides 43 dB of image rejection, confirming better than 1/sup 0/ of quadrature matching.
{"title":"An optimally transformer coupled, 5 GHz quadrature VCO in a 0.18 /spl mu/m digital CMOS process","authors":"A. Ravi, K. Soumyanath, R. Bishop, B. Bloechel, L. Carley","doi":"10.1109/VLSIC.2003.1221184","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221184","url":null,"abstract":"We present a 5 GHz, voltage controlled quadrature oscillator, based on transformer coupling between the quadrature components. The oscillator is fabricated in a 0.18 /spl mu/m, low voltage digital CMOS process with a lossy substrate (/spl rho//spl sim/10mohm-cm) and thin, high resistivity metallization. Fully integrated low Q (/spl sim/4) spirals form the transformer windings in the resonators. The coupling has been optimized to obtain quadrature accuracy with minimum phase noise degradation. The VCO achieves a tuning range of /spl sim/1 GHz, and a phase noise of up to -123 dBc/Hz at a 1 MHz offset, while drawing 7.5 mA at 1.6 V. An image reject receiver built using the onwafer quadrature signals, provides 43 dB of image rejection, confirming better than 1/sup 0/ of quadrature matching.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129259979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221211
R. Montemayor
A 1.22-GHz Downconverter used in a dual-conversion tuner IC for OpenCable/spl trade/ applications is presented. Fabricated in a five-metal, 0.35-/spl mu/m, 27-GHz f/sub t/ SOI BiCMOS technology and consuming 124 mA from a 3.3-V supply, it downconverts the input to an IF of 44 MHz and achieves 26 dB gain, 23 dB gain control range, 5.1 dB NF, 33 dBmV P/sub 1dB/, 56 dBmV IIP/sub 3/, -72 dBc CTB, -60 dBc X-mod., and 30 dB image rejection.
{"title":"A 410-mW, 1.22-GHz downconverter in a dual-conversion tuner IC for OpenCable/spl trade/ applications","authors":"R. Montemayor","doi":"10.1109/VLSIC.2003.1221211","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221211","url":null,"abstract":"A 1.22-GHz Downconverter used in a dual-conversion tuner IC for OpenCable/spl trade/ applications is presented. Fabricated in a five-metal, 0.35-/spl mu/m, 27-GHz f/sub t/ SOI BiCMOS technology and consuming 124 mA from a 3.3-V supply, it downconverts the input to an IF of 44 MHz and achieves 26 dB gain, 23 dB gain control range, 5.1 dB NF, 33 dBmV P/sub 1dB/, 56 dBmV IIP/sub 3/, -72 dBc CTB, -60 dBc X-mod., and 30 dB image rejection.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121220180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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