Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221157
Martin Yeung-Kei Chui, W. Ki, C. Tsui
A 0.6 /spl mu/m CMOS integrated digital PID controller for a buck converter is presented. It consists of: (1) a VCO driving a counter to serve as an ADC; (2) a PID compensator that employs variable integration times for enhancing accuracy and stability, and (3) a dual-band switching PWM generator with a modified tapped delay line for better output resolution and area efficiency. The converter switches at 1 MHz, while the tracking time is 50 /spl mu/s for a step change of 1 V.
介绍了一种用于降压变换器的0.6 /spl μ m CMOS集成数字PID控制器。它包括:(1)一个VCO驱动计数器作为ADC;(2)采用可变积分时间的PID补偿器，以提高精度和稳定性;(3)带有改进抽头延迟线的双频开关PWM发生器，以提高输出分辨率和面积效率。转换器的开关频率为1mhz，当阶跃变化为1v时，跟踪时间为50 /spl mu/s。
{"title":"An integrated digital controller for DC-DC switching converter with dual-band switching","authors":"Martin Yeung-Kei Chui, W. Ki, C. Tsui","doi":"10.1109/VLSIC.2003.1221157","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221157","url":null,"abstract":"A 0.6 /spl mu/m CMOS integrated digital PID controller for a buck converter is presented. It consists of: (1) a VCO driving a counter to serve as an ADC; (2) a PID compensator that employs variable integration times for enhancing accuracy and stability, and (3) a dual-band switching PWM generator with a modified tapped delay line for better output resolution and area efficiency. The converter switches at 1 MHz, while the tracking time is 50 /spl mu/s for a step change of 1 V.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121107637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221159
S. Mukhopadhyay, Kaushik Roy
In this work we have developed an accurate model of total leakage in a transistor stack based on the compact model of gate, subthreshold and band-to-band-tunneling leakage. Using this model, we have analyzed the opportunities for overall stand-by leakage reduction in scaled devices using transistor stacking and proved that the best input vector that minimize overall leakage depends on the relative magnitude of the different leakage components. A novel stacking technique based on the ratio of the different leakage components is proposed and its effectiveness in total leakage reduction in transistor stack and logic gate is analyzed.
{"title":"Accurate modeling of transistor stacks to effectively reduce total standby leakage in nano-scale CMOS circuits","authors":"S. Mukhopadhyay, Kaushik Roy","doi":"10.1109/VLSIC.2003.1221159","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221159","url":null,"abstract":"In this work we have developed an accurate model of total leakage in a transistor stack based on the compact model of gate, subthreshold and band-to-band-tunneling leakage. Using this model, we have analyzed the opportunities for overall stand-by leakage reduction in scaled devices using transistor stacking and proved that the best input vector that minimize overall leakage depends on the relative magnitude of the different leakage components. A novel stacking technique based on the ratio of the different leakage components is proposed and its effectiveness in total leakage reduction in transistor stack and logic gate is analyzed.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126841736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221202
M. Ma, S. Gunther, B. Greiner, N. Wolff, C. Deutschle, T. Arabi
An enhanced thermal management mechanism that reduces power by scaling frequency and voltage in response to excessive temperatures is presented. The voltage transition process is done transparently to the execution of applications. The enhanced mechanism achieves an /spl sim/50% power reduction while limiting the performance impact to only /spl sim/20% for the duration of the thermal event. The approach allows the processor to meet its performance and reliability goals without additional thermal solution costs.
{"title":"Enhanced thermal management for future processors","authors":"M. Ma, S. Gunther, B. Greiner, N. Wolff, C. Deutschle, T. Arabi","doi":"10.1109/VLSIC.2003.1221202","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221202","url":null,"abstract":"An enhanced thermal management mechanism that reduces power by scaling frequency and voltage in response to excessive temperatures is presented. The voltage transition process is done transparently to the execution of applications. The enhanced mechanism achieves an /spl sim/50% power reduction while limiting the performance impact to only /spl sim/20% for the duration of the thermal event. The approach allows the processor to meet its performance and reliability goals without additional thermal solution costs.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114422013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221201
M. Peng
This paper presents a study of substrate noise effects on analog circuits and a technique for minimizing substrate noise. Measured data of a 0.25 /spl mu/m CMOS test chip reveals that substrate noise couples through circuit asymmetries and nonlinearity, degrading analog circuit performance. An active substrate noise shaping circuit implemented on the same test chip demonstrates over 10 dB improvement in SNDR in the 0-20 kHz band of a delta-sigma modulator for substrate noise generated by an inverter array.
本文研究了衬底噪声对模拟电路的影响，并提出了一种减小衬底噪声的技术。0.25 /spl μ l /m CMOS测试芯片的测量数据表明，衬底噪声通过电路的不对称和非线性耦合，降低了模拟电路的性能。在同一测试芯片上实现的有源衬底噪声整形电路表明，对于由逆变器阵列产生的衬底噪声，δ - σ调制器在0-20 kHz频段的SNDR提高了10 dB以上。
{"title":"Study of substrate noise and techniques for minimization","authors":"M. Peng","doi":"10.1109/VLSIC.2003.1221201","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221201","url":null,"abstract":"This paper presents a study of substrate noise effects on analog circuits and a technique for minimizing substrate noise. Measured data of a 0.25 /spl mu/m CMOS test chip reveals that substrate noise couples through circuit asymmetries and nonlinearity, degrading analog circuit performance. An active substrate noise shaping circuit implemented on the same test chip demonstrates over 10 dB improvement in SNDR in the 0-20 kHz band of a delta-sigma modulator for substrate noise generated by an inverter array.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116922064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221185
S. Pellerano, C. Samori, S. Levantino, A. Lacaita
An integrated 5 GHz frequency synthesizer consuming only 5.4 mA from a 2.5 V supply is demonstrated in 0.25 /spl mu/m CMOS technology. The divider within the synthesizer employs the True Single Phase Clock logic. The output frequency spans from 5.14 to 5.70 GHz, with steps of 20 MHz. The reference spurs are -70 dBc and the phase noise is lower than -116 dBc/Hz at 1 MHz offset over the whole tuning range. The synthesizer is suitable for the HiperLAN II and the IEEE 802.11a standards.
{"title":"13.5-mW, 5-GHz WLAN, CMOS frequency synthesizer using a true single phase clock divider","authors":"S. Pellerano, C. Samori, S. Levantino, A. Lacaita","doi":"10.1109/VLSIC.2003.1221185","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221185","url":null,"abstract":"An integrated 5 GHz frequency synthesizer consuming only 5.4 mA from a 2.5 V supply is demonstrated in 0.25 /spl mu/m CMOS technology. The divider within the synthesizer employs the True Single Phase Clock logic. The output frequency spans from 5.14 to 5.70 GHz, with steps of 20 MHz. The reference spurs are -70 dBc and the phase noise is lower than -116 dBc/Hz at 1 MHz offset over the whole tuning range. The synthesizer is suitable for the HiperLAN II and the IEEE 802.11a standards.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131411334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221162
R. Farjad-Rad, Hiok-Tiaq Ng, M.-J. Edward Lee, R. Senthinathan, W. Dally, A. Nguyen, R. Rathi, J. Poulton, J. Edmondson, J. Tran, H. Yazdanmehr
This paper presents a 622 Mbps to 8 Gbps transceiver in standard 0.13 /spl mu/m CMOS technology. Each receiver and transmitter macrocell has its dedicated clock multiplication unit (CMU) and clock/data recovery unit (CDR), providing simultaneous multi-rate operation for multiple lanes on a chip. The transmitter and receiver front-end use direct 4:1 multiplex and 1:4 demultiplexing, using multiple-phase quarter-rate clocks. An automatic phase offset cancellation scheme is used to eliminate the phase mismatch of the multiple clock phases. Each transceiver occupies an active area of less than 0.4 mm/sup 2/ and consumes 150 mW at maximum speed.
{"title":"0.622-8.0 Gbps 150 mW serial IO macrocell with fully flexible preemphasis and equalization","authors":"R. Farjad-Rad, Hiok-Tiaq Ng, M.-J. Edward Lee, R. Senthinathan, W. Dally, A. Nguyen, R. Rathi, J. Poulton, J. Edmondson, J. Tran, H. Yazdanmehr","doi":"10.1109/VLSIC.2003.1221162","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221162","url":null,"abstract":"This paper presents a 622 Mbps to 8 Gbps transceiver in standard 0.13 /spl mu/m CMOS technology. Each receiver and transmitter macrocell has its dedicated clock multiplication unit (CMU) and clock/data recovery unit (CDR), providing simultaneous multi-rate operation for multiple lanes on a chip. The transmitter and receiver front-end use direct 4:1 multiplex and 1:4 demultiplexing, using multiple-phase quarter-rate clocks. An automatic phase offset cancellation scheme is used to eliminate the phase mismatch of the multiple clock phases. Each transceiver occupies an active area of less than 0.4 mm/sup 2/ and consumes 150 mW at maximum speed.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122925194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221174
J. Choi, Moon-Sang Hwang, D. Jeong
This paper describes a high-speed CMOS adaptive cable equalizer with the joint adaptation method of low-frequency gain and high-frequency boosting. The adaptation method compares not only the high-frequency contents but also the low-frequency contents. By this joint adaptation method, the adaptation inaccuracy due to amplitude deviation can be reduced. The filter cell in the equalizer uses the variable-capacitor tuning and feed-forward common-mode-voltage biasing technique to achieve high bandwidth. The prototype chip is fabricated in a 0.18 /spl mu/m mixed-mode CMOS process. The realized active area is 0.48 mm/spl times/0.73 mm. The filter cell operates up to 5 Gbps and the adaptive equalizer operates up to 3.5 Gbps over a 15-m RG-58 coaxial cable with a 1.8 V supply and 80 mW power dissipation.
{"title":"A CMOS 3.5 Gbps continuous-time adaptive cable equalizer with joint adaptation method of low-frequency gain and high-frequency boosting","authors":"J. Choi, Moon-Sang Hwang, D. Jeong","doi":"10.1109/VLSIC.2003.1221174","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221174","url":null,"abstract":"This paper describes a high-speed CMOS adaptive cable equalizer with the joint adaptation method of low-frequency gain and high-frequency boosting. The adaptation method compares not only the high-frequency contents but also the low-frequency contents. By this joint adaptation method, the adaptation inaccuracy due to amplitude deviation can be reduced. The filter cell in the equalizer uses the variable-capacitor tuning and feed-forward common-mode-voltage biasing technique to achieve high bandwidth. The prototype chip is fabricated in a 0.18 /spl mu/m mixed-mode CMOS process. The realized active area is 0.48 mm/spl times/0.73 mm. The filter cell operates up to 5 Gbps and the adaptive equalizer operates up to 3.5 Gbps over a 15-m RG-58 coaxial cable with a 1.8 V supply and 80 mW power dissipation.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114056644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221171
T. Ohsawa, T. Higashi, K. Fujita, T. Ikehashi, T. Kajiyama, Y. Fukuzumi, T. Shino, H. Yamada, H. Nakajima, Y. Minami, T. Yamada, K. Inoh, T. Hamamoto
A 288 Kbit memory chip featuring a one-transistor gain cell on SOI of the size 0.21 /spl mu/m/sup 2/(7F/sup 2/ with F=0.175 /spl mu/m) which we named the floating body transistor cell (FBC) is presented and basic characteristics of the cell and the memory chip performance are disclosed. The threshold voltages of a cell transistor in the chip for the data "1" and for the data "0" are measured by using a direct access test circuit and a fail bit map for the 96 Kbit array is obtained. A sensing scheme which was designed to eliminate the effect of cell characteristics variation due to process and temperature fluctuation as common mode noise is verified to be working and the random access time is measured to be less than 100 ns. The characteristics of data hold demonstrate that the FBC can satisfy retention time specifications for some embedded memories. The access time and the data retention time show that the FBC has a potential to be used as a future embedded DRAM memory cell.
{"title":"A memory using one-transistor gain cell on SOI(FBC) with performance suitable for embedded DRAM's","authors":"T. Ohsawa, T. Higashi, K. Fujita, T. Ikehashi, T. Kajiyama, Y. Fukuzumi, T. Shino, H. Yamada, H. Nakajima, Y. Minami, T. Yamada, K. Inoh, T. Hamamoto","doi":"10.1109/VLSIC.2003.1221171","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221171","url":null,"abstract":"A 288 Kbit memory chip featuring a one-transistor gain cell on SOI of the size 0.21 /spl mu/m/sup 2/(7F/sup 2/ with F=0.175 /spl mu/m) which we named the floating body transistor cell (FBC) is presented and basic characteristics of the cell and the memory chip performance are disclosed. The threshold voltages of a cell transistor in the chip for the data \"1\" and for the data \"0\" are measured by using a direct access test circuit and a fail bit map for the 96 Kbit array is obtained. A sensing scheme which was designed to eliminate the effect of cell characteristics variation due to process and temperature fluctuation as common mode noise is verified to be working and the random access time is measured to be less than 100 ns. The characteristics of data hold demonstrate that the FBC can satisfy retention time specifications for some embedded memories. The access time and the data retention time show that the FBC has a potential to be used as a future embedded DRAM memory cell.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"103 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116656371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221146
The historic three decades, 80's, 90's and 00's are discussed with a focus on the Japanese semiconductor industry in view of global relationship. Financial strategy and market nature rather than pure technology issues drove furious and drastic changes from prosperity to new paradigm in the 90's. For the new century, some key concepts are implied such as from scale to individuals and IPs, from large teams to small ones, and from technology driven to application driven. Strategies needed to overcome the transition impact, and what required for the post-transition competitions are suggested.
{"title":"Semiconductor industry: the name of the game","authors":"","doi":"10.1109/VLSIC.2003.1221146","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221146","url":null,"abstract":"The historic three decades, 80's, 90's and 00's are discussed with a focus on the Japanese semiconductor industry in view of global relationship. Financial strategy and market nature rather than pure technology issues drove furious and drastic changes from prosperity to new paradigm in the 90's. For the new century, some key concepts are implied such as from scale to individuals and IPs, from large teams to small ones, and from technology driven to application driven. Strategies needed to overcome the transition impact, and what required for the post-transition competitions are suggested.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123771855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221223
T. Yamasaki, T. Fukuda, T. Shibata
Low-power and compact CDMA matched filters have been developed based on the floating-gate MOS technology. The low-power operation has been achieved by employing the single-step matching scheme and disconnecting the coupling-capacitors unnecessary for the matching operation. The 255-chip matched filter fabricated in a 0.35-/spl mu/m technology demonstrated 6 mW operation at 3 V power supply and the chip rate of 5 MS/S, while occupying the chip area of 1.0 mm/sup 2/.
{"title":"A floating-gate-MOS-based low-power CDMA matched filter employing capacitance disconnection technique","authors":"T. Yamasaki, T. Fukuda, T. Shibata","doi":"10.1109/VLSIC.2003.1221223","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221223","url":null,"abstract":"Low-power and compact CDMA matched filters have been developed based on the floating-gate MOS technology. The low-power operation has been achieved by employing the single-step matching scheme and disconnecting the coupling-capacitors unnecessary for the matching operation. The 255-chip matched filter fabricated in a 0.35-/spl mu/m technology demonstrated 6 mW operation at 3 V power supply and the chip rate of 5 MS/S, while occupying the chip area of 1.0 mm/sup 2/.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133573673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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