Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332992
Taegeun Yoo, T. T. Kim, Bongjin Kim, Chengshuo Yu, Kevin Chai Tshun Chuan
A novel 8T SRAM bitcell is proposed for computing dot-products using current-mode accumulation. A write disturb issue has been eliminated by adding two extra transistors into a standard 6T SRAM bitcell. Besides, we embed a column ADC in each column-based neuron to address the ADC overhead issue of conventional analog compute-in-memory macros. The resolution of ADC is reconfigurable from 1 to 5bit. A test-chip is fabricated using 65nm, and the energy-efficiency of bitwise operation is 490-to-15.8TOPS/W at 1-5bit.
{"title":"Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks","authors":"Taegeun Yoo, T. T. Kim, Bongjin Kim, Chengshuo Yu, Kevin Chai Tshun Chuan","doi":"10.1109/ISOCC50952.2020.9332992","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332992","url":null,"abstract":"A novel 8T SRAM bitcell is proposed for computing dot-products using current-mode accumulation. A write disturb issue has been eliminated by adding two extra transistors into a standard 6T SRAM bitcell. Besides, we embed a column ADC in each column-based neuron to address the ADC overhead issue of conventional analog compute-in-memory macros. The resolution of ADC is reconfigurable from 1 to 5bit. A test-chip is fabricated using 65nm, and the energy-efficiency of bitwise operation is 490-to-15.8TOPS/W at 1-5bit.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131574122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332957
A. Mishra, Shiho Kim, N. S. Rajput
Intelligent gas monitoring system is having its widespread applications. It essentially requires an accurate classification with precise quantification of gases/odors. Although, gas sensor arrays are capable of generating signatures however, mostly these signatures are complex and have subtle information. Therefore, in this paper, an efficient sensory system has been proposed for intelligent gas monitoring. Concept of analysis space transformation has been utilized for accurate classification of gases/ odors. Also, the drawback of data preprocessing in quantification has been illustrated by comparing the quantifier performance for the processed and raw responses. Further, the proposed sensory system has elevated the classification accuracy from 96% to 98.74% along with the quantification accuracy from 17.65% to 94%.
{"title":"An Efficient Sensory System for Intelligent Gas Monitoring Accurate classification and precise quantification of gases/ odors","authors":"A. Mishra, Shiho Kim, N. S. Rajput","doi":"10.1109/ISOCC50952.2020.9332957","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332957","url":null,"abstract":"Intelligent gas monitoring system is having its widespread applications. It essentially requires an accurate classification with precise quantification of gases/odors. Although, gas sensor arrays are capable of generating signatures however, mostly these signatures are complex and have subtle information. Therefore, in this paper, an efficient sensory system has been proposed for intelligent gas monitoring. Concept of analysis space transformation has been utilized for accurate classification of gases/ odors. Also, the drawback of data preprocessing in quantification has been illustrated by comparing the quantifier performance for the processed and raw responses. Further, the proposed sensory system has elevated the classification accuracy from 96% to 98.74% along with the quantification accuracy from 17.65% to 94%.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131582773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333102
Yuanyang Du, Xueyan Bai, Manato Hirai, Shuhei Yamamoto, A. Kuwana, Haruo Kobayashi, K. Kubo
This paper describes new configurations of digital-to-analog converters (DACs) based on number theory: (i) DACs consisting of N current sources, N-angle number weighted resistor networks, switch arrays and decoders (N= 3, 4, 5,…). (ii) A DAC composed of two current sources, a prime number weighted resistor network, switch array, a decoder; this is based on Goldbach's conjecture in the number theory. Their principles, configurations and operations are presented.
{"title":"Digital-to-Analog Converter Architectures Based on Polygonal and Prime Numbers","authors":"Yuanyang Du, Xueyan Bai, Manato Hirai, Shuhei Yamamoto, A. Kuwana, Haruo Kobayashi, K. Kubo","doi":"10.1109/ISOCC50952.2020.9333102","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333102","url":null,"abstract":"This paper describes new configurations of digital-to-analog converters (DACs) based on number theory: (i) DACs consisting of N current sources, N-angle number weighted resistor networks, switch arrays and decoders (N= 3, 4, 5,…). (ii) A DAC composed of two current sources, a prime number weighted resistor network, switch array, a decoder; this is based on Goldbach's conjecture in the number theory. Their principles, configurations and operations are presented.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128201300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333090
Soyoun Park, Jae-Hee Lee, Hang-Geun Jeong, D. Im
We propose a new current mode CMOS squaring circuit which directly yields the square term. The proposed squaring circuit was designed in a standard with 0.18 µm CMOS technology. The designed chip occupies a chip area of 408µm × 197µm and consumes a power of 3.6mW. The proposed squaring circuit can be used in current mode applications as in analog neurons.
{"title":"Design of a CMOS Current-mode Squaring Circuit for Training Analog Neural Networks","authors":"Soyoun Park, Jae-Hee Lee, Hang-Geun Jeong, D. Im","doi":"10.1109/ISOCC50952.2020.9333090","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333090","url":null,"abstract":"We propose a new current mode CMOS squaring circuit which directly yields the square term. The proposed squaring circuit was designed in a standard with 0.18 µm CMOS technology. The designed chip occupies a chip area of 408µm × 197µm and consumes a power of 3.6mW. The proposed squaring circuit can be used in current mode applications as in analog neurons.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113969431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332971
Jungwon Lee, Hyoju Seo, Yerin Kim, Yongtae Kim
We propose a cost-effective approximate adder using a zero truncation technique with acceptable accuracy. The proposed adder design reduces the area by up to 23% compared to the approximate adders considered in this paper when implemented with a 32-nm CMOS technology. Furthermore, our adder shows 16%, 10%, 10%, and 16% better performance in area, power, power-delay product, and area-delay product, respectively, than the lower-part OR adder while providing an acceptable accuracy performance. To see the impact of approximation errors caused by our adder on real applications, it is adopted in a digital image processing and demonstrates that our adder rarely affects the output image quality.
{"title":"Design of a Low-Cost Approximate Adder with a Zero Truncation","authors":"Jungwon Lee, Hyoju Seo, Yerin Kim, Yongtae Kim","doi":"10.1109/ISOCC50952.2020.9332971","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332971","url":null,"abstract":"We propose a cost-effective approximate adder using a zero truncation technique with acceptable accuracy. The proposed adder design reduces the area by up to 23% compared to the approximate adders considered in this paper when implemented with a 32-nm CMOS technology. Furthermore, our adder shows 16%, 10%, 10%, and 16% better performance in area, power, power-delay product, and area-delay product, respectively, than the lower-part OR adder while providing an acceptable accuracy performance. To see the impact of approximation errors caused by our adder on real applications, it is adopted in a digital image processing and demonstrates that our adder rarely affects the output image quality.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121220368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332807
Mehdi Nasrollahpour, Alexei D. Matyushov, Mohsen Zaeimbashi, N. Sun
This paper presents a miniaturized complementary-metal-oxide-semiconductor (CMOS) oscillator using microelectromechanical system (MEMS) resonating at 159 MHz frequency. The CMOS circuit is designed and simulated in 0.35,..,m XFAB technology. The fabricated magnetoelectric (ME) sensor offers quality factor of 653. The proposed oscillator provides a phase noise as low as -131.3 dBc/Hz at 10kHz and -137.9 dBc/Hz at 100 kHz offset frequencies while consuming 2.24 mW power.
{"title":"A Low Noise MEMS Based CMOS Resonator Using Magnetoelectric Sensor","authors":"Mehdi Nasrollahpour, Alexei D. Matyushov, Mohsen Zaeimbashi, N. Sun","doi":"10.1109/ISOCC50952.2020.9332807","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332807","url":null,"abstract":"This paper presents a miniaturized complementary-metal-oxide-semiconductor (CMOS) oscillator using microelectromechanical system (MEMS) resonating at 159 MHz frequency. The CMOS circuit is designed and simulated in 0.35,..,m XFAB technology. The fabricated magnetoelectric (ME) sensor offers quality factor of 653. The proposed oscillator provides a phase noise as low as -131.3 dBc/Hz at 10kHz and -137.9 dBc/Hz at 100 kHz offset frequencies while consuming 2.24 mW power.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121256661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333089
Yeonjin Kim, Jin-Gyun Chung
Controller area network (CAN) was introduced by Bosch in 1986. CAN has been commonly used in vehicles due to its high reliability and low cost. Over the past decade, the possibilities for security attacks in vehicles have been increasing and have been reported in several papers. However, security issues have not been treated properly in CAN. In this paper, we propose a security protocol based on the data compression algorithm.
{"title":"Variable Length MAC for CAN Security Protocol","authors":"Yeonjin Kim, Jin-Gyun Chung","doi":"10.1109/ISOCC50952.2020.9333089","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333089","url":null,"abstract":"Controller area network (CAN) was introduced by Bosch in 1986. CAN has been commonly used in vehicles due to its high reliability and low cost. Over the past decade, the possibilities for security attacks in vehicles have been increasing and have been reported in several papers. However, security issues have not been treated properly in CAN. In this paper, we propose a security protocol based on the data compression algorithm.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129263073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332974
Junghwan Kim, Jongkil Hyun, Byungin Moon
An integral image is widely used in face detection to calculate feature values at high speed. However, implementing integral images in hardware requires considerable logic and memory resources. This paper proposes a hardware architecture for integral image generation with reduced resource usage by applying the word length reduction method. When implemented in an FPGA, the proposed architecture uses about 83% fewer Slice LUTs than the conventional integral image method. Therefore, the proposed architecture is suitable for low-cost realtime face detection systems.
{"title":"Low-cost Hardware Architecture for Integral Image Generation using Word Length Reduction","authors":"Junghwan Kim, Jongkil Hyun, Byungin Moon","doi":"10.1109/ISOCC50952.2020.9332974","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332974","url":null,"abstract":"An integral image is widely used in face detection to calculate feature values at high speed. However, implementing integral images in hardware requires considerable logic and memory resources. This paper proposes a hardware architecture for integral image generation with reduced resource usage by applying the word length reduction method. When implemented in an FPGA, the proposed architecture uses about 83% fewer Slice LUTs than the conventional integral image method. Therefore, the proposed architecture is suitable for low-cost realtime face detection systems.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115869585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332939
K. Kitamura, Y. Uwate, Y. Nishio
The Cellular Neural Networks (CNN) was developed by Chua and Yang in 1998. The performance of the CNN depends on the parameters which are called the template. The CNN is applied to various image processing by changing the template. The output image processed by CNN is a binary image. Therefore, the unnecessary objects are removed in the process. In this research, we propose a method of switching two templates to stop the image processing in a certain state and output in the grayscale state.
{"title":"Maintaining Images by Cellular Neural Networks with Switching Two Templates","authors":"K. Kitamura, Y. Uwate, Y. Nishio","doi":"10.1109/ISOCC50952.2020.9332939","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332939","url":null,"abstract":"The Cellular Neural Networks (CNN) was developed by Chua and Yang in 1998. The performance of the CNN depends on the parameters which are called the template. The CNN is applied to various image processing by changing the template. The output image processed by CNN is a binary image. Therefore, the unnecessary objects are removed in the process. In this research, we propose a method of switching two templates to stop the image processing in a certain state and output in the grayscale state.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117056051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333002
Y. Uwate, Y. Nishio, M. Obien, U. Frey
It is well known that burst patterns of neuronal networks may play an important role in information processing in the brain. We consider that it is advantageous to construct a model using mathematical neuronal models producing burst patterns, because it is such models are easier to study and more accessible as compared to real biological neuronal data. In this study, we use the Izhikevich neuron model to produce burst patterns and apply a recurrence plot density entropy to the Izhikevich neuron data.
{"title":"Nonlinear Time Series Analysis of Spike Data of Izhikevich Neuron Model","authors":"Y. Uwate, Y. Nishio, M. Obien, U. Frey","doi":"10.1109/ISOCC50952.2020.9333002","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333002","url":null,"abstract":"It is well known that burst patterns of neuronal networks may play an important role in information processing in the brain. We consider that it is advantageous to construct a model using mathematical neuronal models producing burst patterns, because it is such models are easier to study and more accessible as compared to real biological neuronal data. In this study, we use the Izhikevich neuron model to produce burst patterns and apply a recurrence plot density entropy to the Izhikevich neuron data.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115263155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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