Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766209
J. A. Power, S. C. Kelly, E. Griffith, M. O’Neill
Inductors are very important passive elements in many RF circuit applications. Integrated on-chip metal inductors, formed in conventional CMOS or BiCMOS technologies, suffer from performance limitations due to substrate injection through the oxide, metal resistive losses, and substrate losses due to low-resistivity substrates. These problems mean that the highest attainable inductor quality factor (Q) is significantly lower than that which can be attained from off-chip inductors. This paper details an analysis of on-chip metal inductors fabricated on a 0.6 /spl mu/m BiCMOS technology. Issues relating to test structure layout, measurement techniques, inductor composition, and inductor characterization and modeling are addressed. In addition, an analysis of the impact of inductor shape and metal thickness on inductor performance is examined.
电感器是射频电路中非常重要的无源元件。在传统CMOS或BiCMOS技术中形成的集成片上金属电感，由于衬底注入氧化物、金属电阻损耗以及低电阻衬底造成的衬底损耗而受到性能限制。这些问题意味着可获得的最高电感质量因子(Q)明显低于片外电感所能获得的质量因子。本文详细分析了以0.6 /spl μ m BiCMOS工艺制作的片上金属电感。与测试结构布局，测量技术，电感组成，电感表征和建模有关的问题被解决。此外，还分析了电感器形状和金属厚度对电感器性能的影响。
{"title":"An investigation of on-chip spiral inductors on a 0.6 /spl mu/m BiCMOS technology for RF applications","authors":"J. A. Power, S. C. Kelly, E. Griffith, M. O’Neill","doi":"10.1109/ICMTS.1999.766209","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766209","url":null,"abstract":"Inductors are very important passive elements in many RF circuit applications. Integrated on-chip metal inductors, formed in conventional CMOS or BiCMOS technologies, suffer from performance limitations due to substrate injection through the oxide, metal resistive losses, and substrate losses due to low-resistivity substrates. These problems mean that the highest attainable inductor quality factor (Q) is significantly lower than that which can be attained from off-chip inductors. This paper details an analysis of on-chip metal inductors fabricated on a 0.6 /spl mu/m BiCMOS technology. Issues relating to test structure layout, measurement techniques, inductor composition, and inductor characterization and modeling are addressed. In addition, an analysis of the impact of inductor shape and metal thickness on inductor performance is examined.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126580576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766239
P. Lambkin, N. Folan, B. Lane
A straightforward electrical technique for determining the thermal time constant of microbolometer structures is presented. An impedance measurement of a microbolometer using an LCR meter shows that the phase lag/lead reaches a maximum as a function of frequency. It is shown that the frequency of maximum phase difference is simply related to the thermal time constant.
{"title":"Simple technique for the measurement of thermal time constants of microbolometer structures","authors":"P. Lambkin, N. Folan, B. Lane","doi":"10.1109/ICMTS.1999.766239","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766239","url":null,"abstract":"A straightforward electrical technique for determining the thermal time constant of microbolometer structures is presented. An impedance measurement of a microbolometer using an LCR meter shows that the phase lag/lead reaches a maximum as a function of frequency. It is shown that the frequency of maximum phase difference is simply related to the thermal time constant.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127754804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ICMTS.1999.766245
A. van den Bosch, M. Steyaert, W. Sansen
In this paper, a very dense CMOS hexagonal transistor structure is presented. The main advantages of the transistors are the low parasitic drain and source capacitance due to the small area. The matching properties of this structure have been investigated and these results have been compared to those for traditional finger style structures. Exploiting these advantages, these transistors are very well suited for high speed applications with a demand for both good matching and small area, such as e.g. multi-bit current steering D/A converters. The test chips have been implemented in a standard 0.5 /spl mu/m CMOS technology. No adaptations to the technology have been made in order to realize the structures.
本文提出了一种非常致密的CMOS六边形晶体管结构。该晶体管的主要优点是由于面积小而具有较低的寄生漏极和源极电容。研究了这种结构的匹配特性，并将这些结果与传统手指结构的匹配特性进行了比较。利用这些优势，这些晶体管非常适合要求良好匹配和小面积的高速应用，例如多比特电流转向D/ a转换器。测试芯片已在标准的0.5 /spl μ m CMOS技术中实现。为了实现这些结构，没有对技术进行任何调整。
{"title":"A high density matched hexagonal transistor structure in standard CMOS technology for high speed applications","authors":"A. van den Bosch, M. Steyaert, W. Sansen","doi":"10.1109/ICMTS.1999.766245","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766245","url":null,"abstract":"In this paper, a very dense CMOS hexagonal transistor structure is presented. The main advantages of the transistors are the low parasitic drain and source capacitance due to the small area. The matching properties of this structure have been investigated and these results have been compared to those for traditional finger style structures. Exploiting these advantages, these transistors are very well suited for high speed applications with a demand for both good matching and small area, such as e.g. multi-bit current steering D/A converters. The test chips have been implemented in a standard 0.5 /spl mu/m CMOS technology. No adaptations to the technology have been made in order to realize the structures.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122409205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：