Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766208
C. Munro, A. Gundlach, J. Stevenson, D. W. Travis, S. Smith, N. Rankin, A. Walton
This paper presents details of a process for fabricating electrical linewidth structures over etched windows so that they potentially can be inspected with a TEM. These ELISTEMs (electrical linewidth structures for TEM) are fabricated using standard <100> silicon wafers. Measurements are compared with those obtained for conventional linewidth structures.
{"title":"The fabrication of electrical linewidth structures capable of TEM measurement using standard <100> wafers","authors":"C. Munro, A. Gundlach, J. Stevenson, D. W. Travis, S. Smith, N. Rankin, A. Walton","doi":"10.1109/ICMTS.1999.766208","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766208","url":null,"abstract":"This paper presents details of a process for fabricating electrical linewidth structures over etched windows so that they potentially can be inspected with a TEM. These ELISTEMs (electrical linewidth structures for TEM) are fabricated using standard <100> silicon wafers. Measurements are compared with those obtained for conventional linewidth structures.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127039187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766225
T. Kolding
This paper presents five different methods for performing on-wafer calibration of RF CMOS measurements. All methods are compatible with standard CMOS technology. A comparison of method performance up to 12 GHz is made with measurements on RF CMOS devices. The results verify that substrate and metallization losses must be considered to obtain high accuracy. Fixture design issues are discussed and a method for mitigating overestimation of DUT performance is suggested.
{"title":"On-wafer calibration techniques for giga-hertz CMOS measurements","authors":"T. Kolding","doi":"10.1109/ICMTS.1999.766225","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766225","url":null,"abstract":"This paper presents five different methods for performing on-wafer calibration of RF CMOS measurements. All methods are compatible with standard CMOS technology. A comparison of method performance up to 12 GHz is made with measurements on RF CMOS devices. The results verify that substrate and metallization losses must be considered to obtain high accuracy. Fixture design issues are discussed and a method for mitigating overestimation of DUT performance is suggested.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116681657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766238
F. Ingvarson, L. Ragnarsson, P. Lundgren, K. Jeppson
Bipolar transistor degradation during stress and the subsequent recovery was compared to that of ultra-thin oxide MOS structures. Heat treatment was used for recovery of both the bipolar transistors and the MOS structures, and it was found that both types of device show logarithmic recovery transients with similar temperature dependence, suggesting that the stress induced defects are related. A new accelerated characterization technique for bipolar transistors is also presented and included in the investigation. This new technique was found to induce the same type of degradation as the common reverse-bias stress with open collector, making it an attractive tool for bipolar transistor degradation assessment while maintaining a short stress time.
{"title":"Stress and recovery transients in bipolar transistors and MOS structures","authors":"F. Ingvarson, L. Ragnarsson, P. Lundgren, K. Jeppson","doi":"10.1109/ICMTS.1999.766238","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766238","url":null,"abstract":"Bipolar transistor degradation during stress and the subsequent recovery was compared to that of ultra-thin oxide MOS structures. Heat treatment was used for recovery of both the bipolar transistors and the MOS structures, and it was found that both types of device show logarithmic recovery transients with similar temperature dependence, suggesting that the stress induced defects are related. A new accelerated characterization technique for bipolar transistors is also presented and included in the investigation. This new technique was found to induce the same type of degradation as the common reverse-bias stress with open collector, making it an attractive tool for bipolar transistor degradation assessment while maintaining a short stress time.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124758893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766243
T. Mido, H. Ito, K. Asada
A compact new test structure for direct extraction of components of the capacitance matrix for multilayer interconnections is presented. In this new method, each component is directly obtained from the measurement data without any calculation as the difference between current values for driver unit and reference unit, and the total pads are kept at 8 independently of the size of target matrix. As a result of evaluation of measurement errors due to the asymmetry of the structures, this new method can measure components of capacitance matrix with femto-farad order precision.
{"title":"Test structure for direct extraction of capacitance matrix in VLSI","authors":"T. Mido, H. Ito, K. Asada","doi":"10.1109/ICMTS.1999.766243","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766243","url":null,"abstract":"A compact new test structure for direct extraction of components of the capacitance matrix for multilayer interconnections is presented. In this new method, each component is directly obtained from the measurement data without any calculation as the difference between current values for driver unit and reference unit, and the total pads are kept at 8 independently of the size of target matrix. As a result of evaluation of measurement errors due to the asymmetry of the structures, this new method can measure components of capacitance matrix with femto-farad order precision.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117013852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766210
D. Gloria, A. Perrotin, J. Carbonéro, G. Morin
High frequency test structures for bipolar devices with several guard ring configurations are described. Using these structures, the substrate effect on merit figures such as Ft and Fmax has been studied experimentally and compared to Microwave Design System (MDS) electrical simulations. A worst case for guard ring position is proposed, providing up to 15 GHz Fmax degradation.
{"title":"Substrate resistance effect on the Fmax parameter of isolated BJT in BiCMOS process","authors":"D. Gloria, A. Perrotin, J. Carbonéro, G. Morin","doi":"10.1109/ICMTS.1999.766210","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766210","url":null,"abstract":"High frequency test structures for bipolar devices with several guard ring configurations are described. Using these structures, the substrate effect on merit figures such as Ft and Fmax has been studied experimentally and compared to Microwave Design System (MDS) electrical simulations. A worst case for guard ring position is proposed, providing up to 15 GHz Fmax degradation.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116269054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766231
J. Olsson, R. Valtonen, U. Heinle, L. Vestling, A. Soderbarg, H. Norde
This paper reports a new measurement method for extraction of sub-micrometer channel lengths in DMOS transistors. The method is based on capacitance-voltage measurements of the gate to source, gate to p-base and gate to drain capacitances. A channel length of 0.3 /spl mu/m has been measured on DMOS transistors. Numerical device simulations and small-signal capacitance simulations support the results and the measurement principle.
{"title":"A capacitance-voltage measurement method for DMOS transistor channel length extraction","authors":"J. Olsson, R. Valtonen, U. Heinle, L. Vestling, A. Soderbarg, H. Norde","doi":"10.1109/ICMTS.1999.766231","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766231","url":null,"abstract":"This paper reports a new measurement method for extraction of sub-micrometer channel lengths in DMOS transistors. The method is based on capacitance-voltage measurements of the gate to source, gate to p-base and gate to drain capacitances. A channel length of 0.3 /spl mu/m has been measured on DMOS transistors. Numerical device simulations and small-signal capacitance simulations support the results and the measurement principle.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116659819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766247
B. Iñíguez, Z. Xu, T. Fjeldly, M. Shur
We describe direct extraction techniques for the most important parameters of a new physics-based polysilicon (poly-Si) TFT model, suitable for circuit simulation. The physics-based model covers all operating regimes using continuous functions, includes short-channel effects and has been validated for devices of channel lengths down to 2 /spl mu/m. In spite of a small parameter set, the model includes the necessary dependencies on channel length.
{"title":"Direct parameter extraction techniques for a new poly-Si TFT model","authors":"B. Iñíguez, Z. Xu, T. Fjeldly, M. Shur","doi":"10.1109/ICMTS.1999.766247","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766247","url":null,"abstract":"We describe direct extraction techniques for the most important parameters of a new physics-based polysilicon (poly-Si) TFT model, suitable for circuit simulation. The physics-based model covers all operating regimes using continuous functions, includes short-channel effects and has been validated for devices of channel lengths down to 2 /spl mu/m. In spite of a small parameter set, the model includes the necessary dependencies on channel length.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127252678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766230
T. Arnborg, T. Johansson
3D electromagnetic simulations and SPICE were used to model the influence of wire geometry, internal matching networks and package on the characteristics of high-power RF transistors for cellular base stations. A method for extracting the actual internal 3D geometries by applying SEM micrographs and Java software was developed. Measured transistor data was correlated with simulated data, and the importance of the contributing elements and the mutual coupling of the bond wires was demonstrated.
{"title":"3D characterization of RF power transistors","authors":"T. Arnborg, T. Johansson","doi":"10.1109/ICMTS.1999.766230","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766230","url":null,"abstract":"3D electromagnetic simulations and SPICE were used to model the influence of wire geometry, internal matching networks and package on the characteristics of high-power RF transistors for cellular base stations. A method for extracting the actual internal 3D geometries by applying SEM micrographs and Java software was developed. Measured transistor data was correlated with simulated data, and the importance of the contributing elements and the mutual coupling of the bond wires was demonstrated.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128863381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766217
N. Guillaume, M. Cresswell, R. Allen, S. C. Everist, L. W. Linholm
A modification of the standard four-point probing technique has been developed for measurement of the sheet resistance of conducting films. Although the areas of unpatterned film that are required by the new modified technique are significantly less than those normally required with standard four-point probing, the values of sheet resistance provided by the two methods are found to match. The long term goal of this work is to improve the effectiveness of electrical critical-dimension (ECD) metrology in a special application, preferably without committing large surface areas of conducting film exclusively for the purpose of sheet-resistance measurement.
{"title":"Comparison of sheet-resistance measurements obtained by standard and small-area four-point probing","authors":"N. Guillaume, M. Cresswell, R. Allen, S. C. Everist, L. W. Linholm","doi":"10.1109/ICMTS.1999.766217","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766217","url":null,"abstract":"A modification of the standard four-point probing technique has been developed for measurement of the sheet resistance of conducting films. Although the areas of unpatterned film that are required by the new modified technique are significantly less than those normally required with standard four-point probing, the values of sheet resistance provided by the two methods are found to match. The long term goal of this work is to improve the effectiveness of electrical critical-dimension (ECD) metrology in a special application, preferably without committing large surface areas of conducting film exclusively for the purpose of sheet-resistance measurement.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132718188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766248
Ping Chen, Zhihong Liu, C. Yeh, Gang Zhang, K. Nishimura, M. Shimaya, T. Komatsu
A compact SOI MOSFET model based on the Bsim3v3 bulk model with new features of effective substrate bias and transition voltage concepts to cover the transition behavior from partially-depleted to fully-depleted modes, R/sub out/ smoothing, enhanced models for impact ionization, L/sub eff/-dependent parasitic BJT and self-heating is proposed. Results obtained from this model are in excellent agreement with the experimental I-V, C-V and propagation-delay time data.
{"title":"A compact SOI model for fully-depleted and partially-depleted 0.25 /spl mu/m SIMOX devices","authors":"Ping Chen, Zhihong Liu, C. Yeh, Gang Zhang, K. Nishimura, M. Shimaya, T. Komatsu","doi":"10.1109/ICMTS.1999.766248","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766248","url":null,"abstract":"A compact SOI MOSFET model based on the Bsim3v3 bulk model with new features of effective substrate bias and transition voltage concepts to cover the transition behavior from partially-depleted to fully-depleted modes, R/sub out/ smoothing, enhanced models for impact ionization, L/sub eff/-dependent parasitic BJT and self-heating is proposed. Results obtained from this model are in excellent agreement with the experimental I-V, C-V and propagation-delay time data.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114077093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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