Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766249
S. Healy, E. Horan, K. McCarthy, A. Mathewson, Z. Ning, E. Rombouts, W. Vanderbauwhede, M. Tack
This paper presents a methodology for statistical worst-case simulation using the BSIM3v3 model within commercially available tools. Statistical techniques such as principal component analysis and Box-Behnken designs are used to generate a subset of models which reflect the variation of measured device performance. These worst-case corners can be used in circuit simulation to account for the effects of statistical fluctuation on circuit performance. An indication of key process parameters that need to be monitored and controlled is also provided.
{"title":"Implementation of statistical characterisation and design techniques for an industrial 0.5 /spl mu/m CMOS technology","authors":"S. Healy, E. Horan, K. McCarthy, A. Mathewson, Z. Ning, E. Rombouts, W. Vanderbauwhede, M. Tack","doi":"10.1109/ICMTS.1999.766249","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766249","url":null,"abstract":"This paper presents a methodology for statistical worst-case simulation using the BSIM3v3 model within commercially available tools. Statistical techniques such as principal component analysis and Box-Behnken designs are used to generate a subset of models which reflect the variation of measured device performance. These worst-case corners can be used in circuit simulation to account for the effects of statistical fluctuation on circuit performance. An indication of key process parameters that need to be monitored and controlled is also provided.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126730311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766215
R. Allen, E. Vogel, L. W. Linholm, M. Cresswell
Recently, NIST has been developing electrical test structures to serve as critical dimension (CD) reference artifacts for calibration of CD metrology systems. The reference artifacts are fabricated in monocrystalline silicon-on-insulator films and are responsive to the goals of the National Technology Roadmap for Semiconductors beyond the 120 nm generation. The features on these reference artifacts are produced with lattice-plane specific etch techniques which give vertical, atomically planar sidewalls and uniform conductivity. The electrical linewidths, or electrical CDs (ECDs), of these features are determined from the sheet resistance and the resistance of the feature. This paper reports on measurements and models of how the resistance per unit length changes as a function of substrate bias, providing a method to validate the calculated sheet resistance and linewidth, and thus facilitating the use of this uniquely high repeatability and low-cost metrology tool in the production of CD-reference artifacts.
{"title":"Sheet and line resistance of patterned SOI surface film CD reference materials as a function of substrate bias","authors":"R. Allen, E. Vogel, L. W. Linholm, M. Cresswell","doi":"10.1109/ICMTS.1999.766215","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766215","url":null,"abstract":"Recently, NIST has been developing electrical test structures to serve as critical dimension (CD) reference artifacts for calibration of CD metrology systems. The reference artifacts are fabricated in monocrystalline silicon-on-insulator films and are responsive to the goals of the National Technology Roadmap for Semiconductors beyond the 120 nm generation. The features on these reference artifacts are produced with lattice-plane specific etch techniques which give vertical, atomically planar sidewalls and uniform conductivity. The electrical linewidths, or electrical CDs (ECDs), of these features are determined from the sheet resistance and the resistance of the feature. This paper reports on measurements and models of how the resistance per unit length changes as a function of substrate bias, providing a method to validate the calculated sheet resistance and linewidth, and thus facilitating the use of this uniquely high repeatability and low-cost metrology tool in the production of CD-reference artifacts.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114743978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766224
G. Persiano
This paper describes the use and the design of a microelectronic test structure to show a new fast and simple DC method for measuring the dependence of carrier mobilities upon carrier concentration. The test structure is designed for reducing parasitic effects and providing reliable results up to the highest carrier concentrations. Numerical simulation is used for verification of the accuracy of the method for several test structure parameters. Experimental results are provided and represented by a simple fitting formula.
{"title":"Test structure design for a fast and simple evaluation of carrier mobilities in highly injected regions","authors":"G. Persiano","doi":"10.1109/ICMTS.1999.766224","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766224","url":null,"abstract":"This paper describes the use and the design of a microelectronic test structure to show a new fast and simple DC method for measuring the dependence of carrier mobilities upon carrier concentration. The test structure is designed for reducing parasitic effects and providing reliable results up to the highest carrier concentrations. Numerical simulation is used for verification of the accuracy of the method for several test structure parameters. Experimental results are provided and represented by a simple fitting formula.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124198162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766214
R. A. Ashton
Van der Pauw test structures for the measurement of N-well sheet resistance under p/sup +/ diffusion and under p channel gate for CMOS technologies on p substrates are presented.
提出了在p基板上测量p/sup +/扩散和p通道栅极下的n阱片电阻的Van der Pauw测试结构。
{"title":"Measurement of N-well sheet resistance under p/sup +/ diffusion and p channel gate","authors":"R. A. Ashton","doi":"10.1109/ICMTS.1999.766214","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766214","url":null,"abstract":"Van der Pauw test structures for the measurement of N-well sheet resistance under p/sup +/ diffusion and under p channel gate for CMOS technologies on p substrates are presented.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129449808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766221
T. Boutchacha, G. Ghibaudo, B. Belmekki
The low frequency noise in 0.18 /spl mu/m NMOS and PMOS devices is investigated. The devices used throughout this work have been fabricated according to a dual CMOS process with N/sup +/ and P/sup +/ polysilicon metal gate and retrograde well. Prior to the noise analysis, the static characteristics of the devices were measured with an HP 4155 semiconductor parameter analyzer. Subsequently, a theoretical analysis of the drain current noise and the gate voltage noise characteristics is developed in the framework of the carrier number fluctuation model as well as the correlated fluctuation in the mobility model. It is shown experimentally that a close correlation between the drain current spectral density and the transconductance squared dependencies with gate voltage (or drain current) is observed in NMOS devices over a wide current drain. Besides, it is worth mentioning that for the PMOS transistors, there is a significant departure of the noise level from the (g/sub m//I/sub d/)/sup 2/ variation at strong inversion which can be attributed to the correlated mobility fluctuations model. We have developed a simulation based on these flicker noise models and compared the results with experimental noise data. Excellent agreement between the calculations and measurements was observed in the ohmic regime.
{"title":"Study of low frequency noise in the 0.18 /spl mu/m silicon CMOS transistors","authors":"T. Boutchacha, G. Ghibaudo, B. Belmekki","doi":"10.1109/ICMTS.1999.766221","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766221","url":null,"abstract":"The low frequency noise in 0.18 /spl mu/m NMOS and PMOS devices is investigated. The devices used throughout this work have been fabricated according to a dual CMOS process with N/sup +/ and P/sup +/ polysilicon metal gate and retrograde well. Prior to the noise analysis, the static characteristics of the devices were measured with an HP 4155 semiconductor parameter analyzer. Subsequently, a theoretical analysis of the drain current noise and the gate voltage noise characteristics is developed in the framework of the carrier number fluctuation model as well as the correlated fluctuation in the mobility model. It is shown experimentally that a close correlation between the drain current spectral density and the transconductance squared dependencies with gate voltage (or drain current) is observed in NMOS devices over a wide current drain. Besides, it is worth mentioning that for the PMOS transistors, there is a significant departure of the noise level from the (g/sub m//I/sub d/)/sup 2/ variation at strong inversion which can be attributed to the correlated mobility fluctuations model. We have developed a simulation based on these flicker noise models and compared the results with experimental noise data. Excellent agreement between the calculations and measurements was observed in the ohmic regime.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"604 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116452666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766220
S. Bellone, S. Daliento, A. Sanseverino
In this paper, the capability of a new test pattern for extraction of both the intrinsic series resistance and the injection level of power diodes is presented. The method is based on the measurement of the DC voltage manifesting at a sensing region placed near the active device. Two dimensional simulations showing the correct operation of the test structure are reported. Finally, experimental results obtained on fabricated diodes are presented.
{"title":"A special test structure for the measurement of the injection dependent series resistance of power diodes","authors":"S. Bellone, S. Daliento, A. Sanseverino","doi":"10.1109/ICMTS.1999.766220","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766220","url":null,"abstract":"In this paper, the capability of a new test pattern for extraction of both the intrinsic series resistance and the injection level of power diodes is presented. The method is based on the measurement of the DC voltage manifesting at a sensing region placed near the active device. Two dimensional simulations showing the correct operation of the test structure are reported. Finally, experimental results obtained on fabricated diodes are presented.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"319 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132420989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766240
H. Kanata, Y. Tosaka, H. Ehara, S. Satoh
The stopping powers of various ions in Si are essential for simulation of the soft errors of Si devices induced especially by secondary cosmic-ray neutrons. A new method has been developed for measuring ion stopping powers in Si that employs diodes fabricated on the SOI structure. This technique was applied to He/sup 2+/ ions, and the obtained stopping power was in good agreement with that obtained from the well known Ziegler formula.
{"title":"Test structure for measurement of ion stopping power","authors":"H. Kanata, Y. Tosaka, H. Ehara, S. Satoh","doi":"10.1109/ICMTS.1999.766240","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766240","url":null,"abstract":"The stopping powers of various ions in Si are essential for simulation of the soft errors of Si devices induced especially by secondary cosmic-ray neutrons. A new method has been developed for measuring ion stopping powers in Si that employs diodes fabricated on the SOI structure. This technique was applied to He/sup 2+/ ions, and the obtained stopping power was in good agreement with that obtained from the well known Ziegler formula.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124289683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766236
S. Smith, A. Walton, M. Fallon
The effect of optical proximity correction (OPC) on test structures is examined using DEPICT for the lithography simulation and MEDICI for the electrical calculations. It is concluded that OPC can be successfully used to reduce line shortening due to the voltage taps without causing necking effects on the track being measured. The effect of asymmetries (which may be introduced as a result of OPC) on the measurement of Greek crosses are also addressed and methods of accurately extracting sheet resistance from structures exhibiting these effects are discussed.
{"title":"Investigation of optical proximity correction (OPC) and non-uniformities on the performance of resistivity and linewidth measurements","authors":"S. Smith, A. Walton, M. Fallon","doi":"10.1109/ICMTS.1999.766236","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766236","url":null,"abstract":"The effect of optical proximity correction (OPC) on test structures is examined using DEPICT for the lithography simulation and MEDICI for the electrical calculations. It is concluded that OPC can be successfully used to reduce line shortening due to the voltage taps without causing necking effects on the track being measured. The effect of asymmetries (which may be introduced as a result of OPC) on the measurement of Greek crosses are also addressed and methods of accurately extracting sheet resistance from structures exhibiting these effects are discussed.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132738006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766229
S. Sekine, M. Sugiyama, N. Saito
In this paper, we present a new physics-based model for narrow width MOSFETs that accounts for the LOCOS narrow width effect and the webbing effect. The model is based on physical geometry changes of MOSFETs that are caused by the changes in field edge shape during LOCOS isolation and consecutive oxide etch, and the webbing effect of lithography for the dog-bone layout. It allows the use of a single set of parameters for any combination of MOSFET widths and lengths without geometry binning. We also discuss details of the test structures and the modeling procedure, and model implementation in SPICE simulation.
{"title":"Geometry modeling method for narrow/short and narrow MOSFETs","authors":"S. Sekine, M. Sugiyama, N. Saito","doi":"10.1109/ICMTS.1999.766229","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766229","url":null,"abstract":"In this paper, we present a new physics-based model for narrow width MOSFETs that accounts for the LOCOS narrow width effect and the webbing effect. The model is based on physical geometry changes of MOSFETs that are caused by the changes in field edge shape during LOCOS isolation and consecutive oxide etch, and the webbing effect of lithography for the dog-bone layout. It allows the use of a single set of parameters for any combination of MOSFET widths and lengths without geometry binning. We also discuss details of the test structures and the modeling procedure, and model implementation in SPICE simulation.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134159022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766227
Y. Maneglia, D. Bauza
Using a recently proposed method based on charge pumping measurements which allows the extraction of the Si-SiO/sub 2/ interface trap depth concentration profiles, the trap parameters are studied as a function of Fowler-Nordheim injection. As the stress proceeds, the interface trap layer extends deeper in the direction of the oxide depth, the trap density in the oxide seems to increase faster than that at the interface and the trap capture cross-sections strongly increase. This induces deeper penetration of the carriers into the oxide depth and a larger contribution of the so-called slow traps to the device electrical properties. This can be viewed as an extension of the Si-SiO/sub 2/ interface in the direction of the oxide depth.
{"title":"Evolution of the Si-SiO/sub 2/ interface trap characteristics with Fowler-Nordheim injection","authors":"Y. Maneglia, D. Bauza","doi":"10.1109/ICMTS.1999.766227","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766227","url":null,"abstract":"Using a recently proposed method based on charge pumping measurements which allows the extraction of the Si-SiO/sub 2/ interface trap depth concentration profiles, the trap parameters are studied as a function of Fowler-Nordheim injection. As the stress proceeds, the interface trap layer extends deeper in the direction of the oxide depth, the trap density in the oxide seems to increase faster than that at the interface and the trap capture cross-sections strongly increase. This induces deeper penetration of the carriers into the oxide depth and a larger contribution of the so-called slow traps to the device electrical properties. This can be viewed as an extension of the Si-SiO/sub 2/ interface in the direction of the oxide depth.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123791528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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