Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094148
Yu-Fa Tu, T. Chang, Kuan-Ju Zhou, W. Hung, Ting-Tzu Kuo, Chen‐Hsin Lien
In this study, a unique supercritical fluid (SCF) treatment is utilized to improve the resonance properties of thin film bulk acoustic resonators (FBARs) composed of a piezoelectric material of AlN. In an etching process of the sacrificial oxide, FBARs suffered from severe surface tension of etching acid solvent, resulting in structural bonding and residues generation. These impact on FABR’s structural integrity would influence its resonance properties. Therefore, a SCF treatment with low surface tension and high penetrability can effectively carry out residues from the release gap in a FBAR, observed from SEM images. The results show that the reflection coefficient, the quality factor, and the effective coupling coefficient are all improved in FABRs.
{"title":"Improving Performance of FBARs by Advanced Low-Temperature High-Pressure Technology","authors":"Yu-Fa Tu, T. Chang, Kuan-Ju Zhou, W. Hung, Ting-Tzu Kuo, Chen‐Hsin Lien","doi":"10.1109/ICMTS55420.2023.10094148","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094148","url":null,"abstract":"In this study, a unique supercritical fluid (SCF) treatment is utilized to improve the resonance properties of thin film bulk acoustic resonators (FBARs) composed of a piezoelectric material of AlN. In an etching process of the sacrificial oxide, FBARs suffered from severe surface tension of etching acid solvent, resulting in structural bonding and residues generation. These impact on FABR’s structural integrity would influence its resonance properties. Therefore, a SCF treatment with low surface tension and high penetrability can effectively carry out residues from the release gap in a FBAR, observed from SEM images. The results show that the reflection coefficient, the quality factor, and the effective coupling coefficient are all improved in FABRs.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125658942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094063
H. Tuinhout, Oliver Dieball
This paper discusses the so called Pressing Probe Needle (PPN) technique for characterizing out-of-plane mechanical stress sensitivity of arbitrary semiconductor devices, implemented on a standard parametric test system. By utilizing a motorized probe positioner and a force calibrated standard tungsten parametric probe needle, this fast and highspatial-resolution technique provides valuable insights into mechanical stress effects of process and device layout options. Such results are highly beneficial for high-precision analog circuit design and layout optimization.
{"title":"The Pressing Probe Needle Technique for Characterizing Mechanical Stress Sensitivity of Semiconductor Devices","authors":"H. Tuinhout, Oliver Dieball","doi":"10.1109/ICMTS55420.2023.10094063","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094063","url":null,"abstract":"This paper discusses the so called Pressing Probe Needle (PPN) technique for characterizing out-of-plane mechanical stress sensitivity of arbitrary semiconductor devices, implemented on a standard parametric test system. By utilizing a motorized probe positioner and a force calibrated standard tungsten parametric probe needle, this fast and highspatial-resolution technique provides valuable insights into mechanical stress effects of process and device layout options. Such results are highly beneficial for high-precision analog circuit design and layout optimization.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127138156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094164
T. Knežević, L. Nanver
In silicon technology, Schottky diodes mainly exhibit high current levels, and attempts are regularly made to reduce these by introducing 2D layers between the metal contact and the silicon. Defects in such interfacial layers, from weakly bonded structures to actual pinholes, can lead to high, localized metal-semiconductor Schottky currents. Using the example of diodes with an interfacial layer of pure boron (PureB) between an aluminum metallization layer and the Si, a signature for such ‘‘nano-Schottky’s’’ is determined by evaluating the results of several different test-structure arrays and measurement techniques. An adapted bipolar-type measurement is introduced as an additional method to determine whether any high current characteristics originate from a low Schottky barrier height over the entire diode surface or from a localized nano-Schottky structure.
{"title":"Identifying nano-Schottky diode currents in silicon diodes with 2D interfacial layers","authors":"T. Knežević, L. Nanver","doi":"10.1109/ICMTS55420.2023.10094164","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094164","url":null,"abstract":"In silicon technology, Schottky diodes mainly exhibit high current levels, and attempts are regularly made to reduce these by introducing 2D layers between the metal contact and the silicon. Defects in such interfacial layers, from weakly bonded structures to actual pinholes, can lead to high, localized metal-semiconductor Schottky currents. Using the example of diodes with an interfacial layer of pure boron (PureB) between an aluminum metallization layer and the Si, a signature for such ‘‘nano-Schottky’s’’ is determined by evaluating the results of several different test-structure arrays and measurement techniques. An adapted bipolar-type measurement is introduced as an additional method to determine whether any high current characteristics originate from a low Schottky barrier height over the entire diode surface or from a localized nano-Schottky structure.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134403975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094064
Yu-Hsing Cheng
The use of polysilicon heater structures provides a useful tool for fast NBTI monitoring of wafer level reliability in production measurements. It could reduce device relaxation in NBTI measurement without special ultra-fast test equipment. In this work NBTI characterization from a parametric tester using polysilicon heater test structures for 1.2V PMOS devices placed in the scribe line of a 65 nm BCD technology was performed with real-time feedback temperature control methodology without changing the chuck temperature to realize NBTI reliability assessment with a short test time.
{"title":"Wafer Level Reliability Monitoring of NBTI Using Polysilicon Heater Structures for Production Measurements","authors":"Yu-Hsing Cheng","doi":"10.1109/ICMTS55420.2023.10094064","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094064","url":null,"abstract":"The use of polysilicon heater structures provides a useful tool for fast NBTI monitoring of wafer level reliability in production measurements. It could reduce device relaxation in NBTI measurement without special ultra-fast test equipment. In this work NBTI characterization from a parametric tester using polysilicon heater test structures for 1.2V PMOS devices placed in the scribe line of a 65 nm BCD technology was performed with real-time feedback temperature control methodology without changing the chuck temperature to realize NBTI reliability assessment with a short test time.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122939192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094099
L. Laborie, Paola Trotti, Killian Veyret, C. Cagli
This work presents a novel, discrete-component circuit for the electrical characterisation of Resistive Random Access Memory (RRAM). The forming of State-Of-The-Art RRAM cell in one resistor (1R) configuration is demonstrated, enabling the possibility of sparing the commonly integrated series transistor. The presented DCL circuit is furthermore benchmarked versus other discrete and integrated typologies, showing dramatic improvement over existing discrete solutions, and comparable performances with integrated architectures. Finally, multi-bit storage is experimentally demonstrated through modulation of the programming current amplitude.
{"title":"Discrete current limiting circuit for emerging memory programming","authors":"L. Laborie, Paola Trotti, Killian Veyret, C. Cagli","doi":"10.1109/ICMTS55420.2023.10094099","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094099","url":null,"abstract":"This work presents a novel, discrete-component circuit for the electrical characterisation of Resistive Random Access Memory (RRAM). The forming of State-Of-The-Art RRAM cell in one resistor (1R) configuration is demonstrated, enabling the possibility of sparing the commonly integrated series transistor. The presented DCL circuit is furthermore benchmarked versus other discrete and integrated typologies, showing dramatic improvement over existing discrete solutions, and comparable performances with integrated architectures. Finally, multi-bit storage is experimentally demonstrated through modulation of the programming current amplitude.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121987146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094071
D. Navarro, C. Tanaka, K. Adachi, Takeshi Naito, Kenshi Tada, A. Hokazono
Models for parasitic capacitances in the MOSFET overlap region are developed for circuit simulation. In particular, the overlap capacitance ($C_{mathrm{o}mathrm{v}}$) model considers the modulation of the overlap length due to the dynamic depletion of channel/LDDjunction, which is the physical origin of the $C_{mathrm{o}mathrm{v}}$ bias-dependence. The models are implemented in Verilog-A, and incorporated in a MOSFET model for circuit simulation. Reproduction of device simulation results and RF-CMOS gatedrain capacitance measurements are verified.
{"title":"Technology-Dependent Modeling of MOSFET Parasitic Capacitances for Circuit Simulation","authors":"D. Navarro, C. Tanaka, K. Adachi, Takeshi Naito, Kenshi Tada, A. Hokazono","doi":"10.1109/ICMTS55420.2023.10094071","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094071","url":null,"abstract":"Models for parasitic capacitances in the MOSFET overlap region are developed for circuit simulation. In particular, the overlap capacitance ($C_{mathrm{o}mathrm{v}}$) model considers the modulation of the overlap length due to the dynamic depletion of channel/LDDjunction, which is the physical origin of the $C_{mathrm{o}mathrm{v}}$ bias-dependence. The models are implemented in Verilog-A, and incorporated in a MOSFET model for circuit simulation. Reproduction of device simulation results and RF-CMOS gatedrain capacitance measurements are verified.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127744224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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