Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094125
Ting-Tzu Kuo, Ying-Chung Chen, T. Chang, Fong-Min Ciou, C. Yeh, Po-Hsun Chen, S. Sze
This work proposed extended methods, which can analyze kinds of defects more easily with power spectrum density (PSD) and weighted time lag plot (W-TLP), to decouple single or multi-traps. To get additional high voltage tolerance, it is common to design different kinds of structures dispersing the electric field. In this work, boron and fluorine were doped in the source and drain extension regions to achieve higher voltage operation. However, boron diffusion could worsen the interface quality. Interestingly, after different stress conditions of hot carrier degradation (HCD) and positive bias temperature instability (PBTI), the degradation trends of the two devices show opposite behaviors. It is because the boron can bear the high voltage operation, but also weak the devices’ interface quality. Therefore, to analyze the influence of these defects plays an important role. With Agilent B1530A WGFMU and RTSDataAnalysis software, varied defects response to frequency can be simply detected. It can also use W-TLP to decouple single trap and multi-traps behaviors at the same time.
{"title":"An Extended Method to Analyze Boron Diffusion Defects in 16 nm Node High-Voltage FinFETs","authors":"Ting-Tzu Kuo, Ying-Chung Chen, T. Chang, Fong-Min Ciou, C. Yeh, Po-Hsun Chen, S. Sze","doi":"10.1109/ICMTS55420.2023.10094125","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094125","url":null,"abstract":"This work proposed extended methods, which can analyze kinds of defects more easily with power spectrum density (PSD) and weighted time lag plot (W-TLP), to decouple single or multi-traps. To get additional high voltage tolerance, it is common to design different kinds of structures dispersing the electric field. In this work, boron and fluorine were doped in the source and drain extension regions to achieve higher voltage operation. However, boron diffusion could worsen the interface quality. Interestingly, after different stress conditions of hot carrier degradation (HCD) and positive bias temperature instability (PBTI), the degradation trends of the two devices show opposite behaviors. It is because the boron can bear the high voltage operation, but also weak the devices’ interface quality. Therefore, to analyze the influence of these defects plays an important role. With Agilent B1530A WGFMU and RTSDataAnalysis software, varied defects response to frequency can be simply detected. It can also use W-TLP to decouple single trap and multi-traps behaviors at the same time.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114661446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094087
Owen Gauthier, S. Haendler, Ronan Beucher, P. Scheer, Q. Rafhay, C. Theodorou
The use of an addressable array test structure designed on a 28 nm FD-SOI technology for the variability analysis of static, low frequency noise (LFN) and Random Telegraph Noise (RTN) matching is presented. The experimental setup was validated, and a statistical analysis of the above electrical quantities is provided. Using such structures, combined with a switching matrix, local and global variability analysis can be performed while significantly increasing the number of samples, thus enabling a better description of the variations in LFN and RTN, especially when RTN signatures can be scarce. We show that local variations dominate the noise variability compared to global variations.
{"title":"Static and LFN/RTN Local and Global Variability Analysis Using an Addressable Array Test Structure","authors":"Owen Gauthier, S. Haendler, Ronan Beucher, P. Scheer, Q. Rafhay, C. Theodorou","doi":"10.1109/ICMTS55420.2023.10094087","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094087","url":null,"abstract":"The use of an addressable array test structure designed on a 28 nm FD-SOI technology for the variability analysis of static, low frequency noise (LFN) and Random Telegraph Noise (RTN) matching is presented. The experimental setup was validated, and a statistical analysis of the above electrical quantities is provided. Using such structures, combined with a switching matrix, local and global variability analysis can be performed while significantly increasing the number of samples, thus enabling a better description of the variations in LFN and RTN, especially when RTN signatures can be scarce. We show that local variations dominate the noise variability compared to global variations.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132404944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094130
Surachoke Thanapitak, P. Sedtheetorn, Pornchai Chanyagorn, T. Chulajata, Somnida Bhatranand, P. Phattanasri
A practical test bench for dry electrode bio-signal instrumentation amplifier is presented and demonstrated. By modifying the on-the-shelf single-ended to differential amplifier, the common-mode rejection ratio and distortion under electrodes offset scenario can be characterized. The other essential parameters such as input impedance and power supply rejection ratio can also be determined.
{"title":"Test Bench for Biopotential Instrumentation Amplifier using Single-Ended to Differential Amplifiers","authors":"Surachoke Thanapitak, P. Sedtheetorn, Pornchai Chanyagorn, T. Chulajata, Somnida Bhatranand, P. Phattanasri","doi":"10.1109/ICMTS55420.2023.10094130","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094130","url":null,"abstract":"A practical test bench for dry electrode bio-signal instrumentation amplifier is presented and demonstrated. By modifying the on-the-shelf single-ended to differential amplifier, the common-mode rejection ratio and distortion under electrodes offset scenario can be characterized. The other essential parameters such as input impedance and power supply rejection ratio can also be determined.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"323 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121250685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094127
Kohei Oasa, T. Nishiwaki, T. Ohguro, Yasunobu Saito, Y. Kawaguchi
To accelerate the development of low voltage MOSFET, we designed a test element group pattern that enables on-resistance measurement at wafer level. We confirmed that the on-resistance can be measured at wafer level by optimizing the device size and contact method to eliminate the influence of parasitic resistance.
{"title":"On-Resistance Measurements of Low Voltage MOSFET at wafer level","authors":"Kohei Oasa, T. Nishiwaki, T. Ohguro, Yasunobu Saito, Y. Kawaguchi","doi":"10.1109/ICMTS55420.2023.10094127","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094127","url":null,"abstract":"To accelerate the development of low voltage MOSFET, we designed a test element group pattern that enables on-resistance measurement at wafer level. We confirmed that the on-resistance can be measured at wafer level by optimizing the device size and contact method to eliminate the influence of parasitic resistance.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125966974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094166
N. Yazigy, J. Postel-Pellerin, V. D. Marca, R. C. Sousa, Anne-Lise Ribotta, G. D. Pendina, P. Canet
The goal of the study is to monitor the device’s response during laser injection while being able to track pre- and post-attack conditions. We show the irradiation power affects the STT-MRAM behavior. Our electrical/optical setup enables to know the memory cell behavior to study real-time laser attack countermeasures and device reliability. We have highlighted the possibility to switch, to degrade or even to destruct the cell, depending on the laser power.
{"title":"Real-time electrical measurements during laser attack on STT-MRAM","authors":"N. Yazigy, J. Postel-Pellerin, V. D. Marca, R. C. Sousa, Anne-Lise Ribotta, G. D. Pendina, P. Canet","doi":"10.1109/ICMTS55420.2023.10094166","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094166","url":null,"abstract":"The goal of the study is to monitor the device’s response during laser injection while being able to track pre- and post-attack conditions. We show the irradiation power affects the STT-MRAM behavior. Our electrical/optical setup enables to know the memory cell behavior to study real-time laser attack countermeasures and device reliability. We have highlighted the possibility to switch, to degrade or even to destruct the cell, depending on the laser power.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129525270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094096
Minxing Zhang, Shan Zhang, C. Dunare, J. Marland, J. Terry, Stewart Smith
Using a test structure chip designed to assist in process development for reference electrode fabrication for integrated electrochemical sensors, this paper reports measurements of Greek cross test structures and compares them to measurements of bridge resistor structures on the same chip. The correct application of these structures requires careful consideration of the measurement parameters to provide accurate results and different force current values have been investigated. Results from platinum structures suggest there is measureable variation in the feature size when Greek cross results are used to extract electrical critical dimension from the bridge resistor measurements. Similar measurements of silver structures were less conclusive. While the bridge structures show a significant effect of oxidation of silver which has been exposed to air since fabrication, the Greek cross results are highly variable and may not be reliable.
{"title":"Application of Greek cross structures for process development of electrochemical sensors","authors":"Minxing Zhang, Shan Zhang, C. Dunare, J. Marland, J. Terry, Stewart Smith","doi":"10.1109/ICMTS55420.2023.10094096","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094096","url":null,"abstract":"Using a test structure chip designed to assist in process development for reference electrode fabrication for integrated electrochemical sensors, this paper reports measurements of Greek cross test structures and compares them to measurements of bridge resistor structures on the same chip. The correct application of these structures requires careful consideration of the measurement parameters to provide accurate results and different force current values have been investigated. Results from platinum structures suggest there is measureable variation in the feature size when Greek cross results are used to extract electrical critical dimension from the bridge resistor measurements. Similar measurements of silver structures were less conclusive. While the bridge structures show a significant effect of oxidation of silver which has been exposed to air since fabrication, the Greek cross results are highly variable and may not be reliable.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129686625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094167
R. Tambone, A. Ferrara, F. Magrini, A. Hoffmann, A. Wood, G. Noebauer, E. Gondro, R. Hueting
Fast electric transients can cause distributed effects inside trench MOSFETs possibly resulting in device failure. A new test structure to study those distributed effects, combined with a new Transmission-Line Pulse (TLP) setup, is presented. On-wafer TLP measurements are performed and combined with TCAD and SPICE simulations to predict the space and time evolution of the field plate potential during transients.
{"title":"Distributed field plate effects in split-gate trench MOSFETs","authors":"R. Tambone, A. Ferrara, F. Magrini, A. Hoffmann, A. Wood, G. Noebauer, E. Gondro, R. Hueting","doi":"10.1109/ICMTS55420.2023.10094167","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094167","url":null,"abstract":"Fast electric transients can cause distributed effects inside trench MOSFETs possibly resulting in device failure. A new test structure to study those distributed effects, combined with a new Transmission-Line Pulse (TLP) setup, is presented. On-wafer TLP measurements are performed and combined with TCAD and SPICE simulations to predict the space and time evolution of the field plate potential during transients.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127427110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094187
Shufan Xu, Kunyang Liu, Yichen Tang, Ruilin Zhang, H. Shinohara
This article presents a bitcell of a static randomaccess memory (SRAM)-based physically unclonable function (PUF) with quadruple-size transistor, which reduces the tail’ of mismatch distribution after hot carrier injection (HCI) burn-in. A statistical mismatch distribution model after HCI application for a certain time is proposed by combining native mismatch distribution before HCI and mismatch shift distribution after HCI. Model calculation shows that quadruple-size transistor SRAM PUF needs 15-min HCI burn-in time to achieve cryptographic level requirement, which is more than 3 times shorter than normal-size transistor SRAM PUF of 46-min. The effect of utilizing the quadruple-size transistor with respect to HCI burn-in for stability reinforcement is also confirmed by measuring chips fabricated in a 130-nm CMOS process. Experimental results show that the ‘tail’ in mismatch distribution is significantly eliminated after 18-min HCI burnin time of quadruple-size transistor SRAM PUF, which meets our expectations. The presented statistical model also matches the measurement data well.
{"title":"Effect of Quadruple Size Transistor on SRAM Physically Unclonable Function Stabilized by Hot Carrier Injection","authors":"Shufan Xu, Kunyang Liu, Yichen Tang, Ruilin Zhang, H. Shinohara","doi":"10.1109/ICMTS55420.2023.10094187","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094187","url":null,"abstract":"This article presents a bitcell of a static randomaccess memory (SRAM)-based physically unclonable function (PUF) with quadruple-size transistor, which reduces the tail’ of mismatch distribution after hot carrier injection (HCI) burn-in. A statistical mismatch distribution model after HCI application for a certain time is proposed by combining native mismatch distribution before HCI and mismatch shift distribution after HCI. Model calculation shows that quadruple-size transistor SRAM PUF needs 15-min HCI burn-in time to achieve cryptographic level requirement, which is more than 3 times shorter than normal-size transistor SRAM PUF of 46-min. The effect of utilizing the quadruple-size transistor with respect to HCI burn-in for stability reinforcement is also confirmed by measuring chips fabricated in a 130-nm CMOS process. Experimental results show that the ‘tail’ in mismatch distribution is significantly eliminated after 18-min HCI burnin time of quadruple-size transistor SRAM PUF, which meets our expectations. The presented statistical model also matches the measurement data well.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"203 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128403943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094054
Toshihiro Takada, Takayuki Mori, J. Ida
The variability of the neuronal function device of a metal oxide semiconductor-gated PNPN diode was evaluated. The variability of neurons is known to affect the inference accuracy of spiking neural networks (SNNs). The device has stochastic operation on its own, and the spike frequency can be controlled by the gate voltage, which has the possibility to improve the accuracy of SNNs.
{"title":"Variability Evaluation of MOS-gated PNPN Diode for Hardware Spiking Neural Network","authors":"Toshihiro Takada, Takayuki Mori, J. Ida","doi":"10.1109/ICMTS55420.2023.10094054","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094054","url":null,"abstract":"The variability of the neuronal function device of a metal oxide semiconductor-gated PNPN diode was evaluated. The variability of neurons is known to affect the inference accuracy of spiking neural networks (SNNs). The device has stochastic operation on its own, and the spike frequency can be controlled by the gate voltage, which has the possibility to improve the accuracy of SNNs.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130739181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094069
T. Hara, S. Nakajima, T. Ohguro, K. Miyashita
We provide the method to estimate intrinsic Qrr ($Q_{r_{-}text{int}})$ without parasitic inductance in the measurement system for the first time. In this paper, we analyze parasitic inductance dependence of Qrr by TCAD simulation and we propose the method for removing the parasitic inductance effect as well as calculating the carrier of recombination and discharge (qr_into).
{"title":"New Extraction Method for Intrinsic Qrr of Power MOSFETs","authors":"T. Hara, S. Nakajima, T. Ohguro, K. Miyashita","doi":"10.1109/ICMTS55420.2023.10094069","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094069","url":null,"abstract":"We provide the method to estimate intrinsic Qrr ($Q_{r_{-}text{int}})$ without parasitic inductance in the measurement system for the first time. In this paper, we analyze parasitic inductance dependence of Qrr by TCAD simulation and we propose the method for removing the parasitic inductance effect as well as calculating the carrier of recombination and discharge (qr_into).","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134152987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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