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2023 35th International Conference on Microelectronic Test Structure (ICMTS)最新文献

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Damage Assessment Structure of Thermal-Annealing Post-Processing on CMOS LSIs CMOS lsi热退火后处理损伤评估结构
Pub Date : 2023-03-27 DOI: 10.1109/ICMTS55420.2023.10094159
Yuki Okamoto, N. Makimoto, Kei Misumi, Takeshi Kobayashi, Y. Mita, M. Ichiki
We assessed the degradation of MOSFET and CMOS LSI circuit characteristics induced by the high temperature annealing, especially for the PZT deposition process. The test structure consists of ring oscillators having different numbers of stages and single PMOSFETs and NMOEFETs designed with $0.6 mu mathrm{m}$ CMOS technology. We observed the ring oscillator (RO) oscillating frequencies and the $I_{mathrm{d}}-V_{mathrm{g}}$ characteristics of the MOSFETs before and after the annealing post-process. The result indicated that such an annealing process involving high temperatures of around 575°C is possible unless the wiring on the CMOS components is mechanically broken. In addition, annealing temperature affected the MOSFET characteristics more than annealing times. Therefore, the effects of the CMOSMEMS monolithic integration using PZT thin films be optimized using the proposed test structures.
我们评估了高温退火引起的MOSFET和CMOS LSI电路特性的退化,特别是PZT沉积过程。测试结构由不同级数的环形振荡器和采用$0.6 mu mathm {m}$ CMOS技术设计的单pmosfet和nmoefet组成。我们观察了退火后处理前后mosfet的环形振荡器(RO)振荡频率和$I_{mathrm{d}}-V_{mathrm{g}}$特性。结果表明,除非CMOS元件上的布线机械断裂,否则这种涉及575℃左右高温的退火过程是可能的。此外,退火温度对MOSFET特性的影响大于退火次数。因此,利用所提出的测试结构,可以优化PZT薄膜的cmos单片集成效果。
{"title":"Damage Assessment Structure of Thermal-Annealing Post-Processing on CMOS LSIs","authors":"Yuki Okamoto, N. Makimoto, Kei Misumi, Takeshi Kobayashi, Y. Mita, M. Ichiki","doi":"10.1109/ICMTS55420.2023.10094159","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094159","url":null,"abstract":"We assessed the degradation of MOSFET and CMOS LSI circuit characteristics induced by the high temperature annealing, especially for the PZT deposition process. The test structure consists of ring oscillators having different numbers of stages and single PMOSFETs and NMOEFETs designed with $0.6 mu mathrm{m}$ CMOS technology. We observed the ring oscillator (RO) oscillating frequencies and the $I_{mathrm{d}}-V_{mathrm{g}}$ characteristics of the MOSFETs before and after the annealing post-process. The result indicated that such an annealing process involving high temperatures of around 575°C is possible unless the wiring on the CMOS components is mechanically broken. In addition, annealing temperature affected the MOSFET characteristics more than annealing times. Therefore, the effects of the CMOSMEMS monolithic integration using PZT thin films be optimized using the proposed test structures.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126382280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Measurement of Temperature Effect on Comparator Offset Voltage Variation 温度对比较器偏置电压变化影响的测量
Pub Date : 2023-03-27 DOI: 10.1109/ICMTS55420.2023.10094194
Yuma Iwata, T. Kitamura, Mahfuzul Islam
Comparator offset voltage often limits the perfor-mance of a system. This paper demonstrates a measurement circuit of offset voltage variation. The digital nature of the circuit allows complete automation to enable high-volume measurement. We evaluate the temperature effect on offset voltage for 255 near-minimum size comparators fabricated in a commercial 65 nm general-purpose process. Detailed evaluation of offset voltage under a wide temperature range reveals that the temperature drift coefficient of offset voltage is a few mVs over 100o C. We also reveal that asymmetric sizing will cause large drifts in offset voltage, in the order of several tens of mV over 100o C. Thus, offset calibration circuits as well as circuits utilizing offset voltage variation need to take sufficient measures.
比较器偏置电压通常会限制系统的性能。本文介绍了一种测量偏置电压变化的电路。电路的数字特性允许完全自动化,以实现大批量测量。我们评估了255个在商用65nm通用工艺中制造的接近最小尺寸比较器的温度对偏置电压的影响。在宽温度范围内对偏置电压的详细评估表明,偏置电压的温度漂移系数在1000℃以上为几个mV。我们还发现,不对称尺寸会导致偏置电压的大漂移,在1000℃以上漂移几十mV。因此,偏置校准电路以及利用偏置电压变化的电路需要采取足够的措施。
{"title":"Measurement of Temperature Effect on Comparator Offset Voltage Variation","authors":"Yuma Iwata, T. Kitamura, Mahfuzul Islam","doi":"10.1109/ICMTS55420.2023.10094194","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094194","url":null,"abstract":"Comparator offset voltage often limits the perfor-mance of a system. This paper demonstrates a measurement circuit of offset voltage variation. The digital nature of the circuit allows complete automation to enable high-volume measurement. We evaluate the temperature effect on offset voltage for 255 near-minimum size comparators fabricated in a commercial 65 nm general-purpose process. Detailed evaluation of offset voltage under a wide temperature range reveals that the temperature drift coefficient of offset voltage is a few mVs over 100o C. We also reveal that asymmetric sizing will cause large drifts in offset voltage, in the order of several tens of mV over 100o C. Thus, offset calibration circuits as well as circuits utilizing offset voltage variation need to take sufficient measures.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115922326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A multi-contact six-terminal cross-bridge Kelvin resistor (CBKR) structure for evaluation of interface uniformity of the Ti-Al alloy/p-type 4H-SiC contact 一种用于评价ti-铝合金/p型4H-SiC触点界面均匀性的多触点六端跨桥开尔文电阻(CBKR)结构
Pub Date : 2023-03-27 DOI: 10.1109/ICMTS55420.2023.10094097
Yen-Ling Chen, Shih-Hao Lai, Jian-Hao Lin, B. Tsui
A multi-contact six-terminal cross-bridge Kelvin resistor (CBKR) structure is proposed to characterize the Ti-Al alloy/p-type 4H-SiC contact. It is confirmed that the test structure can judge the uniformity of the contact interface without destructive analysis such as cross-sectional transmission electron microscopy. Comparing with the results of singlecontact CBKR structure, it is observed that the contact interface is non-uniform and the formation of low resistivity interface depends on the contact area. This area-dependence issue should be solved in order to improve the SiC power devices and CMOS ICs.
提出了一种多触点六端跨桥开尔文电阻(CBKR)结构来表征Ti-Al合金/p型4H-SiC触点。验证了该试验结构可以在不需要横断面透射电镜等破坏性分析的情况下,对接触界面的均匀性进行判断。与单接触CBKR结构的结果相比,观察到接触界面不均匀,低电阻率界面的形成取决于接触面积。为了改进SiC功率器件和CMOS集成电路,必须解决这一面积依赖性问题。
{"title":"A multi-contact six-terminal cross-bridge Kelvin resistor (CBKR) structure for evaluation of interface uniformity of the Ti-Al alloy/p-type 4H-SiC contact","authors":"Yen-Ling Chen, Shih-Hao Lai, Jian-Hao Lin, B. Tsui","doi":"10.1109/ICMTS55420.2023.10094097","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094097","url":null,"abstract":"A multi-contact six-terminal cross-bridge Kelvin resistor (CBKR) structure is proposed to characterize the Ti-Al alloy/p-type 4H-SiC contact. It is confirmed that the test structure can judge the uniformity of the contact interface without destructive analysis such as cross-sectional transmission electron microscopy. Comparing with the results of singlecontact CBKR structure, it is observed that the contact interface is non-uniform and the formation of low resistivity interface depends on the contact area. This area-dependence issue should be solved in order to improve the SiC power devices and CMOS ICs.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116640479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design and Analysis of Discrete FET Monitors in 7nm FinFET Product for Robust Technology Validation 7nm FinFET产品中离散FET监视器的设计与分析,用于稳健技术验证
Pub Date : 2023-03-27 DOI: 10.1109/ICMTS55420.2023.10094206
V. Vidya, N. Zamdmer, T. Mechler, K. Onishi, D. Chidambarrao, B. Jeong, Y. Ko, C. H. Lee, J. Sim, M. Angyal, E. Crabbé
This paper presents two phenomena captured by product-like analog layout design of experiments (DOEs) that are otherwise difficult to capture in foundry baseline test structures. Such product driven test structures are critical for early detection of yield detractors and robustly validating a technology in a fabless design environment.
本文提出了两种现象,通过类似产品的模拟布局设计的实验(do)捕获,否则难以捕捉铸造基线测试结构。这种产品驱动的测试结构对于早期发现良率减损因素和在无晶圆厂设计环境中可靠地验证技术至关重要。
{"title":"Design and Analysis of Discrete FET Monitors in 7nm FinFET Product for Robust Technology Validation","authors":"V. Vidya, N. Zamdmer, T. Mechler, K. Onishi, D. Chidambarrao, B. Jeong, Y. Ko, C. H. Lee, J. Sim, M. Angyal, E. Crabbé","doi":"10.1109/ICMTS55420.2023.10094206","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094206","url":null,"abstract":"This paper presents two phenomena captured by product-like analog layout design of experiments (DOEs) that are otherwise difficult to capture in foundry baseline test structures. Such product driven test structures are critical for early detection of yield detractors and robustly validating a technology in a fabless design environment.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127001162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Test Structures for Studying Coplanar Reverse- Electrowetting for Vibration Sensing and Energy Harvesting 用于研究共面反电润湿振动传感和能量收集的试验结构
Pub Date : 2023-03-27 DOI: 10.1109/ICMTS55420.2023.10094057
Anotidaishe Moyo, M. W. Shahzad, J. Terry, Stewart Smith, Y. Mita, Yifan Li
Reverse electrowetting on dielectric (REWOD) has emerged to be a promising energy harvesting technology from low frequency vibrations. This study aims to use test structures to characterize a unique form of REWOD using a coplanar electrode configuration. This configuration allows for better versatility in system integration, device packaging and applications.
介质上反电润湿(REWOD)是一种很有前途的低频振动能量收集技术。本研究旨在使用测试结构来表征一种独特的REWOD形式,使用共面电极配置。这种配置允许在系统集成,设备封装和应用程序更好的多功能性。
{"title":"Test Structures for Studying Coplanar Reverse- Electrowetting for Vibration Sensing and Energy Harvesting","authors":"Anotidaishe Moyo, M. W. Shahzad, J. Terry, Stewart Smith, Y. Mita, Yifan Li","doi":"10.1109/ICMTS55420.2023.10094057","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094057","url":null,"abstract":"Reverse electrowetting on dielectric (REWOD) has emerged to be a promising energy harvesting technology from low frequency vibrations. This study aims to use test structures to characterize a unique form of REWOD using a coplanar electrode configuration. This configuration allows for better versatility in system integration, device packaging and applications.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121989131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Demonstration of frequency doubler application using ZnO-DNTT anti-ambipolar switch device ZnO-DNTT抗双极开关装置倍频应用演示
Pub Date : 2023-03-27 DOI: 10.1109/ICMTS55420.2023.10094079
Yongsu Lee, H. Hwang, Byoung Hun Lee
This paper presents the demonstration of an antiambipolar switch (AAS) using a ZnO-dinaphtho[2,3-$b: 2^{prime}, 3^{prime}$ ' $f]$ thieno $[3,2-b]$ thiophene (DNTT) heterojunction structure. The proper combination of n-and p-type thin-film semiconductors achieved a high peak-to-valley ratio of $sim 10^{5}$ at a low process temperature compatible with the back-end-of-line process. Using the electrical characteristic of positive-to-negative transconductance switching at the peak current point, a frequency doubler was implemented with only one device. The excellent electrical performance of the ZnO-DNTT AAS device resulted in a high conversion gain of $-5 mathrm{~dB}$ and an output frequency purity of 97 %.
本文介绍了利用zno -二萘[2,3-$b: 2^{素数},3^{素数}$ $f]$噻吩$[3,2-b]$噻吩(DNTT)异质结结构的反双极性开关(AAS)。n型和p型薄膜半导体的适当组合在与后端工艺兼容的低工艺温度下实现了高峰谷比$sim 10^{5}$。利用峰值电流点正、负跨导开关的电特性,实现了一种倍频器。ZnO-DNTT AAS器件具有优异的电性能,转换增益高达-5 μ m{~dB}$,输出频率纯度高达97%。
{"title":"Demonstration of frequency doubler application using ZnO-DNTT anti-ambipolar switch device","authors":"Yongsu Lee, H. Hwang, Byoung Hun Lee","doi":"10.1109/ICMTS55420.2023.10094079","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094079","url":null,"abstract":"This paper presents the demonstration of an antiambipolar switch (AAS) using a ZnO-dinaphtho[2,3-$b: 2^{prime}, 3^{prime}$ ' $f]$ thieno $[3,2-b]$ thiophene (DNTT) heterojunction structure. The proper combination of n-and p-type thin-film semiconductors achieved a high peak-to-valley ratio of $sim 10^{5}$ at a low process temperature compatible with the back-end-of-line process. Using the electrical characteristic of positive-to-negative transconductance switching at the peak current point, a frequency doubler was implemented with only one device. The excellent electrical performance of the ZnO-DNTT AAS device resulted in a high conversion gain of $-5 mathrm{~dB}$ and an output frequency purity of 97 %.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131156455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Electrical Inline-Testable Structure to Monitor Gate-Source/Drain Short Defect Caused by Imperfect Fin-Cut Patterning in FinFET Technology 一种用于监测FinFET技术中鳍片切割不完美导致的栅极-源/漏极短路缺陷的电气在线测试结构
Pub Date : 2023-03-27 DOI: 10.1109/ICMTS55420.2023.10094149
Hai Zhu, Katsunori Onishi, Stephen Wu, Adam Yang, B. Jeong, Seong-Joon Lim, Nan Jing, Choong-Ho Lee, David P. Conrady, D. Chidambarrao
On semiconductor IC chips, non-functional test structures are often designed along with the functional circuits in order to monitor the process quality even when the wafers are running in the line. This paper introduces an inline electrical test structure to monitor a systematic gate-source/drain short defect that degrades chip product yield. This area efficient, test time friendly, and insightful test structure is ideal to monitor process quality for the forementioned failure mode and help with the diagnosis of chip functional failures.
在半导体IC芯片上,非功能测试结构通常与功能电路一起设计,以便在晶圆在生产线上运行时监控工艺质量。本文介绍了一种在线电气测试结构,用于监测降低芯片产品良率的系统栅源漏极短缺陷。这种区域高效,测试时间友好,有洞察力的测试结构是理想的监控过程质量的上述故障模式,并有助于芯片功能故障的诊断。
{"title":"An Electrical Inline-Testable Structure to Monitor Gate-Source/Drain Short Defect Caused by Imperfect Fin-Cut Patterning in FinFET Technology","authors":"Hai Zhu, Katsunori Onishi, Stephen Wu, Adam Yang, B. Jeong, Seong-Joon Lim, Nan Jing, Choong-Ho Lee, David P. Conrady, D. Chidambarrao","doi":"10.1109/ICMTS55420.2023.10094149","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094149","url":null,"abstract":"On semiconductor IC chips, non-functional test structures are often designed along with the functional circuits in order to monitor the process quality even when the wafers are running in the line. This paper introduces an inline electrical test structure to monitor a systematic gate-source/drain short defect that degrades chip product yield. This area efficient, test time friendly, and insightful test structure is ideal to monitor process quality for the forementioned failure mode and help with the diagnosis of chip functional failures.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"14 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123513093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Test Structure for Evaluation of Pad Size for Wafer Probing 评估晶圆探测衬垫尺寸的测试结构
Pub Date : 2023-03-27 DOI: 10.1109/ICMTS55420.2023.10094145
Brad Smith, D. Hall, Garrett Tranquillo
A new, cage-like structure is presented and is shown to be able to electrically identify a probe needle that has fallen slightly off its probe pad, even when the standard probe resistance structure (pads shorted together) reports “good” probe resistance. Using both structures together enables a more accurate evaluation of a probe system’s capabilities. Both test structures were used to compare three types of probe cards, reporting the smallest probe pad size that provides 100& probe yield.
提出了一种新的笼状结构,即使在标准探头电阻结构(焊盘短路在一起)报告“良好”探头电阻的情况下,该结构也能从电上识别稍微脱离探头垫的探针针。同时使用这两种结构可以更准确地评估探针系统的能力。两种测试结构用于比较三种类型的探头卡,报告提供100&探头良率的最小探头垫尺寸。
{"title":"Test Structure for Evaluation of Pad Size for Wafer Probing","authors":"Brad Smith, D. Hall, Garrett Tranquillo","doi":"10.1109/ICMTS55420.2023.10094145","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094145","url":null,"abstract":"A new, cage-like structure is presented and is shown to be able to electrically identify a probe needle that has fallen slightly off its probe pad, even when the standard probe resistance structure (pads shorted together) reports “good” probe resistance. Using both structures together enables a more accurate evaluation of a probe system’s capabilities. Both test structures were used to compare three types of probe cards, reporting the smallest probe pad size that provides 100& probe yield.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122372267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Introducing Transfer Learning Framework on Device Modeling by Machine Learning 基于机器学习的设备建模迁移学习框架介绍
Pub Date : 2023-03-27 DOI: 10.1109/ICMTS55420.2023.10094067
Kota Niiyama, Hiromitu Awano, Takashi Sato
In this study, we propose a novel transistor modeling method using machine learning techniques, with a focus on extrapolation performance. Our method leverages knowledge from a base model that is related to the target model, instead of relying solely on device-specific information. The results show that our approach outperforms other transistor modeling methods based on machine learning, particularly in modeling similar but different transistors that belong to the same device family. Our method was able to reduce the root mean squared error (RMSE) by up to 80.0% compared to other methods.
在这项研究中,我们提出了一种使用机器学习技术的新型晶体管建模方法,重点关注外推性能。我们的方法利用了与目标模型相关的基础模型的知识,而不是仅仅依赖于特定于设备的信息。结果表明,我们的方法优于其他基于机器学习的晶体管建模方法,特别是在建模属于同一器件家族的相似但不同的晶体管方面。与其他方法相比,我们的方法能够将均方根误差(RMSE)降低高达80.0%。
{"title":"Introducing Transfer Learning Framework on Device Modeling by Machine Learning","authors":"Kota Niiyama, Hiromitu Awano, Takashi Sato","doi":"10.1109/ICMTS55420.2023.10094067","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094067","url":null,"abstract":"In this study, we propose a novel transistor modeling method using machine learning techniques, with a focus on extrapolation performance. Our method leverages knowledge from a base model that is related to the target model, instead of relying solely on device-specific information. The results show that our approach outperforms other transistor modeling methods based on machine learning, particularly in modeling similar but different transistors that belong to the same device family. Our method was able to reduce the root mean squared error (RMSE) by up to 80.0% compared to other methods.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"279 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123134357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Test Circuit Design for Accurately Characterizing Cells’ Output Currents in a Read-Decoupled 8T SRAM Array for Computing-in-Memory Applications 用于内存中计算应用的读去耦8T SRAM阵列中精确表征单元输出电流的测试电路设计
Pub Date : 2023-03-27 DOI: 10.1109/ICMTS55420.2023.10094078
Hao-Chiao Hong, Long-Yi Lin, Bo-Chang Chen
Computing-in-memory (CIM) is a promising technique for energy-efficiently conducting the massive amount of required multiply-and-accumulate (MAC) calculations in neural networks (NNs). The read-decoupled 8T (RD8T) SRAM cell is popular in the CIM designs because of being read disturbance free. However, local process variations may lead significant errors to the CIM results. This work proposes an accurate on-chip test circuit design for characterizing the output current of every RD8T SRAM cell in a 8-kb RD8T SRAM array fabricated in 90nm CMOS. The experimental results show the detailed and accurate spatial distribution of the RD8T cells which helps optimize the CIM circuit design.
内存计算(CIM)是一种很有前途的技术,它可以在神经网络(nn)中高效地进行大量的乘法累加(MAC)计算。读去耦8T (RD8T) SRAM单元因其无读干扰而在CIM设计中得到广泛应用。然而,本地流程变化可能会导致CIM结果出现重大错误。本文提出了一种精确的片上测试电路设计,用于表征90nm CMOS制造的8 kb RD8T SRAM阵列中每个RD8T SRAM单元的输出电流。实验结果显示了RD8T单元的详细、准确的空间分布,有助于优化CIM电路设计。
{"title":"Test Circuit Design for Accurately Characterizing Cells’ Output Currents in a Read-Decoupled 8T SRAM Array for Computing-in-Memory Applications","authors":"Hao-Chiao Hong, Long-Yi Lin, Bo-Chang Chen","doi":"10.1109/ICMTS55420.2023.10094078","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094078","url":null,"abstract":"Computing-in-memory (CIM) is a promising technique for energy-efficiently conducting the massive amount of required multiply-and-accumulate (MAC) calculations in neural networks (NNs). The read-decoupled 8T (RD8T) SRAM cell is popular in the CIM designs because of being read disturbance free. However, local process variations may lead significant errors to the CIM results. This work proposes an accurate on-chip test circuit design for characterizing the output current of every RD8T SRAM cell in a 8-kb RD8T SRAM array fabricated in 90nm CMOS. The experimental results show the detailed and accurate spatial distribution of the RD8T cells which helps optimize the CIM circuit design.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114264843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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2023 35th International Conference on Microelectronic Test Structure (ICMTS)
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