Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094159
Yuki Okamoto, N. Makimoto, Kei Misumi, Takeshi Kobayashi, Y. Mita, M. Ichiki
We assessed the degradation of MOSFET and CMOS LSI circuit characteristics induced by the high temperature annealing, especially for the PZT deposition process. The test structure consists of ring oscillators having different numbers of stages and single PMOSFETs and NMOEFETs designed with $0.6 mu mathrm{m}$ CMOS technology. We observed the ring oscillator (RO) oscillating frequencies and the $I_{mathrm{d}}-V_{mathrm{g}}$ characteristics of the MOSFETs before and after the annealing post-process. The result indicated that such an annealing process involving high temperatures of around 575°C is possible unless the wiring on the CMOS components is mechanically broken. In addition, annealing temperature affected the MOSFET characteristics more than annealing times. Therefore, the effects of the CMOSMEMS monolithic integration using PZT thin films be optimized using the proposed test structures.
我们评估了高温退火引起的MOSFET和CMOS LSI电路特性的退化,特别是PZT沉积过程。测试结构由不同级数的环形振荡器和采用$0.6 mu mathm {m}$ CMOS技术设计的单pmosfet和nmoefet组成。我们观察了退火后处理前后mosfet的环形振荡器(RO)振荡频率和$I_{mathrm{d}}-V_{mathrm{g}}$特性。结果表明,除非CMOS元件上的布线机械断裂,否则这种涉及575℃左右高温的退火过程是可能的。此外,退火温度对MOSFET特性的影响大于退火次数。因此,利用所提出的测试结构,可以优化PZT薄膜的cmos单片集成效果。
{"title":"Damage Assessment Structure of Thermal-Annealing Post-Processing on CMOS LSIs","authors":"Yuki Okamoto, N. Makimoto, Kei Misumi, Takeshi Kobayashi, Y. Mita, M. Ichiki","doi":"10.1109/ICMTS55420.2023.10094159","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094159","url":null,"abstract":"We assessed the degradation of MOSFET and CMOS LSI circuit characteristics induced by the high temperature annealing, especially for the PZT deposition process. The test structure consists of ring oscillators having different numbers of stages and single PMOSFETs and NMOEFETs designed with $0.6 mu mathrm{m}$ CMOS technology. We observed the ring oscillator (RO) oscillating frequencies and the $I_{mathrm{d}}-V_{mathrm{g}}$ characteristics of the MOSFETs before and after the annealing post-process. The result indicated that such an annealing process involving high temperatures of around 575°C is possible unless the wiring on the CMOS components is mechanically broken. In addition, annealing temperature affected the MOSFET characteristics more than annealing times. Therefore, the effects of the CMOSMEMS monolithic integration using PZT thin films be optimized using the proposed test structures.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126382280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094194
Yuma Iwata, T. Kitamura, Mahfuzul Islam
Comparator offset voltage often limits the perfor-mance of a system. This paper demonstrates a measurement circuit of offset voltage variation. The digital nature of the circuit allows complete automation to enable high-volume measurement. We evaluate the temperature effect on offset voltage for 255 near-minimum size comparators fabricated in a commercial 65 nm general-purpose process. Detailed evaluation of offset voltage under a wide temperature range reveals that the temperature drift coefficient of offset voltage is a few mVs over 100o C. We also reveal that asymmetric sizing will cause large drifts in offset voltage, in the order of several tens of mV over 100o C. Thus, offset calibration circuits as well as circuits utilizing offset voltage variation need to take sufficient measures.
{"title":"Measurement of Temperature Effect on Comparator Offset Voltage Variation","authors":"Yuma Iwata, T. Kitamura, Mahfuzul Islam","doi":"10.1109/ICMTS55420.2023.10094194","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094194","url":null,"abstract":"Comparator offset voltage often limits the perfor-mance of a system. This paper demonstrates a measurement circuit of offset voltage variation. The digital nature of the circuit allows complete automation to enable high-volume measurement. We evaluate the temperature effect on offset voltage for 255 near-minimum size comparators fabricated in a commercial 65 nm general-purpose process. Detailed evaluation of offset voltage under a wide temperature range reveals that the temperature drift coefficient of offset voltage is a few mVs over 100o C. We also reveal that asymmetric sizing will cause large drifts in offset voltage, in the order of several tens of mV over 100o C. Thus, offset calibration circuits as well as circuits utilizing offset voltage variation need to take sufficient measures.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115922326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094097
Yen-Ling Chen, Shih-Hao Lai, Jian-Hao Lin, B. Tsui
A multi-contact six-terminal cross-bridge Kelvin resistor (CBKR) structure is proposed to characterize the Ti-Al alloy/p-type 4H-SiC contact. It is confirmed that the test structure can judge the uniformity of the contact interface without destructive analysis such as cross-sectional transmission electron microscopy. Comparing with the results of singlecontact CBKR structure, it is observed that the contact interface is non-uniform and the formation of low resistivity interface depends on the contact area. This area-dependence issue should be solved in order to improve the SiC power devices and CMOS ICs.
{"title":"A multi-contact six-terminal cross-bridge Kelvin resistor (CBKR) structure for evaluation of interface uniformity of the Ti-Al alloy/p-type 4H-SiC contact","authors":"Yen-Ling Chen, Shih-Hao Lai, Jian-Hao Lin, B. Tsui","doi":"10.1109/ICMTS55420.2023.10094097","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094097","url":null,"abstract":"A multi-contact six-terminal cross-bridge Kelvin resistor (CBKR) structure is proposed to characterize the Ti-Al alloy/p-type 4H-SiC contact. It is confirmed that the test structure can judge the uniformity of the contact interface without destructive analysis such as cross-sectional transmission electron microscopy. Comparing with the results of singlecontact CBKR structure, it is observed that the contact interface is non-uniform and the formation of low resistivity interface depends on the contact area. This area-dependence issue should be solved in order to improve the SiC power devices and CMOS ICs.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116640479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094206
V. Vidya, N. Zamdmer, T. Mechler, K. Onishi, D. Chidambarrao, B. Jeong, Y. Ko, C. H. Lee, J. Sim, M. Angyal, E. Crabbé
This paper presents two phenomena captured by product-like analog layout design of experiments (DOEs) that are otherwise difficult to capture in foundry baseline test structures. Such product driven test structures are critical for early detection of yield detractors and robustly validating a technology in a fabless design environment.
{"title":"Design and Analysis of Discrete FET Monitors in 7nm FinFET Product for Robust Technology Validation","authors":"V. Vidya, N. Zamdmer, T. Mechler, K. Onishi, D. Chidambarrao, B. Jeong, Y. Ko, C. H. Lee, J. Sim, M. Angyal, E. Crabbé","doi":"10.1109/ICMTS55420.2023.10094206","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094206","url":null,"abstract":"This paper presents two phenomena captured by product-like analog layout design of experiments (DOEs) that are otherwise difficult to capture in foundry baseline test structures. Such product driven test structures are critical for early detection of yield detractors and robustly validating a technology in a fabless design environment.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127001162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094057
Anotidaishe Moyo, M. W. Shahzad, J. Terry, Stewart Smith, Y. Mita, Yifan Li
Reverse electrowetting on dielectric (REWOD) has emerged to be a promising energy harvesting technology from low frequency vibrations. This study aims to use test structures to characterize a unique form of REWOD using a coplanar electrode configuration. This configuration allows for better versatility in system integration, device packaging and applications.
{"title":"Test Structures for Studying Coplanar Reverse- Electrowetting for Vibration Sensing and Energy Harvesting","authors":"Anotidaishe Moyo, M. W. Shahzad, J. Terry, Stewart Smith, Y. Mita, Yifan Li","doi":"10.1109/ICMTS55420.2023.10094057","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094057","url":null,"abstract":"Reverse electrowetting on dielectric (REWOD) has emerged to be a promising energy harvesting technology from low frequency vibrations. This study aims to use test structures to characterize a unique form of REWOD using a coplanar electrode configuration. This configuration allows for better versatility in system integration, device packaging and applications.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121989131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094079
Yongsu Lee, H. Hwang, Byoung Hun Lee
This paper presents the demonstration of an antiambipolar switch (AAS) using a ZnO-dinaphtho[2,3-$b: 2^{prime}, 3^{prime}$ ' $f]$ thieno $[3,2-b]$ thiophene (DNTT) heterojunction structure. The proper combination of n-and p-type thin-film semiconductors achieved a high peak-to-valley ratio of $sim 10^{5}$ at a low process temperature compatible with the back-end-of-line process. Using the electrical characteristic of positive-to-negative transconductance switching at the peak current point, a frequency doubler was implemented with only one device. The excellent electrical performance of the ZnO-DNTT AAS device resulted in a high conversion gain of $-5 mathrm{~dB}$ and an output frequency purity of 97 %.
{"title":"Demonstration of frequency doubler application using ZnO-DNTT anti-ambipolar switch device","authors":"Yongsu Lee, H. Hwang, Byoung Hun Lee","doi":"10.1109/ICMTS55420.2023.10094079","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094079","url":null,"abstract":"This paper presents the demonstration of an antiambipolar switch (AAS) using a ZnO-dinaphtho[2,3-$b: 2^{prime}, 3^{prime}$ ' $f]$ thieno $[3,2-b]$ thiophene (DNTT) heterojunction structure. The proper combination of n-and p-type thin-film semiconductors achieved a high peak-to-valley ratio of $sim 10^{5}$ at a low process temperature compatible with the back-end-of-line process. Using the electrical characteristic of positive-to-negative transconductance switching at the peak current point, a frequency doubler was implemented with only one device. The excellent electrical performance of the ZnO-DNTT AAS device resulted in a high conversion gain of $-5 mathrm{~dB}$ and an output frequency purity of 97 %.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131156455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094149
Hai Zhu, Katsunori Onishi, Stephen Wu, Adam Yang, B. Jeong, Seong-Joon Lim, Nan Jing, Choong-Ho Lee, David P. Conrady, D. Chidambarrao
On semiconductor IC chips, non-functional test structures are often designed along with the functional circuits in order to monitor the process quality even when the wafers are running in the line. This paper introduces an inline electrical test structure to monitor a systematic gate-source/drain short defect that degrades chip product yield. This area efficient, test time friendly, and insightful test structure is ideal to monitor process quality for the forementioned failure mode and help with the diagnosis of chip functional failures.
{"title":"An Electrical Inline-Testable Structure to Monitor Gate-Source/Drain Short Defect Caused by Imperfect Fin-Cut Patterning in FinFET Technology","authors":"Hai Zhu, Katsunori Onishi, Stephen Wu, Adam Yang, B. Jeong, Seong-Joon Lim, Nan Jing, Choong-Ho Lee, David P. Conrady, D. Chidambarrao","doi":"10.1109/ICMTS55420.2023.10094149","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094149","url":null,"abstract":"On semiconductor IC chips, non-functional test structures are often designed along with the functional circuits in order to monitor the process quality even when the wafers are running in the line. This paper introduces an inline electrical test structure to monitor a systematic gate-source/drain short defect that degrades chip product yield. This area efficient, test time friendly, and insightful test structure is ideal to monitor process quality for the forementioned failure mode and help with the diagnosis of chip functional failures.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"14 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123513093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094145
Brad Smith, D. Hall, Garrett Tranquillo
A new, cage-like structure is presented and is shown to be able to electrically identify a probe needle that has fallen slightly off its probe pad, even when the standard probe resistance structure (pads shorted together) reports “good” probe resistance. Using both structures together enables a more accurate evaluation of a probe system’s capabilities. Both test structures were used to compare three types of probe cards, reporting the smallest probe pad size that provides 100& probe yield.
{"title":"Test Structure for Evaluation of Pad Size for Wafer Probing","authors":"Brad Smith, D. Hall, Garrett Tranquillo","doi":"10.1109/ICMTS55420.2023.10094145","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094145","url":null,"abstract":"A new, cage-like structure is presented and is shown to be able to electrically identify a probe needle that has fallen slightly off its probe pad, even when the standard probe resistance structure (pads shorted together) reports “good” probe resistance. Using both structures together enables a more accurate evaluation of a probe system’s capabilities. Both test structures were used to compare three types of probe cards, reporting the smallest probe pad size that provides 100& probe yield.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122372267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094067
Kota Niiyama, Hiromitu Awano, Takashi Sato
In this study, we propose a novel transistor modeling method using machine learning techniques, with a focus on extrapolation performance. Our method leverages knowledge from a base model that is related to the target model, instead of relying solely on device-specific information. The results show that our approach outperforms other transistor modeling methods based on machine learning, particularly in modeling similar but different transistors that belong to the same device family. Our method was able to reduce the root mean squared error (RMSE) by up to 80.0% compared to other methods.
{"title":"Introducing Transfer Learning Framework on Device Modeling by Machine Learning","authors":"Kota Niiyama, Hiromitu Awano, Takashi Sato","doi":"10.1109/ICMTS55420.2023.10094067","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094067","url":null,"abstract":"In this study, we propose a novel transistor modeling method using machine learning techniques, with a focus on extrapolation performance. Our method leverages knowledge from a base model that is related to the target model, instead of relying solely on device-specific information. The results show that our approach outperforms other transistor modeling methods based on machine learning, particularly in modeling similar but different transistors that belong to the same device family. Our method was able to reduce the root mean squared error (RMSE) by up to 80.0% compared to other methods.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"279 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123134357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094078
Hao-Chiao Hong, Long-Yi Lin, Bo-Chang Chen
Computing-in-memory (CIM) is a promising technique for energy-efficiently conducting the massive amount of required multiply-and-accumulate (MAC) calculations in neural networks (NNs). The read-decoupled 8T (RD8T) SRAM cell is popular in the CIM designs because of being read disturbance free. However, local process variations may lead significant errors to the CIM results. This work proposes an accurate on-chip test circuit design for characterizing the output current of every RD8T SRAM cell in a 8-kb RD8T SRAM array fabricated in 90nm CMOS. The experimental results show the detailed and accurate spatial distribution of the RD8T cells which helps optimize the CIM circuit design.
{"title":"Test Circuit Design for Accurately Characterizing Cells’ Output Currents in a Read-Decoupled 8T SRAM Array for Computing-in-Memory Applications","authors":"Hao-Chiao Hong, Long-Yi Lin, Bo-Chang Chen","doi":"10.1109/ICMTS55420.2023.10094078","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094078","url":null,"abstract":"Computing-in-memory (CIM) is a promising technique for energy-efficiently conducting the massive amount of required multiply-and-accumulate (MAC) calculations in neural networks (NNs). The read-decoupled 8T (RD8T) SRAM cell is popular in the CIM designs because of being read disturbance free. However, local process variations may lead significant errors to the CIM results. This work proposes an accurate on-chip test circuit design for characterizing the output current of every RD8T SRAM cell in a 8-kb RD8T SRAM array fabricated in 90nm CMOS. The experimental results show the detailed and accurate spatial distribution of the RD8T cells which helps optimize the CIM circuit design.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114264843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}