Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904342
F. Perkins, S. Fertig, K. Brown, D. McCarthy, L. Tender, M. Peckerar
A device is described that enables the rapid sensing of molecules with a high degree of sensitivity and selectivity. This device is based on a depletion mode FET in which the gate electrode has been removed, certain molecular receptor species (e.g. proteins, oligonucleotides, antibodies, etc.) have been affixed, and a test solution is exposed to the gate. A counter electrode is immersed in the solution in order to establish a reference potential. Changes in the source-drain current indicate an attachment response of the system. Preliminary results are presented.
{"title":"An active microelectronic transducer for enabling label-free miniaturized chemical sensors","authors":"F. Perkins, S. Fertig, K. Brown, D. McCarthy, L. Tender, M. Peckerar","doi":"10.1109/IEDM.2000.904342","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904342","url":null,"abstract":"A device is described that enables the rapid sensing of molecules with a high degree of sensitivity and selectivity. This device is based on a depletion mode FET in which the gate electrode has been removed, certain molecular receptor species (e.g. proteins, oligonucleotides, antibodies, etc.) have been affixed, and a test solution is exposed to the gate. A counter electrode is immersed in the solution in order to establish a reference potential. Changes in the source-drain current indicate an attachment response of the system. Preliminary results are presented.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132674067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904408
D. Esseni, M. Mastrapasqua, G. Celler, F. Baumann, C. Fiegna, L. Selmi, E. Sangiorgi
Electron and hole effective mobilities of ultra-thin SOI N- and P-MOSFETs have been measured at different temperatures using a special test structure able to circumvent parasitic resistance effects. At large inversion densities (N/sub inv/) ultra-thin SOI mobility can be higher than in heavily doped bulk MOS due a lower effective field and it is largely insensitive to silicon thickness (T/sub SI/). However, at small Ni/sub inv/ the mobility is clearly reduced for decreasing T/sub SI/. The effective mobility data are used to study the implications for ultra-short MOS transistor performance at device simulation level.
{"title":"Low field mobility of ultra-thin SOI N- and P-MOSFETs: Measurements and implications on the performance of ultra-short MOSFETs","authors":"D. Esseni, M. Mastrapasqua, G. Celler, F. Baumann, C. Fiegna, L. Selmi, E. Sangiorgi","doi":"10.1109/IEDM.2000.904408","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904408","url":null,"abstract":"Electron and hole effective mobilities of ultra-thin SOI N- and P-MOSFETs have been measured at different temperatures using a special test structure able to circumvent parasitic resistance effects. At large inversion densities (N/sub inv/) ultra-thin SOI mobility can be higher than in heavily doped bulk MOS due a lower effective field and it is largely insensitive to silicon thickness (T/sub SI/). However, at small Ni/sub inv/ the mobility is clearly reduced for decreasing T/sub SI/. The effective mobility data are used to study the implications for ultra-short MOS transistor performance at device simulation level.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130997365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904396
C. Sheraw, J. A. Nichols, D. Gundlach, J. Huang, C. Kuo, H. Klauk, T. Jackson, M. Kane, J. Campi, F. Cuomo, B. Greening
We have fabricated the fastest organic circuits on flexible substrates yet reported. These circuits use the small-molecule hydrocarbon pentacene as the active semiconductor material and 75 /spl mu/m thick flexible, transparent, colorless, polyethylene naphthalate (PEN) film as the substrate. Transistor arrays, inverters, ring oscillators, and other circuits with good electrical performance, yield, and uniformity were obtained. A field-effect mobility of 1 cm/sup 2// V-s was extracted from OTFT saturation characteristics, and ring oscillators had minimum propagation delay <40 /spl mu/sec per stage and <50 /spl mu/sec per stage at bias levels below 8 V.
{"title":"Fast organic circuits on flexible polymeric substrates","authors":"C. Sheraw, J. A. Nichols, D. Gundlach, J. Huang, C. Kuo, H. Klauk, T. Jackson, M. Kane, J. Campi, F. Cuomo, B. Greening","doi":"10.1109/IEDM.2000.904396","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904396","url":null,"abstract":"We have fabricated the fastest organic circuits on flexible substrates yet reported. These circuits use the small-molecule hydrocarbon pentacene as the active semiconductor material and 75 /spl mu/m thick flexible, transparent, colorless, polyethylene naphthalate (PEN) film as the substrate. Transistor arrays, inverters, ring oscillators, and other circuits with good electrical performance, yield, and uniformity were obtained. A field-effect mobility of 1 cm/sup 2// V-s was extracted from OTFT saturation characteristics, and ring oscillators had minimum propagation delay <40 /spl mu/sec per stage and <50 /spl mu/sec per stage at bias levels below 8 V.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126886045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904361
Kihong Kim, H. Yoon, K. O
The feasibility of integrated antennas for a wireless clock distribution system is investigated. A wide range of linear, meander, zigzag dipole, and loop antennas on 10 and 20 /spl Omega/-cm silicon and SOS substrates has been experimentally evaluated. A 2-mm long, 30-/spl mu/m wide, 30-degree zigzag dipole antenna pair on a 20 /spl Omega/-cm silicon substrate has -56 dB of transmission gain near 18 GHz. A loop-zigzag pair shows similar gain. The loop antenna with a compact size and an isotropic radiation pattern is ideal for a transmitter antenna.
{"title":"On-chip wireless interconnection with integrated antennas","authors":"Kihong Kim, H. Yoon, K. O","doi":"10.1109/IEDM.2000.904361","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904361","url":null,"abstract":"The feasibility of integrated antennas for a wireless clock distribution system is investigated. A wide range of linear, meander, zigzag dipole, and loop antennas on 10 and 20 /spl Omega/-cm silicon and SOS substrates has been experimentally evaluated. A 2-mm long, 30-/spl mu/m wide, 30-degree zigzag dipole antenna pair on a 20 /spl Omega/-cm silicon substrate has -56 dB of transmission gain near 18 GHz. A loop-zigzag pair shows similar gain. The loop antenna with a compact size and an isotropic radiation pattern is ideal for a transmitter antenna.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123750911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904450
M. Tagami, T. Fukai, M. Hiroi, J. Kawahara, K. Shiba, M. Tada, T. Onodera, S. Saito, K. Kinoshita, T. Ogura, M. Narihiro, K. Arai, K. Yamaguchi, M. Fukaishi, K. Kikuta, T. Mogami, Y. Hayashi
For high-speed CMOS devices, triple-layered Cu single damascene interconnects (SDI) with Cu-via plugs are fabricated in hybrid dielectric films of plasma-polymerized divinylsiloxan benzocyclobuten film (p-BCB: k=2.6) and p-CVD SiO/sub 2/. No degradation of O.1 /spl mu/m MOSFETs is observed after the full interconnect integration through MOCVD-Cu filling and pad-scanning, local-CMP for Cu polish. The stacked Cu-pads in the high modulus p-BCB film (19Gpa) withstand sever mechanical impact during Al wire bonding. The 0.08 /spl mu/m CMOS transmitter, which consists of 32:8 pre-multiplexer (MUX), 8B10B encoder, 10:1 MUX and DATA driver, is obtained successfully to generate high-speed serial signals up to 6 Gb/s. This fabrication process is the key to obtaining high-speed CMOS devices with low-k/Cu interconnects.
{"title":"Cu single damascene interconnects with plasma-polymerized organic polymers (k=2.6) for high-speed, 0.1 /spl mu/m CMOS devices","authors":"M. Tagami, T. Fukai, M. Hiroi, J. Kawahara, K. Shiba, M. Tada, T. Onodera, S. Saito, K. Kinoshita, T. Ogura, M. Narihiro, K. Arai, K. Yamaguchi, M. Fukaishi, K. Kikuta, T. Mogami, Y. Hayashi","doi":"10.1109/IEDM.2000.904450","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904450","url":null,"abstract":"For high-speed CMOS devices, triple-layered Cu single damascene interconnects (SDI) with Cu-via plugs are fabricated in hybrid dielectric films of plasma-polymerized divinylsiloxan benzocyclobuten film (p-BCB: k=2.6) and p-CVD SiO/sub 2/. No degradation of O.1 /spl mu/m MOSFETs is observed after the full interconnect integration through MOCVD-Cu filling and pad-scanning, local-CMP for Cu polish. The stacked Cu-pads in the high modulus p-BCB film (19Gpa) withstand sever mechanical impact during Al wire bonding. The 0.08 /spl mu/m CMOS transmitter, which consists of 32:8 pre-multiplexer (MUX), 8B10B encoder, 10:1 MUX and DATA driver, is obtained successfully to generate high-speed serial signals up to 6 Gb/s. This fabrication process is the key to obtaining high-speed CMOS devices with low-k/Cu interconnects.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126664812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904455
A. Fujiwara, Y. Takahashi
Single-electron (SE) devices have been attracting much attention because of their low power consumption and potential for novel functions based on the manipulation of a single charge. Silicon-on-insulator (SOI) wafers are the most feasible material for fabricating SE devices since Si nanostructures can be implemented by the nanolithography technique. We have already reported SE transistors, SE memories and coupled-island SE devices, which were fabricated by means of pattern-dependent oxidation (PADOX). Nevertheless, the ultimate operation, the manipulation of a single charge, such as in a SE pump, has not yet been realized in Si devices and remains a future subject. Here, we report a novel type of SE device, an ultrasmall charge-coupled device (CCD) on a SOI wafer. The fabricated prototype can transfer a single hole like a conventional CCD. We also demonstrate a new method of storing holes and sensing them on the level of a single charge.
{"title":"Silicon single-electron CCD","authors":"A. Fujiwara, Y. Takahashi","doi":"10.1109/IEDM.2000.904455","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904455","url":null,"abstract":"Single-electron (SE) devices have been attracting much attention because of their low power consumption and potential for novel functions based on the manipulation of a single charge. Silicon-on-insulator (SOI) wafers are the most feasible material for fabricating SE devices since Si nanostructures can be implemented by the nanolithography technique. We have already reported SE transistors, SE memories and coupled-island SE devices, which were fabricated by means of pattern-dependent oxidation (PADOX). Nevertheless, the ultimate operation, the manipulation of a single charge, such as in a SE pump, has not yet been realized in Si devices and remains a future subject. Here, we report a novel type of SE device, an ultrasmall charge-coupled device (CCD) on a SOI wafer. The fabricated prototype can transfer a single hole like a conventional CCD. We also demonstrate a new method of storing holes and sensing them on the level of a single charge.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126613755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904441
J. Goo, William Liut, Chang-hoon Choi, Keith R. Greent, Zhiping Yu, Thomas H. Lee, Robert, Dutton
This paper is the first independent comparison between BSIM4 and the van der Ziel models for induced gate noise. Despite the very different modeling strategies, BSIM4 successfully reproduces the classical van der Ziel model, introducing only small errors in the correlated noise term. In the case of practical circuits, noticeable errors usually arise for very low gate bias conditions yet the errors are acceptably small. Therefore, the two models can be considered as being equivalent to each other in most practical circuits, including nongrounded source conditions of operation.
本文是BSIM4和van der Ziel模型在感应门噪声方面的首次独立比较。尽管建模策略非常不同，但BSIM4成功地再现了经典的van der Ziel模型，仅在相关噪声项中引入了很小的误差。在实际电路中，在极低的栅极偏置条件下通常会产生明显的误差，但误差是可以接受的。因此，在大多数实际电路中，包括工作的非接地源条件下，这两种模型可以认为是相互等效的。
{"title":"The equivalence of van der Ziel and BSIM4 models in modeling the induced gate noise of MOSFETs","authors":"J. Goo, William Liut, Chang-hoon Choi, Keith R. Greent, Zhiping Yu, Thomas H. Lee, Robert, Dutton","doi":"10.1109/IEDM.2000.904441","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904441","url":null,"abstract":"This paper is the first independent comparison between BSIM4 and the van der Ziel models for induced gate noise. Despite the very different modeling strategies, BSIM4 successfully reproduces the classical van der Ziel model, introducing only small errors in the correlated noise term. In the case of practical circuits, noticeable errors usually arise for very low gate bias conditions yet the errors are acceptably small. Therefore, the two models can be considered as being equivalent to each other in most practical circuits, including nongrounded source conditions of operation.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"5 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122020346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904429
S. Aritome
This paper describes a high density flash memory technology suitable for file storage application. Requirements for file storage memory are low cost, high-speed programming and erasing, low power consumption and good endurance characteristics. In order to satisfy these requirements, key technologies of self-aligned STI (SA-STI) cell, uniform FN-FN program/erase scheme and multi-level-cell (MLC) technology have been developed. By using SA-STI technology, small cell size of 4F/sup 2/ (F: feature size) can be realized. Reliable tunnel oxide can be also obtained because the floating gate does not overlap the STI corner. As a result, reliable 512 Mbit flash memories with 0.145 um/sup 2/ cell size under 0.175 /spl mu/m design rule have been newly developed based on these technologies, as well as 0.25 /spl mu/m 256 Mbit. Moreover, MLC technology combined with this small cell size of 4F/sup 2/ can reduce bit cost more, and can expand the file storage market in the near future.
{"title":"Advanced flash memory technology and trends for file storage application","authors":"S. Aritome","doi":"10.1109/IEDM.2000.904429","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904429","url":null,"abstract":"This paper describes a high density flash memory technology suitable for file storage application. Requirements for file storage memory are low cost, high-speed programming and erasing, low power consumption and good endurance characteristics. In order to satisfy these requirements, key technologies of self-aligned STI (SA-STI) cell, uniform FN-FN program/erase scheme and multi-level-cell (MLC) technology have been developed. By using SA-STI technology, small cell size of 4F/sup 2/ (F: feature size) can be realized. Reliable tunnel oxide can be also obtained because the floating gate does not overlap the STI corner. As a result, reliable 512 Mbit flash memories with 0.145 um/sup 2/ cell size under 0.175 /spl mu/m design rule have been newly developed based on these technologies, as well as 0.25 /spl mu/m 256 Mbit. Moreover, MLC technology combined with this small cell size of 4F/sup 2/ can reduce bit cost more, and can expand the file storage market in the near future.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"67 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122545983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904259
T. Schulz, W. Rosner, L. Risch, U. Langmann
Vertical MOSFETs have been proposed in the roadmap of semiconductors as a candidate for sub 100 nm CMOS technologies. A process flow using sidewall gates and implantations instead of multiple layer depositions reduces process complexity and offers better CMOS compatibility. High doping concentrations in the channel are needed for sub 100 nm devices. Especially for vertical transistors the uniform channel doping is more critical than for a planar technology, where optimized profiles can be easier implemented. Therefore, we investigated for the first time vertical MOSFETs with high channel doping concentration up to 1*10/sup 19/ cm/sup -3/ and channel lengths down to 50 nm. The impact of the high doping levels on threshold voltage and on tunneling currents is discussed. Finally, by using slight process modifications first results on vertical double gate MOSFETs will be presented, which in principle can operate with an undoped channel region.
{"title":"50-nm vertical sidewall transistors with high channel doping concentrations","authors":"T. Schulz, W. Rosner, L. Risch, U. Langmann","doi":"10.1109/IEDM.2000.904259","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904259","url":null,"abstract":"Vertical MOSFETs have been proposed in the roadmap of semiconductors as a candidate for sub 100 nm CMOS technologies. A process flow using sidewall gates and implantations instead of multiple layer depositions reduces process complexity and offers better CMOS compatibility. High doping concentrations in the channel are needed for sub 100 nm devices. Especially for vertical transistors the uniform channel doping is more critical than for a planar technology, where optimized profiles can be easier implemented. Therefore, we investigated for the first time vertical MOSFETs with high channel doping concentration up to 1*10/sup 19/ cm/sup -3/ and channel lengths down to 50 nm. The impact of the high doping levels on threshold voltage and on tunneling currents is discussed. Finally, by using slight process modifications first results on vertical double gate MOSFETs will be presented, which in principle can operate with an undoped channel region.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129463129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904267
P. Palestri, M. Pavesi, P. Rigolli, L. Selmi, A. Dalla Serra, A. Abramo, F. Widdershoven, E. Sangiorgi
This paper addresses the problem of the origin of majority and minority carriers' substrate currents in MOS devices. In particular, we present a critical analysis of published and original tunneling experiments by means of a novel, physically based model of impact ionization and hot carrier photon emission and re-absorption in the substrate. The model explains some relevant features of substrate minority carrier currents in saturated nMOSFETs, and provides a better understanding of the origin of substrate currents in tunneling MOS capacitors.
{"title":"Impact ionization and photon emission in MOS capacitors and FETs","authors":"P. Palestri, M. Pavesi, P. Rigolli, L. Selmi, A. Dalla Serra, A. Abramo, F. Widdershoven, E. Sangiorgi","doi":"10.1109/IEDM.2000.904267","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904267","url":null,"abstract":"This paper addresses the problem of the origin of majority and minority carriers' substrate currents in MOS devices. In particular, we present a critical analysis of published and original tunneling experiments by means of a novel, physically based model of impact ionization and hot carrier photon emission and re-absorption in the substrate. The model explains some relevant features of substrate minority carrier currents in saturated nMOSFETs, and provides a better understanding of the origin of substrate currents in tunneling MOS capacitors.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128928477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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