Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904405
S. Pidin, M. Mushiga, H. Shido, T. Yamamoto, Y. Sambonsugi, Y. Tamura, T. Sugii
We demonstrate a notched W/TiN gate MOSFET for which both threshold voltage adjustment and suppression of the short channel effect are achieved simultaneously. To lower the threshold voltage, low channel doping concentration and high dose-low energy counter-doping are combined with high-dose tilted pocket implant performed using notched gate. Due to presence of notches, near optimal pocket implant distribution in the channel is achieved.
{"title":"A notched metal gate MOSFET for sub-0.1 /spl mu/m operation","authors":"S. Pidin, M. Mushiga, H. Shido, T. Yamamoto, Y. Sambonsugi, Y. Tamura, T. Sugii","doi":"10.1109/IEDM.2000.904405","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904405","url":null,"abstract":"We demonstrate a notched W/TiN gate MOSFET for which both threshold voltage adjustment and suppression of the short channel effect are achieved simultaneously. To lower the threshold voltage, low channel doping concentration and high dose-low energy counter-doping are combined with high-dose tilted pocket implant performed using notched gate. Due to presence of notches, near optimal pocket implant distribution in the channel is achieved.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128497188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904431
A. Goda, W. Moriyama, H. Hazama, H. Iizuka, K. Shimizu, S. Aritome, R. Shirota
This paper describes a novel surface-oxidized barrier-SiN cell technology to effect a tenfold improvement in endurance and read disturb characteristics. In conventional memory cells, degradation of tunnel oxides due to barrier-SiN films for Self-Aligned Contact (SAC) limits the scaling of memory cells. The proposed technology overcomes this problem by an additional oxidation process subsequent to barrier-SiN deposition to reduce hydrogen in both SiN film and tunnel oxide. 0.18 /spl mu/m-rule NAND cells fabricated by the proposed technology demonstrate a tenfold improvement in allowable program/erase cycles and read disturb lifetime without any deterioration of other cell properties.
{"title":"A novel surface-oxidized barrier-SiN cell technology to improve endurance and read-disturb characteristics for gigabit NAND flash memories","authors":"A. Goda, W. Moriyama, H. Hazama, H. Iizuka, K. Shimizu, S. Aritome, R. Shirota","doi":"10.1109/IEDM.2000.904431","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904431","url":null,"abstract":"This paper describes a novel surface-oxidized barrier-SiN cell technology to effect a tenfold improvement in endurance and read disturb characteristics. In conventional memory cells, degradation of tunnel oxides due to barrier-SiN films for Self-Aligned Contact (SAC) limits the scaling of memory cells. The proposed technology overcomes this problem by an additional oxidation process subsequent to barrier-SiN deposition to reduce hydrogen in both SiN film and tunnel oxide. 0.18 /spl mu/m-rule NAND cells fabricated by the proposed technology demonstrate a tenfold improvement in allowable program/erase cycles and read disturb lifetime without any deterioration of other cell properties.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128736864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904381
Y. Takao, H. Kudo, J. Mitani, Y. Kotani, S. Yamaguchi, K. Yoshie, M. Kawano, T. Nagano, I. Yamamura, M. Uematsu, N. Nagashima, S. Kadomura
This paper describes a 0.11 /spl mu/m CMOS technology with high-reliable copper and very-low-k (VLK) (k<2.7) interconnects for high performance and low power applications. Aggressive design rules, 0.11 /spl mu/m gate transistor, and 2.2 /spl mu/m/sup 2/ 6T-SRAM cell are realized by using KrF 248 nm lithography, optical proximity-effect correction (OPC), and gate-shrink techniques. Drain current of 0.63 mA//spl mu/m and 0.28 mA//spl mu/m are realized for nMOSFET and pMOSFET with 0.11 /spl mu/m gate, respectively. Propagation delay of 2-input NAND with the copper/hybrid VLK interconnects is estimated. The delay is improved by more than 70%, compared to 0.18 /spl mu/m CMOS technology with copper/FSG interconnects.
{"title":"A 0.11 /spl mu/m CMOS technology with copper and very-low-k interconnects for high-performance system-on-a-chip cores","authors":"Y. Takao, H. Kudo, J. Mitani, Y. Kotani, S. Yamaguchi, K. Yoshie, M. Kawano, T. Nagano, I. Yamamura, M. Uematsu, N. Nagashima, S. Kadomura","doi":"10.1109/IEDM.2000.904381","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904381","url":null,"abstract":"This paper describes a 0.11 /spl mu/m CMOS technology with high-reliable copper and very-low-k (VLK) (k<2.7) interconnects for high performance and low power applications. Aggressive design rules, 0.11 /spl mu/m gate transistor, and 2.2 /spl mu/m/sup 2/ 6T-SRAM cell are realized by using KrF 248 nm lithography, optical proximity-effect correction (OPC), and gate-shrink techniques. Drain current of 0.63 mA//spl mu/m and 0.28 mA//spl mu/m are realized for nMOSFET and pMOSFET with 0.11 /spl mu/m gate, respectively. Propagation delay of 2-input NAND with the copper/hybrid VLK interconnects is estimated. The delay is improved by more than 70%, compared to 0.18 /spl mu/m CMOS technology with copper/FSG interconnects.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129111117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904316
T. Osabe, T. Ishii, T. Mine, F. Murai, K. Yano
The developed single-electron shut-off (SESO) transistor has a leakage current in the range of 10/sup -19/ A (less than one electron per 100 ms; typical DRAM refresh cycle) or better, and it ushers in an era of opportunities for 4-Gb-or-larger post-DRAM memories. In its ultra-thin (2 nm) polycrystalline silicon film, electron hopping between traps is dramatically suppressed because of its limited number of neighboring traps and the Coulomb blockade effect. A SESO memory gain cell using the SESO transistor, has an over 3,000 second retention time even without a memory capacitor.
{"title":"A single-electron shut-off transistor for a scalable sub-0.1 /spl mu/m memory","authors":"T. Osabe, T. Ishii, T. Mine, F. Murai, K. Yano","doi":"10.1109/IEDM.2000.904316","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904316","url":null,"abstract":"The developed single-electron shut-off (SESO) transistor has a leakage current in the range of 10/sup -19/ A (less than one electron per 100 ms; typical DRAM refresh cycle) or better, and it ushers in an era of opportunities for 4-Gb-or-larger post-DRAM memories. In its ultra-thin (2 nm) polycrystalline silicon film, electron hopping between traps is dramatically suppressed because of its limited number of neighboring traps and the Coulomb blockade effect. A SESO memory gain cell using the SESO transistor, has an over 3,000 second retention time even without a memory capacitor.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117168680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904305
K. Kinoshita, M. Tada, T. Usami, M. Hiroi, T. Tonegawa, K. Shiba, T. Onodera, M. Tagami, S. Saitoh, Y. Hayashi
By dual hard mask (dHM) process combined with sidewall-hardening etching step, copper dual-damascene (DD) interconnects are fabricated in low-k organic film without any etch-stop layers under the trench. Careful designs of dHM structures and their patterning sequence enable us to harden the via-sidewall by fluorocarbon plasma, which is a key to reduce final via-shoulder loss at the via/trench connecting region. The low-k structure has low via resistance such as 0.65 /spl Omega//0.28 /spl mu/m/sup /spl phi//-via while keeping the large tolerance of misalignment in via/trench, appreciable for 0.1 /spl mu/m-generation CMOS ULSIs.
{"title":"Process design methodology for via-shape-controlled, copper dual-damascene interconnects in low-k organic film","authors":"K. Kinoshita, M. Tada, T. Usami, M. Hiroi, T. Tonegawa, K. Shiba, T. Onodera, M. Tagami, S. Saitoh, Y. Hayashi","doi":"10.1109/IEDM.2000.904305","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904305","url":null,"abstract":"By dual hard mask (dHM) process combined with sidewall-hardening etching step, copper dual-damascene (DD) interconnects are fabricated in low-k organic film without any etch-stop layers under the trench. Careful designs of dHM structures and their patterning sequence enable us to harden the via-sidewall by fluorocarbon plasma, which is a key to reduce final via-shoulder loss at the via/trench connecting region. The low-k structure has low via resistance such as 0.65 /spl Omega//0.28 /spl mu/m/sup /spl phi//-via while keeping the large tolerance of misalignment in via/trench, appreciable for 0.1 /spl mu/m-generation CMOS ULSIs.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"218 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117340702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904328
H. Jeong, W.S. Yang, Y. Hwang, C. Cho, S. Park, S. Ahn, Y. Chun, S. shin, S.H. Song, J.Y. Lee, S. Jang, C.H. Lee, J. Jeong, M. Cho, J.K. Lee, Kinam Kim
4 Gb DRAM has been developed successfully using 0.11 /spl mu/m DRAM technology. Considering manufacturability, we have focused on developing patterning technology that makes 0.11 /spl mu/m design rules possible using KrF lithography. Also, novel DRAM technologies, which have a big influence on the future DRAM integration, are developed as follows:, using novel oxide (SOG) for the enhanced capability of gap-filling, borderless metal contact and stud processes, line-type storage node SAC, thin gate oxide, and CVD Al process for metal interconnections.
{"title":"Highly manufacturable 4 Gb DRAM using using 0.11 /spl mu/m DRAM technology","authors":"H. Jeong, W.S. Yang, Y. Hwang, C. Cho, S. Park, S. Ahn, Y. Chun, S. shin, S.H. Song, J.Y. Lee, S. Jang, C.H. Lee, J. Jeong, M. Cho, J.K. Lee, Kinam Kim","doi":"10.1109/IEDM.2000.904328","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904328","url":null,"abstract":"4 Gb DRAM has been developed successfully using 0.11 /spl mu/m DRAM technology. Considering manufacturability, we have focused on developing patterning technology that makes 0.11 /spl mu/m design rules possible using KrF lithography. Also, novel DRAM technologies, which have a big influence on the future DRAM integration, are developed as follows:, using novel oxide (SOG) for the enhanced capability of gap-filling, borderless metal contact and stud processes, line-type storage node SAC, thin gate oxide, and CVD Al process for metal interconnections.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115739994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904445
I. Kizilyalli, G. Watson, R. Kohler, O. Nalamasu, L. Harriott
In this paper the successful integration of alternating aperture phase-shift lithography methodology into a 0.12 /spl mu/m random-logic CMOS process flow is discussed. This methodology enabled the fabrication of a digital signal processor (DSP) operating at 100 MHz with a 1.0 V supply voltage with a measured stand-by current of less than 100 /spl mu/A and a dynamic power dissipation of 0.23 mW/MHz. The phase-shifted DSP chip clocks above 170 MHz at 1.5 V, a threefold improvement over the 0.24 /spl mu/m device, demonstrating an improvement approximately proportional to 1/L/sup 2/. A commercially available software tool was used to generate the phase-shift mask patterns to reach this milestone DSP performance. Two million transistors in this DSP integrated circuit with critical dimensions (CD) of 0.24 /spl mu/m are phase shifted down to gate lengths below 0.12 /spl mu/m. The CMOS process flow is optimized to achieve a low power-delay product and transistor implants are designed for conventionally designed circuits to be operational at low voltages. The technology features symmetric NMOS/PMOS threshold-voltage, nitrogen incorporated gate oxides, and a novel WSi/WSiN-polycide gate electrode stack to prevent Boron lateral diffusion.
{"title":"Phase shift lithography in the manufacture of sub-120 nm low-voltage DSP circuits","authors":"I. Kizilyalli, G. Watson, R. Kohler, O. Nalamasu, L. Harriott","doi":"10.1109/IEDM.2000.904445","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904445","url":null,"abstract":"In this paper the successful integration of alternating aperture phase-shift lithography methodology into a 0.12 /spl mu/m random-logic CMOS process flow is discussed. This methodology enabled the fabrication of a digital signal processor (DSP) operating at 100 MHz with a 1.0 V supply voltage with a measured stand-by current of less than 100 /spl mu/A and a dynamic power dissipation of 0.23 mW/MHz. The phase-shifted DSP chip clocks above 170 MHz at 1.5 V, a threefold improvement over the 0.24 /spl mu/m device, demonstrating an improvement approximately proportional to 1/L/sup 2/. A commercially available software tool was used to generate the phase-shift mask patterns to reach this milestone DSP performance. Two million transistors in this DSP integrated circuit with critical dimensions (CD) of 0.24 /spl mu/m are phase shifted down to gate lengths below 0.12 /spl mu/m. The CMOS process flow is optimized to achieve a low power-delay product and transistor implants are designed for conventionally designed circuits to be operational at low voltages. The technology features symmetric NMOS/PMOS threshold-voltage, nitrogen incorporated gate oxides, and a novel WSi/WSiN-polycide gate electrode stack to prevent Boron lateral diffusion.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125456177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904263
M.R. van den Berg, L. Nanver, J. Slotboom
The temperature dependence of avalanche multiplication in spiked electric fields in silicon is investigated for charge carrier transport across highly doped pn-junctions and across thin gate oxides. Impact ionization events with near-zero to positive temperature coefficients are experimentally observed. A model is proposed that explains the positive temperature coefficient in terms of increased effective electric field due to the decrease of the energy relaxation length for increasing temperature.
{"title":"Temperature dependence of avalanche multiplication in spiked electric fields","authors":"M.R. van den Berg, L. Nanver, J. Slotboom","doi":"10.1109/IEDM.2000.904263","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904263","url":null,"abstract":"The temperature dependence of avalanche multiplication in spiked electric fields in silicon is investigated for charge carrier transport across highly doped pn-junctions and across thin gate oxides. Impact ionization events with near-zero to positive temperature coefficients are experimentally observed. A model is proposed that explains the positive temperature coefficient in terms of increased effective electric field due to the decrease of the energy relaxation length for increasing temperature.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125819463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904414
V. Suntharalingam, B. Burke, M. Cooper, D. Yost, P. Gouker, M. Anthony, H. Whittingham, J. Sage, J. Burns, S. Rabe, C. Chen, J. Knecht, S. Cann, P. Wyatt, C. Keast
We have developed a merged CCD/SOI-CMOS technology that enables the fabrication of monolithic, low-power imaging systems on a chip. The CCD's, fabricated in the bulk handle wafer, have charge-transfer inefficiencies of about 1/spl times/10/sup -5/ and well capacities of more than 100,000 electrons with 3.3-V clocks and 8/spl times/8-/spl mu/m pixels. Fully depleted 0.35-/spl mu/m SOI-CMOS ring oscillators have stage delay of 48 ps at 3.3 V. We demonstrate for the first time an integrated image sensor with charge-domain A/D conversion and on-chip clocking.
{"title":"Monolithic 3.3 V CCD/SOI-CMOS imager technology","authors":"V. Suntharalingam, B. Burke, M. Cooper, D. Yost, P. Gouker, M. Anthony, H. Whittingham, J. Sage, J. Burns, S. Rabe, C. Chen, J. Knecht, S. Cann, P. Wyatt, C. Keast","doi":"10.1109/IEDM.2000.904414","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904414","url":null,"abstract":"We have developed a merged CCD/SOI-CMOS technology that enables the fabrication of monolithic, low-power imaging systems on a chip. The CCD's, fabricated in the bulk handle wafer, have charge-transfer inefficiencies of about 1/spl times/10/sup -5/ and well capacities of more than 100,000 electrons with 3.3-V clocks and 8/spl times/8-/spl mu/m pixels. Fully depleted 0.35-/spl mu/m SOI-CMOS ring oscillators have stage delay of 48 ps at 3.3 V. We demonstrate for the first time an integrated image sensor with charge-domain A/D conversion and on-chip clocking.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127345858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904349
K. Miyano, I. Mizushima, A. Hokazono, K. Ohuchi, Y. Tsunashima
A new low thermal-budget process for elevated source/drain (S/D) structure was developed utilizing novel solid phase epitaxy (SPE) followed by vapor phase selective etching. Short channel characteristics were drastically improved compared to those attainable with the conventional selective epitaxial growth process. Bridging problems, which had been regarded as unavoidable, were also cleared. This newly developed process is a potential solution for the elevated S/D structure in 0.1 /spl mu/m devices and beyond.
{"title":"Low thermal budget elevated source/drain technology utilizing novel solid phase epitaxy and selective vapor phase etching","authors":"K. Miyano, I. Mizushima, A. Hokazono, K. Ohuchi, Y. Tsunashima","doi":"10.1109/IEDM.2000.904349","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904349","url":null,"abstract":"A new low thermal-budget process for elevated source/drain (S/D) structure was developed utilizing novel solid phase epitaxy (SPE) followed by vapor phase selective etching. Short channel characteristics were drastically improved compared to those attainable with the conventional selective epitaxial growth process. Bridging problems, which had been regarded as unavoidable, were also cleared. This newly developed process is a potential solution for the elevated S/D structure in 0.1 /spl mu/m devices and beyond.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121691669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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