Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904448
K. Miyamoto, K. Inoue, I. Tamura, N. Kondo, H. Inoto, I. Ito, K. Kasahara, Y. Oshikiri
This paper proposes a new yield management method for the SoC (System on a Chip) VYR (vertical yield ramp). In this method, test structures and analysis methods are adjusted to quantitatively analyze and optimize failure modes for improved yield. To verify the new methodology, two types of test chips were designed to monitor and distinguish the various failure modes affecting typical LSI product chips. It is concluded that the new methodology can diagnose and improve these several failure modes simultaneously to achieve the SoC VYR.
本文提出了一种新的片上系统(System on a Chip)垂直良率坡道(vertical yield ramp)良率管理方法。该方法通过调整试验结构和分析方法，定量分析和优化失效模式，提高良率。为了验证新方法，设计了两种类型的测试芯片来监测和区分影响典型LSI产品芯片的各种失效模式。结果表明，该方法可以同时诊断和改进这几种故障模式，从而实现SoC的VYR。
{"title":"Yield management methodology for SoC vertical yield ramp","authors":"K. Miyamoto, K. Inoue, I. Tamura, N. Kondo, H. Inoto, I. Ito, K. Kasahara, Y. Oshikiri","doi":"10.1109/IEDM.2000.904448","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904448","url":null,"abstract":"This paper proposes a new yield management method for the SoC (System on a Chip) VYR (vertical yield ramp). In this method, test structures and analysis methods are adjusted to quantitatively analyze and optimize failure modes for improved yield. To verify the new methodology, two types of test chips were designed to monitor and distinguish the various failure modes affecting typical LSI product chips. It is concluded that the new methodology can diagnose and improve these several failure modes simultaneously to achieve the SoC VYR.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129972045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904451
M. Ida, K. Kurishima, H. Nakajima, N. Watanabe, S. Yamahata
Scaling down the lateral emitter dimension is an effective way to reduce the power dissipation of HBT ICs. Various authors have demonstrated submicrometer HBTs operating at >100 GHz with submilliampere current. On the other hand, there have been few reports on vertical layer structures optimized for low-current operation. At low current, the dominant delay time of HBTs is the emitter charging time. Thus, it is essential to reduce the emitter junction capacitance by increasing the thickness of the emitter depletion layer. In this paper, we propose an undoped-emitter structure for InP-based HBTs and investigate its impact on low-power applications.
{"title":"Undoped-emitter InP/InGaAs HBTs for high-speed and low-power applications","authors":"M. Ida, K. Kurishima, H. Nakajima, N. Watanabe, S. Yamahata","doi":"10.1109/IEDM.2000.904451","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904451","url":null,"abstract":"Scaling down the lateral emitter dimension is an effective way to reduce the power dissipation of HBT ICs. Various authors have demonstrated submicrometer HBTs operating at >100 GHz with submilliampere current. On the other hand, there have been few reports on vertical layer structures optimized for low-current operation. At low current, the dominant delay time of HBTs is the emitter charging time. Thus, it is essential to reduce the emitter junction capacitance by increasing the thickness of the emitter depletion layer. In this paper, we propose an undoped-emitter structure for InP-based HBTs and investigate its impact on low-power applications.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134283027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904309
Tetsu Tanaka, Tatsuya Usuki, T. Futatsugi, Y. Momiyama, T. Sugii
This paper studies effect of pocket (halo) profile on V/sub th/ fluctuation due to statistical dopant variation by measurement and simulation. A pocket profile significantly enhances V/sub th/ fluctuation by a factor of >15% at worst even if the implantation process variations would be negligible. This is because pocket dopants shrink the area which controls V/sub th/.
{"title":"V/sub th/ fluctuation induced by statistical variation of pocket dopant profile","authors":"Tetsu Tanaka, Tatsuya Usuki, T. Futatsugi, Y. Momiyama, T. Sugii","doi":"10.1109/IEDM.2000.904309","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904309","url":null,"abstract":"This paper studies effect of pocket (halo) profile on V/sub th/ fluctuation due to statistical dopant variation by measurement and simulation. A pocket profile significantly enhances V/sub th/ fluctuation by a factor of >15% at worst even if the implantation process variations would be negligible. This is because pocket dopants shrink the area which controls V/sub th/.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134324566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904366
L. S. Adam, M. E. Law, O. Dokumaci, S. Hegde
Nitrogen has been used to control oxide thickness, allowing process engineers to have multiple gate oxide thickness in the same process. New models have been developed for nitrogen behavior in silicon and its interaction with oxide growth. The diffusion model is based on ab-initio results, and is compared to experimental results at two temperatures. The oxide reduction model is based on the diffusion of nitrogen to the surface. The surface nitrogen is coupled to the surface reaction rate of oxygen and silicon to moderate the growth of the oxide.
{"title":"A physical model for implanted nitrogen diffusion and its effect on oxide growth","authors":"L. S. Adam, M. E. Law, O. Dokumaci, S. Hegde","doi":"10.1109/IEDM.2000.904366","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904366","url":null,"abstract":"Nitrogen has been used to control oxide thickness, allowing process engineers to have multiple gate oxide thickness in the same process. New models have been developed for nitrogen behavior in silicon and its interaction with oxide growth. The diffusion model is based on ab-initio results, and is compared to experimental results at two temperatures. The oxide reduction model is based on the diffusion of nitrogen to the surface. The surface nitrogen is coupled to the surface reaction rate of oxygen and silicon to moderate the growth of the oxide.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132114882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904430
Jungdal Choi, Joon-hee Lee, W. Lee, Kwang-Shik Shin, Y. Yim, Jaeduk Lee, Yoocheol Shin, Sung-nam Chang, Kyucharn Park, Jongwoo Park, C. Hwang
A new 1 Gb NAND flash technology with high-aspect-ratio floating gate, tungsten bit line and poly-Si source line has been developed. It is fabricated using 0.15 /spl mu/m photolithography, shallow trench isolation (STI), highly selective gate etching, damascene and chemical-mechanical polishing (CMP) processes. Since thick poly-Si is deposited and its sidewall has an inclined profile by anisotropic etching, narrow floating gate space (/spl sim/80 nm) under the design rule and a high coupling ratio (/spl sim/0.75) are obtained. To interconnect the NAND cell array, the poly-Si source is connected to every string as a common line and the tungsten bit line is damascened over the entire string. These double-layer interconnections lead to simple process and reduced steps. Thus, for the first time, a prototype 1 Gb NAND flash memory with an extremely small cell size of 0.11 /spl mu/m/sup 2/ has been achieved.
{"title":"A 0.15 /spl mu/m NAND flash technology with 0.11 /spl mu/m/sup 2/ cell size for 1 Gbit flash memory","authors":"Jungdal Choi, Joon-hee Lee, W. Lee, Kwang-Shik Shin, Y. Yim, Jaeduk Lee, Yoocheol Shin, Sung-nam Chang, Kyucharn Park, Jongwoo Park, C. Hwang","doi":"10.1109/IEDM.2000.904430","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904430","url":null,"abstract":"A new 1 Gb NAND flash technology with high-aspect-ratio floating gate, tungsten bit line and poly-Si source line has been developed. It is fabricated using 0.15 /spl mu/m photolithography, shallow trench isolation (STI), highly selective gate etching, damascene and chemical-mechanical polishing (CMP) processes. Since thick poly-Si is deposited and its sidewall has an inclined profile by anisotropic etching, narrow floating gate space (/spl sim/80 nm) under the design rule and a high coupling ratio (/spl sim/0.75) are obtained. To interconnect the NAND cell array, the poly-Si source is connected to every string as a common line and the tungsten bit line is damascened over the entire string. These double-layer interconnections lead to simple process and reduced steps. Thus, for the first time, a prototype 1 Gb NAND flash memory with an extremely small cell size of 0.11 /spl mu/m/sup 2/ has been achieved.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"26 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132865105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904285
G. Neudeck, T. Su, J. Denton
Silicon selective epitaxial growth (SEG) and epitaxial lateral overgrowth provide a technology for fabricating thin SOI device islands, fully self-aligned double gate SOI MOSFETs and multiple layers of SOI devices. Sub-micron P-MOSFETs in 2 SOI layers of SOI islands and the double-gate fully-depleted devices show low off currents <0.2 pA//spl mu/m with low values of sub-threshold slopes (<70 mV/dec).
{"title":"Novel silicon epitaxy for advanced MOSFET devices","authors":"G. Neudeck, T. Su, J. Denton","doi":"10.1109/IEDM.2000.904285","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904285","url":null,"abstract":"Silicon selective epitaxial growth (SEG) and epitaxial lateral overgrowth provide a technology for fabricating thin SOI device islands, fully self-aligned double gate SOI MOSFETs and multiple layers of SOI devices. Sub-micron P-MOSFETs in 2 SOI layers of SOI islands and the double-gate fully-depleted devices show low off currents <0.2 pA//spl mu/m with low values of sub-threshold slopes (<70 mV/dec).","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121910207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904343
C. Bartic, A. Campitelli, K. Baert, J. Suls, S. Borghs
In this paper we describe a new application for organic field-effect transistors (OFETs) as sensing devices for charge detection in aqueous media. The detection principle is based on the field-enhanced conduction that occurs in organic semiconductors in a similar way as in the crystalline inorganic ones. The electrochemical potential developed at the solution/dielectric interface is responsible for the charge-sensitivity. To prove the principle, we have fabricated and modified an OFET to achieve proton sensitivity. The device concept, testing procedure and the pH response are presented.
{"title":"Organic-based transducer for low-cost charge detection in aqueous media","authors":"C. Bartic, A. Campitelli, K. Baert, J. Suls, S. Borghs","doi":"10.1109/IEDM.2000.904343","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904343","url":null,"abstract":"In this paper we describe a new application for organic field-effect transistors (OFETs) as sensing devices for charge detection in aqueous media. The detection principle is based on the field-enhanced conduction that occurs in organic semiconductors in a similar way as in the crystalline inorganic ones. The electrochemical potential developed at the solution/dielectric interface is responsible for the charge-sensitivity. To prove the principle, we have fabricated and modified an OFET to achieve proton sensitivity. The device concept, testing procedure and the pH response are presented.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130216769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904282
M. Armacost, A. Augustin, P. Felsner, Y. Feng, G. Friese, J. Heidenreich, G. Hueckel, O. Prigge, K. Stein
A high reliability Metal-Insulator-Metal capacitor integrated into a 0.18 /spl mu/m CMOS foundry technology using Copper interconnects is discussed. Integration solutions specific to Copper processing are described and process yield and reliability results are presented on 0.72 fF//spl mu/m/sup 2/ capacitors. Performance and reliability metrics are shown to be comparable to those formed on Aluminum technologies.
{"title":"A high reliability metal insulator metal capacitor for 0.18 /spl mu/m copper technology","authors":"M. Armacost, A. Augustin, P. Felsner, Y. Feng, G. Friese, J. Heidenreich, G. Hueckel, O. Prigge, K. Stein","doi":"10.1109/IEDM.2000.904282","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904282","url":null,"abstract":"A high reliability Metal-Insulator-Metal capacitor integrated into a 0.18 /spl mu/m CMOS foundry technology using Copper interconnects is discussed. Integration solutions specific to Copper processing are described and process yield and reliability results are presented on 0.72 fF//spl mu/m/sup 2/ capacitors. Performance and reliability metrics are shown to be comparable to those formed on Aluminum technologies.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130362394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904298
M. Fujiwara, M. Takayanagi, T. Shimizu, Y. Toyoshima
In this work, the characteristics of CMOSFETs with heavily nitrided NO oxynitrides, which meet performance and manufacturability criteria, are investigated. The gate leakage current in NO oxynitride with sufficient nitridation is reduced by a factor of more than 10 when compared with thermal oxide of equivalent thickness. It is projected that NO oxynitride can be scaled down to an effective physical oxide thickness of 1.5 nm while maintaining strong resistance to B penetration and low standby power. Significantly enhanced diffusion of B in the Si substrate is observed during NO annealing. It is revealed that the magnitude of the diffusivity enhancement strongly depends on the NO annealing temperature, suggesting that the NO anneal process should be carefully optimized to minimize the channel/well dopant redistribution. Additionally, optimum device design for CMOSFETs with heavily nitrided NO oxynitrides is studied. It is experimentally demonstrated that careful tailoring of doping profiles for halo and S/D regions is required to minimize short-channel device degradation in heavily nitrided devices.
{"title":"Extending gate dielectric scaling limit by NO oxynitride: design and process issues for sub-100 nm technology","authors":"M. Fujiwara, M. Takayanagi, T. Shimizu, Y. Toyoshima","doi":"10.1109/IEDM.2000.904298","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904298","url":null,"abstract":"In this work, the characteristics of CMOSFETs with heavily nitrided NO oxynitrides, which meet performance and manufacturability criteria, are investigated. The gate leakage current in NO oxynitride with sufficient nitridation is reduced by a factor of more than 10 when compared with thermal oxide of equivalent thickness. It is projected that NO oxynitride can be scaled down to an effective physical oxide thickness of 1.5 nm while maintaining strong resistance to B penetration and low standby power. Significantly enhanced diffusion of B in the Si substrate is observed during NO annealing. It is revealed that the magnitude of the diffusivity enhancement strongly depends on the NO annealing temperature, suggesting that the NO anneal process should be carefully optimized to minimize the channel/well dopant redistribution. Additionally, optimum device design for CMOSFETs with heavily nitrided NO oxynitrides is studied. It is experimentally demonstrated that careful tailoring of doping profiles for halo and S/D regions is required to minimize short-channel device degradation in heavily nitrided devices.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127153519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904275
R. Bolam, G. Shahidi, F. Assaderaghi, M. Khare, A. Mocuta, T. Hook, E. Wu, E. Leobandung, S. Voldman, D. Badami
Understanding the reliability implications for silicon-on-insulator (SOI) is crucial for its use in ULSI technology. The fabrication process of SOI material and the device operation, due to the buried oxide (BOX) layer, could present additional concerns for meeting reliability requirements. In this paper, we discuss the reliability issues with silicon-on-insulator (SOI) technology. We focus on partially depleted (PD) SOI CMOS technology using SIMOX and bonded substrate material. We compare the reliability mechanisms, namely channel hot electron (CHE), gate oxide time dependent dielectric breakdown (TDDB), bias temperature stress (BTS) and plasma-induced charging damage, to bulk CMOS. In addition, results from high performance microprocessors subjected to burn-in stress are presented. Finally, we discuss the circuitry implications for electrostatic discharge (ESD).
了解绝缘体上硅(SOI)的可靠性影响对于其在ULSI技术中的应用至关重要。由于埋藏氧化物(BOX)层的存在，SOI材料的制造过程和器件操作可能会对满足可靠性要求提出额外的担忧。本文讨论了绝缘体上硅(SOI)技术的可靠性问题。我们专注于使用SIMOX和键合衬底材料的部分耗尽(PD) SOI CMOS技术。我们比较了本体CMOS的可靠性机制，即通道热电子(CHE)、栅极氧化物时间相关介电击穿(TDDB)、偏置温度应力(BTS)和等离子体诱导充电损伤。此外，还介绍了高性能微处理器在老化应力下的测试结果。最后，我们讨论了静电放电(ESD)的电路含义。
{"title":"Reliability issues for silicon-on-insulator","authors":"R. Bolam, G. Shahidi, F. Assaderaghi, M. Khare, A. Mocuta, T. Hook, E. Wu, E. Leobandung, S. Voldman, D. Badami","doi":"10.1109/IEDM.2000.904275","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904275","url":null,"abstract":"Understanding the reliability implications for silicon-on-insulator (SOI) is crucial for its use in ULSI technology. The fabrication process of SOI material and the device operation, due to the buried oxide (BOX) layer, could present additional concerns for meeting reliability requirements. In this paper, we discuss the reliability issues with silicon-on-insulator (SOI) technology. We focus on partially depleted (PD) SOI CMOS technology using SIMOX and bonded substrate material. We compare the reliability mechanisms, namely channel hot electron (CHE), gate oxide time dependent dielectric breakdown (TDDB), bias temperature stress (BTS) and plasma-induced charging damage, to bulk CMOS. In addition, results from high performance microprocessors subjected to burn-in stress are presented. Finally, we discuss the circuitry implications for electrostatic discharge (ESD).","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127424150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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