Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904453
Q. Xiang, J. Jeon, P. Sachdey, B. Yu, K. Saraswat, M. Lin
In this work, we report very high performance CMOS devices with 40 nm physical gate length, 12 A (EOT) nitride/oxynitride (N/O) stack gate dielectrics, and dual pre-doped poly-Si gate electrodes. The strong boron penetration resistance of the high quality N/O stack gate dielectric allows pre-doped poly gates not only for NMOS, but also for PMOS, to minimize poly depletion and improve performance. At room temperature and power supply Vdd of 1.5 V, drive currents of 1.12 mA/um for NMOS and 545 uA/um for PMOS are achieved at off-state leakage Idoff of both devices on the order of 20 nA/um. At low temperature of -50 C and proper forward body biases, those devices showed drive currents of 1.4 mA/m/um (@ 20 nA/um Idoff) for NMOS and 620 uA/um (@ 20 nA/um Idoff) for PMOS. These represent the highest 40 nm CMOS performance figures reported to date.
{"title":"Very high performance 40 nm CMOS with ultra-thin nitride/oxynitride stack gate dielectric and pre-doped dual poly-Si gate electrodes","authors":"Q. Xiang, J. Jeon, P. Sachdey, B. Yu, K. Saraswat, M. Lin","doi":"10.1109/IEDM.2000.904453","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904453","url":null,"abstract":"In this work, we report very high performance CMOS devices with 40 nm physical gate length, 12 A (EOT) nitride/oxynitride (N/O) stack gate dielectrics, and dual pre-doped poly-Si gate electrodes. The strong boron penetration resistance of the high quality N/O stack gate dielectric allows pre-doped poly gates not only for NMOS, but also for PMOS, to minimize poly depletion and improve performance. At room temperature and power supply Vdd of 1.5 V, drive currents of 1.12 mA/um for NMOS and 545 uA/um for PMOS are achieved at off-state leakage Idoff of both devices on the order of 20 nA/um. At low temperature of -50 C and proper forward body biases, those devices showed drive currents of 1.4 mA/m/um (@ 20 nA/um Idoff) for NMOS and 620 uA/um (@ 20 nA/um Idoff) for PMOS. These represent the highest 40 nm CMOS performance figures reported to date.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122954572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904302
A. Hokazono, K. Ohuchi, K. Miyano, I. Mizushima, Y. Tsunashima, Y. Toyoshima
High performance sub-100 nm MOSFETs have been realized utilizing elevated source/drain technologies. By utilizing the selective epitaxial growth process, the suppression of short channel effect, junction leakage current, and parasitic resistance are realized. Moreover, the necessity of special technique for channel engineering in order not to increase the gate-to-source/drain capacitance is described when using elevated source/drain structures. A novel prohibition process of deposition on poly-Si gate electrodes for reducing gate depletion is also mentioned.
{"title":"Source/drain engineering for sub-100 nm CMOS using selective epitaxial growth technique","authors":"A. Hokazono, K. Ohuchi, K. Miyano, I. Mizushima, Y. Tsunashima, Y. Toyoshima","doi":"10.1109/IEDM.2000.904302","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904302","url":null,"abstract":"High performance sub-100 nm MOSFETs have been realized utilizing elevated source/drain technologies. By utilizing the selective epitaxial growth process, the suppression of short channel effect, junction leakage current, and parasitic resistance are realized. Moreover, the necessity of special technique for channel engineering in order not to increase the gate-to-source/drain capacitance is described when using elevated source/drain structures. A novel prohibition process of deposition on poly-Si gate electrodes for reducing gate depletion is also mentioned.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133346269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904393
M. Lu, C. Madigan, J. Sturm
High-index-of-refraction substrates are shown theoretically and experimentally to increase the external coupling efficiency of organic light-emitting devices (OLEDs) by using a quantum mechanical microcavity model. This increase is due to the elimination of those modes waveguided in the ITO/organic layer. Bi-layer OLEDs were fabricated on standard soda lime glass and high-index glass substrates, and their far-field intensity pattern was measured. Among the devices optimized for external efficiency, those on shaped high-index substrates exhibited a 53% improvement in external quantum efficiency over the devices on shaped standard glass substrates, and an increase by a factor of 2-3 times over those on planar glass substrates. This principle is applicable to any backside patterning technique in conjunction with other OLED structural improvements.
{"title":"Improved external coupling efficiency in organic light-emitting devices on high-index substrates","authors":"M. Lu, C. Madigan, J. Sturm","doi":"10.1109/IEDM.2000.904393","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904393","url":null,"abstract":"High-index-of-refraction substrates are shown theoretically and experimentally to increase the external coupling efficiency of organic light-emitting devices (OLEDs) by using a quantum mechanical microcavity model. This increase is due to the elimination of those modes waveguided in the ITO/organic layer. Bi-layer OLEDs were fabricated on standard soda lime glass and high-index glass substrates, and their far-field intensity pattern was measured. Among the devices optimized for external efficiency, those on shaped high-index substrates exhibited a 53% improvement in external quantum efficiency over the devices on shaped standard glass substrates, and an increase by a factor of 2-3 times over those on planar glass substrates. This principle is applicable to any backside patterning technique in conjunction with other OLED structural improvements.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133531250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904252
S.J. Lee, H. Luan, W. Bai, C. Lee, T. Jeon, Y. Senzaki, D. Roberts, D. Kwong
We have developed and demonstrated an in-situ rapid thermal CVD (RTCVD) process for the fabrication of high quality ultra thin CVD HfO/sub 2/ gate stack that is compatible with conventional self-aligned poly-Si gate technology. These poly-Si gated HfO/sub 2/ gate stack show excellent interface properties, EOT=10.4 /spl Aring/, and leakage current Jg=0.23 mA/cm/sup 2/ @Vg=-1 V which is several orders of magnitude lower than RTO SiO/sub 2/ with poly-Si gate. In addition, the HfO/sub 2/ gate stack is thermally stable in direct contact with n/sup +/-poly Si gate under typical dopant activation conditions. These films also show excellent reliability under high-field electrical stress. We have also fabricated and demonstrated NMOSFETs, and studied boron penetration in HfO/sub 2/ gate stack with p/sup +/-poly Si gate.
{"title":"High quality ultra thin CVD HfO/sub 2/ gate stack with poly-Si gate electrode","authors":"S.J. Lee, H. Luan, W. Bai, C. Lee, T. Jeon, Y. Senzaki, D. Roberts, D. Kwong","doi":"10.1109/IEDM.2000.904252","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904252","url":null,"abstract":"We have developed and demonstrated an in-situ rapid thermal CVD (RTCVD) process for the fabrication of high quality ultra thin CVD HfO/sub 2/ gate stack that is compatible with conventional self-aligned poly-Si gate technology. These poly-Si gated HfO/sub 2/ gate stack show excellent interface properties, EOT=10.4 /spl Aring/, and leakage current Jg=0.23 mA/cm/sup 2/ @Vg=-1 V which is several orders of magnitude lower than RTO SiO/sub 2/ with poly-Si gate. In addition, the HfO/sub 2/ gate stack is thermally stable in direct contact with n/sup +/-poly Si gate under typical dopant activation conditions. These films also show excellent reliability under high-field electrical stress. We have also fabricated and demonstrated NMOSFETs, and studied boron penetration in HfO/sub 2/ gate stack with p/sup +/-poly Si gate.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131768869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904322
K. Deguchi, S. Uno, A. Ishida, T. Hirose, Y. Kamakura, K. Taniguchi
Degradation of ultra-thin gate oxide films accompanied by hole direct tunneling is investigated using a substrate hot hole injection technique. Although cold hole injection from the inversion layer of p-MOSFET does not affect the oxide reliability, the drastic degradation during the hot hole injection was observed. The new experimental findings on the hot-hole induced oxide degradation are well explained by the model of two-hole capture by an O vacancy.
{"title":"Degradation of ultra-thin gate oxides accompanied by hole direct tunneling: can we keep long-term reliability of p-MOSFETs?","authors":"K. Deguchi, S. Uno, A. Ishida, T. Hirose, Y. Kamakura, K. Taniguchi","doi":"10.1109/IEDM.2000.904322","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904322","url":null,"abstract":"Degradation of ultra-thin gate oxide films accompanied by hole direct tunneling is investigated using a substrate hot hole injection technique. Although cold hole injection from the inversion layer of p-MOSFET does not affect the oxide reliability, the drastic degradation during the hot hole injection was observed. The new experimental findings on the hot-hole induced oxide degradation are well explained by the model of two-hole capture by an O vacancy.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134060346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904416
S. Wuu, D. Yaung, C. Tseng, H. Chien, C.S. Wang, Yean-Kuen Hsiao, Chin-Kung Chang, B.J. Chang
A high performance 0.25 um CMOS image sensor technology has been developed to overcome device scaling and process issues. Non-silicide source/drain pixel (3 transistors, 3.3 um/spl times/3.3 um, fill factor: 28%) is provided to reduce dark current and increase photoresponse. By optimizing thermal oxide in STI structure, double ion implanted source/drain junction and using H/sub 2/ annealing, the dark current can be drastically reduced (less than 0.5 fA per pixel). The color pixel performance with microlens and related crosstalk characters are also reported in this paper. Two photodiode structures are used to characterize pixel performance. The result shows NW/Psub photodiode demonstrate reduced dark current and higher sensitivity than N+PW diode.
{"title":"High performance 0.25-um CMOS color imager technology with non-silicide source/drain pixel","authors":"S. Wuu, D. Yaung, C. Tseng, H. Chien, C.S. Wang, Yean-Kuen Hsiao, Chin-Kung Chang, B.J. Chang","doi":"10.1109/IEDM.2000.904416","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904416","url":null,"abstract":"A high performance 0.25 um CMOS image sensor technology has been developed to overcome device scaling and process issues. Non-silicide source/drain pixel (3 transistors, 3.3 um/spl times/3.3 um, fill factor: 28%) is provided to reduce dark current and increase photoresponse. By optimizing thermal oxide in STI structure, double ion implanted source/drain junction and using H/sub 2/ annealing, the dark current can be drastically reduced (less than 0.5 fA per pixel). The color pixel performance with microlens and related crosstalk characters are also reported in this paper. Two photodiode structures are used to characterize pixel performance. The result shows NW/Psub photodiode demonstrate reduced dark current and higher sensitivity than N+PW diode.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134087933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904273
T. Oshima, T. Tamaru, K. Ohmori, H. Aoki, H. Ashihara, Tatsuyuki Saito, H. Yamaguchi, M. Miyauchi, Kazuyoshi Torii, J. Murata, A. Satoh, H. Miyazaki, K. Hinode
Thermal stability of via resistance in the multilevel dual damascene Cu interconnection was investigated. The via resistance stability strongly depends on via size, via density and width of connecting Cu wires. The significant via-resistance shift was introduced by stress-induced voiding. To avoid the voiding failure, optimization of heat treatments after electroplating (EP)-Cu deposition are necessary for both stability of Cu films and adhesion of barrier layer with Cu. Thermal stress balance between Cu wires and inter-level-dielectric (ILD) is also important to suppress the via degradation. The dual damascene structure with lower-stress and lower-Young's modulus ILD films such as FSG can provide wider process windows for the stability of the via resistance.
{"title":"Improvement of thermal stability of via resistance in dual damascene copper interconnection","authors":"T. Oshima, T. Tamaru, K. Ohmori, H. Aoki, H. Ashihara, Tatsuyuki Saito, H. Yamaguchi, M. Miyauchi, Kazuyoshi Torii, J. Murata, A. Satoh, H. Miyazaki, K. Hinode","doi":"10.1109/IEDM.2000.904273","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904273","url":null,"abstract":"Thermal stability of via resistance in the multilevel dual damascene Cu interconnection was investigated. The via resistance stability strongly depends on via size, via density and width of connecting Cu wires. The significant via-resistance shift was introduced by stress-induced voiding. To avoid the voiding failure, optimization of heat treatments after electroplating (EP)-Cu deposition are necessary for both stability of Cu films and adhesion of barrier layer with Cu. Thermal stress balance between Cu wires and inter-level-dielectric (ILD) is also important to suppress the via degradation. The dual damascene structure with lower-stress and lower-Young's modulus ILD films such as FSG can provide wider process windows for the stability of the via resistance.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122167951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904306
TingYen Chiang, K. Banerjee, K. Saraswat
This paper reports the impact of vias on the spatial distribution of temperature rise in metal lines and shows that the temperature is highly dependent on the via separation. A 3D electro-thermal simulation methodology using a short-pulse stress is presented to evaluate interconnect design options from a thermal point of view. The simulation methodology has also been applied to quantify the use of dummy thermal vias as additional heat sinking paths to alleviate the temperature rise in the metal wires for the first time. Finally, the impact of metal wire aspect ratio and low-k dielectrics on interconnect thermal characteristics is discussed.
{"title":"Effect of via separation and low-k dielectric materials on the thermal characteristics of Cu interconnects","authors":"TingYen Chiang, K. Banerjee, K. Saraswat","doi":"10.1109/IEDM.2000.904306","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904306","url":null,"abstract":"This paper reports the impact of vias on the spatial distribution of temperature rise in metal lines and shows that the temperature is highly dependent on the via separation. A 3D electro-thermal simulation methodology using a short-pulse stress is presented to evaluate interconnect design options from a thermal point of view. The simulation methodology has also been applied to quantify the use of dummy thermal vias as additional heat sinking paths to alleviate the temperature rise in the metal wires for the first time. Finally, the impact of metal wire aspect ratio and low-k dielectrics on interconnect thermal characteristics is discussed.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125334770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904335
H. Masato, Y. Ikeda, T. Matsuno, K. Inoue, K. Nishii
We have developed novel selective thermal oxidation process for AlGaN/GaN Heterostructure Field Effect Transistors (HFETs) and realized extremely high device isolation and high drain breakdown voltage device of over 100 V. The leakage current of device isolation between two active islands exhibited drastic reduction of 5 order of magnitude smaller than that of conventional mesa isolation process. Moreover, the fabricated 1.3 /spl mu/m-gatelength AlGaN/GaN HFETs exhibited maximum transconductance (gm/sub max/) of 130 mS/mm, maximum drain current (I/sub max/) of 500 mA/mm and excellent pinch off characteristics at high drain voltage of over 120 V.
{"title":"Novel high drain breakdown voltage AlGaN/GaN HFETs using selective thermal oxidation process","authors":"H. Masato, Y. Ikeda, T. Matsuno, K. Inoue, K. Nishii","doi":"10.1109/IEDM.2000.904335","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904335","url":null,"abstract":"We have developed novel selective thermal oxidation process for AlGaN/GaN Heterostructure Field Effect Transistors (HFETs) and realized extremely high device isolation and high drain breakdown voltage device of over 100 V. The leakage current of device isolation between two active islands exhibited drastic reduction of 5 order of magnitude smaller than that of conventional mesa isolation process. Moreover, the fabricated 1.3 /spl mu/m-gatelength AlGaN/GaN HFETs exhibited maximum transconductance (gm/sub max/) of 130 mS/mm, maximum drain current (I/sub max/) of 500 mA/mm and excellent pinch off characteristics at high drain voltage of over 120 V.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128718129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904423
L. Larson
The rapid deployment of next generation communications systems-both wired and wireless-on a worldwide basis creates a unique opportunity for the semiconductor industry. High-speed networks require massive computing power and analog and radio frequency devices with wide dynamic range and bandwidth. The semiconductor technologies required to implement these systems will be highlighted, with particular emphasis on the technologies required to meet the demands of mobile computing applications.
{"title":"Device and technology requirements for next generation communications systems","authors":"L. Larson","doi":"10.1109/IEDM.2000.904423","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904423","url":null,"abstract":"The rapid deployment of next generation communications systems-both wired and wireless-on a worldwide basis creates a unique opportunity for the semiconductor industry. High-speed networks require massive computing power and analog and radio frequency devices with wide dynamic range and bandwidth. The semiconductor technologies required to implement these systems will be highlighted, with particular emphasis on the technologies required to meet the demands of mobile computing applications.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122408693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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