Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904255
R. Chau, J. Kavalieros, B. Roberds, R. Schenker, D. Lionberger, D. Barlage, B. Doyle, R. Arghavani, A. Murthy, G. Dewey
Planar CMOS transistors have been fabricated to evaluate the 70 nm technology node using conventional transistor design methodologies. Conventional CMOS transistors with 30 nm physical gate length were fabricated using aggressively scaled junctions, polysilicon gate electrode, gate oxide and Ni silicide. These devices have inversion Cox exceeding 1.9 /spl mu/F/cm2, n-MOS gate delay (CV/I) of 0.94 ps and p-MOS gate delay of 1.7 ps at V/sub cc/=0.85 V. These are the smallest CV/I values ever reported for Si CMOS devices. The transistors also show good short channel control and subthreshold swings. The n-MOS and p-MOS have drive currents equal to 514 /spl mu/A//spl mu/m and 285 /spl mu/A//spl mu/m respectively with I/sub off/ at or below 100 nA//spl mu/m at Vcc=0.85 V. The saturation gm is equal to 1200 mS/mm for n-MOS and 640 mS/mm for p-MOS. These are among the highest gm values ever reported. The junction edge leakage is reasonably low with less than 1 nA//spl mu/m at 1.0 V and 100 C for both n-MOS and p-MOS. These encouraging results suggest that the 70 nm technology node is achievable using conventional planar transistor design and process flow.
{"title":"30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays","authors":"R. Chau, J. Kavalieros, B. Roberds, R. Schenker, D. Lionberger, D. Barlage, B. Doyle, R. Arghavani, A. Murthy, G. Dewey","doi":"10.1109/IEDM.2000.904255","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904255","url":null,"abstract":"Planar CMOS transistors have been fabricated to evaluate the 70 nm technology node using conventional transistor design methodologies. Conventional CMOS transistors with 30 nm physical gate length were fabricated using aggressively scaled junctions, polysilicon gate electrode, gate oxide and Ni silicide. These devices have inversion Cox exceeding 1.9 /spl mu/F/cm2, n-MOS gate delay (CV/I) of 0.94 ps and p-MOS gate delay of 1.7 ps at V/sub cc/=0.85 V. These are the smallest CV/I values ever reported for Si CMOS devices. The transistors also show good short channel control and subthreshold swings. The n-MOS and p-MOS have drive currents equal to 514 /spl mu/A//spl mu/m and 285 /spl mu/A//spl mu/m respectively with I/sub off/ at or below 100 nA//spl mu/m at Vcc=0.85 V. The saturation gm is equal to 1200 mS/mm for n-MOS and 640 mS/mm for p-MOS. These are among the highest gm values ever reported. The junction edge leakage is reasonably low with less than 1 nA//spl mu/m at 1.0 V and 100 C for both n-MOS and p-MOS. These encouraging results suggest that the 70 nm technology node is achievable using conventional planar transistor design and process flow.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114814921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904357
Y. Hirano, T. Matsumoto, S. Maeda, T. Iwamatsu, T. Kunikiyo, K. Nii, K. Yamamoto, Y. Yamaguchi, T. Ipposhi, S. Maegawa, M. Inuishi
A hybrid-trench-isolation (HTI) technology is proposed to overcome the scaling limitations caused by the difficulty of gate thinning and increased soft error rate at the 0.1 /spl mu/m era. It is revealed that a significant speed improvement against bulk is achieved by using the body-tied structure without floating-body-relate speed deterioration. A two-order reduction in the soft error rate for an HTI-SOI 4M-bit SRAM was demonstrated as compared with bulk structure. Moreover, it is shown that full trench isolation in the HTI offers excellent isolation characteristics to realize the one-chip integration of analog and digital LSI's. It is concluded that SOI technology with HTI structure is one of the solutions against the scaling limitations.
{"title":"Impact of 0.10 /spl mu/m SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology","authors":"Y. Hirano, T. Matsumoto, S. Maeda, T. Iwamatsu, T. Kunikiyo, K. Nii, K. Yamamoto, Y. Yamaguchi, T. Ipposhi, S. Maegawa, M. Inuishi","doi":"10.1109/IEDM.2000.904357","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904357","url":null,"abstract":"A hybrid-trench-isolation (HTI) technology is proposed to overcome the scaling limitations caused by the difficulty of gate thinning and increased soft error rate at the 0.1 /spl mu/m era. It is revealed that a significant speed improvement against bulk is achieved by using the body-tied structure without floating-body-relate speed deterioration. A two-order reduction in the soft error rate for an HTI-SOI 4M-bit SRAM was demonstrated as compared with bulk structure. Moreover, it is shown that full trench isolation in the HTI offers excellent isolation characteristics to realize the one-chip integration of analog and digital LSI's. It is concluded that SOI technology with HTI structure is one of the solutions against the scaling limitations.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114852280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904424
K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, M. Kondo, T. Hashimoto, T. Harada
A 0.2-/spl mu/m self-aligned selective-epitaxial-growth (SEG) SiGe heterojunction bipolar transistor (HBT)/CMOS technology with high-quality passive elements, made by using SOI on a high-resistivity substrate (SOI/HRS), was developed. The SiGe HBTs exhibited high-frequency, high-speed capability with f/sub max/ of 180 GHz and a fast ECL-gate delay of 6.7 ps.
{"title":"A 0.2-/spl mu/m 180-GHz-f/sub max/ 6.7-ps-ECL SOI/HRS self aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications","authors":"K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, M. Kondo, T. Hashimoto, T. Harada","doi":"10.1109/IEDM.2000.904424","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904424","url":null,"abstract":"A 0.2-/spl mu/m self-aligned selective-epitaxial-growth (SEG) SiGe heterojunction bipolar transistor (HBT)/CMOS technology with high-quality passive elements, made by using SOI on a high-resistivity substrate (SOI/HRS), was developed. The SiGe HBTs exhibited high-frequency, high-speed capability with f/sub max/ of 180 GHz and a fast ECL-gate delay of 6.7 ps.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127601195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904317
T. Ishii, T. Osabe, T. Mine, F. Murai, K. Yano
The origin of device characteristic deviations of a single or a few-electrons memory, which are the most serious obstacles to achieving a practical memory, is studied from the viewpoint of fluctuation of storage dots. Our model, in which dot occupation area is essential for device characteristics, is compared to the measured characteristics of fabricated memory cells with various dot radii and densities. The potential to achieve gigabit class memory is demonstrated. Manufacturing enhancement by isolated-dots storage (MEID) is proposed as the practical benefit of nonvolatile multi-dot memories.
{"title":"Engineering variations: towards practical single-electron (few-electron) memory","authors":"T. Ishii, T. Osabe, T. Mine, F. Murai, K. Yano","doi":"10.1109/IEDM.2000.904317","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904317","url":null,"abstract":"The origin of device characteristic deviations of a single or a few-electrons memory, which are the most serious obstacles to achieving a practical memory, is studied from the viewpoint of fluctuation of storage dots. Our model, in which dot occupation area is essential for device characteristics, is compared to the measured characteristics of fabricated memory cells with various dot radii and densities. The potential to achieve gigabit class memory is demonstrated. Manufacturing enhancement by isolated-dots storage (MEID) is proposed as the practical benefit of nonvolatile multi-dot memories.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134556088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904382
K. K. Young, S. Wu, C.C. Wu, C. Wang, C. Lin, J.Y. Cheng, M. Chiang, S. Chen, T. Lo, Y.S. Chen, J.H. Chen, L. Chen, S. Hou, J. J. Law, T. Chang, C. Hou, J. Shih, S. Jeng, H. Hsieh, Y. Ku, T. Yen, H. Tao, L. Chao, S. Shue, S. Jang, T. Ong, C. Yu, M. Liang, C. H. Diaz, J. Sun
A leading-edge 0.13 /spl mu/m CMOS technology using 193 nm lithography and Cu/low-k interconnect is described in this paper. High performance 80 nm core devices use 17 /spl Aring/ nitrided oxide for 1.0-1.2 V operation. These devices deliver unloaded 8.5 ps gate delay @1.2 V. This technology also supports general ASIC applications with 20 /spl Aring/ oxide for 1.2-1.5 V operation and low-standby power applications with 26 /spl Aring/ for 1.5 V operation, respectively. Dual gate oxides of 50 or 65 /spl Aring/ are also supported for 2.5 V or 3.3 V I/O circuits respectively. Cu with low-k dielectric is used for the 8-layer metal interconnect system with tight pitch. The aggressive design rules and border-less contacts/vias support a high density 1P3M 2.43 /spl mu/m/sup 2/ 6T-SRAM cell without local interconnect. A suite of embedded SRAM cells (6T, 8T) with competitive density and performance optimized for different applications are also supported with memory compilers and large block macros.
{"title":"A 0.13 /spl mu/m CMOS technology with 193 nm lithography and Cu/low-k for high performance applications","authors":"K. K. Young, S. Wu, C.C. Wu, C. Wang, C. Lin, J.Y. Cheng, M. Chiang, S. Chen, T. Lo, Y.S. Chen, J.H. Chen, L. Chen, S. Hou, J. J. Law, T. Chang, C. Hou, J. Shih, S. Jeng, H. Hsieh, Y. Ku, T. Yen, H. Tao, L. Chao, S. Shue, S. Jang, T. Ong, C. Yu, M. Liang, C. H. Diaz, J. Sun","doi":"10.1109/IEDM.2000.904382","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904382","url":null,"abstract":"A leading-edge 0.13 /spl mu/m CMOS technology using 193 nm lithography and Cu/low-k interconnect is described in this paper. High performance 80 nm core devices use 17 /spl Aring/ nitrided oxide for 1.0-1.2 V operation. These devices deliver unloaded 8.5 ps gate delay @1.2 V. This technology also supports general ASIC applications with 20 /spl Aring/ oxide for 1.2-1.5 V operation and low-standby power applications with 26 /spl Aring/ for 1.5 V operation, respectively. Dual gate oxides of 50 or 65 /spl Aring/ are also supported for 2.5 V or 3.3 V I/O circuits respectively. Cu with low-k dielectric is used for the 8-layer metal interconnect system with tight pitch. The aggressive design rules and border-less contacts/vias support a high density 1P3M 2.43 /spl mu/m/sup 2/ 6T-SRAM cell without local interconnect. A suite of embedded SRAM cells (6T, 8T) with competitive density and performance optimized for different applications are also supported with memory compilers and large block macros.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128921412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904256
H. Wakabayashi, M. Ueki, M. Narihiro, T. Fukai, N. Ikezawa, T. Matsuda, K. Yoshida, K. Takeuchi, Y. Ochiai, T. Mogami, T. Kunio
45-nm CMOS devices with a steep halo using a high-ramp-rate spike annealing (HRR-SA) are demonstrated with drive currents of 697 and 292 /spl mu/A//spl mu/m for an off current less than 10 nA//spl mu/m at 1.2 V. For an off current less than 300 nA//spl mu/m, 33-nm pMOSFETs have a high drive current of 403 /spl mu/A//spl mu/m at 1.2 V. In order to fabricate a steeper halo than these MOSFETs, a source/drain extension (SDE) activation using the HRR-SA process was performed after a deep source/drain (S/D) formation. By using this sequence defined as a reverse-order S/D formation, 24-nm nMOSFETs are achieved with a high drive current of 796 /spl mu/A//spl mu/m for an off current less than 300 nA//spl mu/m at 1.2 V.
采用高陡坡速率尖峰退火(HRR-SA)的45纳米陡光晕CMOS器件在1.2 V下的关闭电流小于10 nA//spl mu/m，驱动电流分别为697和292 /spl mu/ a //spl mu/m。当关闭电流小于300 nA//spl mu/m时，33 nm pmosfet在1.2 V时具有403 /spl mu/ a //spl mu/m的高驱动电流。为了制造比这些mosfet更陡峭的光晕，在深源/漏极(S/D)形成后，使用HRR-SA工艺进行源/漏极扩展(SDE)激活。通过使用这个定义为反阶S/D形成的序列，在1.2 V下，在小于300 nA//spl mu/m的关闭电流下，实现了796 /spl mu/ a //spl mu/m的高驱动电流的24nm nmosfet。
{"title":"45-nm gate length CMOS technology and beyond using steep halo","authors":"H. Wakabayashi, M. Ueki, M. Narihiro, T. Fukai, N. Ikezawa, T. Matsuda, K. Yoshida, K. Takeuchi, Y. Ochiai, T. Mogami, T. Kunio","doi":"10.1109/IEDM.2000.904256","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904256","url":null,"abstract":"45-nm CMOS devices with a steep halo using a high-ramp-rate spike annealing (HRR-SA) are demonstrated with drive currents of 697 and 292 /spl mu/A//spl mu/m for an off current less than 10 nA//spl mu/m at 1.2 V. For an off current less than 300 nA//spl mu/m, 33-nm pMOSFETs have a high drive current of 403 /spl mu/A//spl mu/m at 1.2 V. In order to fabricate a steeper halo than these MOSFETs, a source/drain extension (SDE) activation using the HRR-SA process was performed after a deep source/drain (S/D) formation. By using this sequence defined as a reverse-order S/D formation, 24-nm nMOSFETs are achieved with a high drive current of 796 /spl mu/A//spl mu/m for an off current less than 300 nA//spl mu/m at 1.2 V.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115423106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904398
D. Elqaq, M. Hasan
A cost efficient, easy to fabricate cathodoluminescent (CL) device that utilizes porous silicon (Si) as a high-density field emitter in a vacuumless layered structure, was fabricated and tested. The structure consists of a porous Si substrate capped with three layers: an active phosphor layer, an insulating layer and a transparent indium-tin-oxide electrode. Electrons emitted from protrusions in porous Si are accelerated toward the phosphor layer where light is generated both upon impact ionization of activator atoms and due to further ballistic acceleration of electrons within the phosphor layer.
{"title":"Fabrication and characterization of cathodoluminescent devices made using porous silicon as a cold-cathode field emitter","authors":"D. Elqaq, M. Hasan","doi":"10.1109/IEDM.2000.904398","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904398","url":null,"abstract":"A cost efficient, easy to fabricate cathodoluminescent (CL) device that utilizes porous silicon (Si) as a high-density field emitter in a vacuumless layered structure, was fabricated and tested. The structure consists of a porous Si substrate capped with three layers: an active phosphor layer, an insulating layer and a transparent indium-tin-oxide electrode. Electrons emitted from protrusions in porous Si are accelerated toward the phosphor layer where light is generated both upon impact ionization of activator atoms and due to further ballistic acceleration of electrons within the phosphor layer.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115806999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904390
D. Klotzkin, J. Sheridan-Eng, A. Mazzatesta, G. Ford, J. Laquindinum, M. Chien, M. Park, E. Michel, R. Kinkel, S. Roycroft, L. Ketelsen, J.E. Johnson, S. K. Sputz, J. Lentz, M. A. Alam, M. Hybertsen, C. Reynolds, K. Glogovsky, D. Stampone, S. Chu, D. Romero, J. Freund, R. Liebenguth, F. Walters
Fabry-Perot and distributed feedback spot size converted 1.3 /spl mu/m lasers are demonstrated with competitive performance (/spl sim/10 mA threshold, >0.30 W/A slope) and narrow (16/spl times/9) far fields capable of coupling 45% of the output light into flat cleaved fiber. The Fabry-Perot device demonstrated error-floor-free transmission at 85/spl deg/C with a wide-open eye, uncooled 2.5 Gb/s operation up to 85/spl deg/C, and reliability of 105 FITS at 50/spl deg/C. The DFB devices have good DC performance with side mode suppression ratios of >40 dB. These devices will allow passive alignment and packaging without the need for intervening optics.
{"title":"Spot-size-converted 1.3 /spl mu/m directly-modulated Fabry-Perot and distributed feedback lasers suitable for passive alignment and 2.5 gb/s operation at 85/spl deg/C","authors":"D. Klotzkin, J. Sheridan-Eng, A. Mazzatesta, G. Ford, J. Laquindinum, M. Chien, M. Park, E. Michel, R. Kinkel, S. Roycroft, L. Ketelsen, J.E. Johnson, S. K. Sputz, J. Lentz, M. A. Alam, M. Hybertsen, C. Reynolds, K. Glogovsky, D. Stampone, S. Chu, D. Romero, J. Freund, R. Liebenguth, F. Walters","doi":"10.1109/IEDM.2000.904390","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904390","url":null,"abstract":"Fabry-Perot and distributed feedback spot size converted 1.3 /spl mu/m lasers are demonstrated with competitive performance (/spl sim/10 mA threshold, >0.30 W/A slope) and narrow (16/spl times/9) far fields capable of coupling 45% of the output light into flat cleaved fiber. The Fabry-Perot device demonstrated error-floor-free transmission at 85/spl deg/C with a wide-open eye, uncooled 2.5 Gb/s operation up to 85/spl deg/C, and reliability of 105 FITS at 50/spl deg/C. The DFB devices have good DC performance with side mode suppression ratios of >40 dB. These devices will allow passive alignment and packaging without the need for intervening optics.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124336555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904299
S. Fung, N. Zamdmer, P. Oldiges, J. Sleight, A. Mocuta, M. Sherony, S.-H. Lo, R. Joshi, C. Chuang, I. Yang, S. Crowder, T. Chen, F. Assaderaghi, G. Shahidi
The ultra-thin gate oxide required for the 0.13 /spl mu/m generation and beyond introduces a significant amount of gate-to-body tunneling current. The gate current modulates the body voltage and therefore the history effect. This paper discusses several methods to minimize the impact of gate current, which can cause excessive history effect in 0.10 /spl mu/m SOI CMOS. Our result demonstrates that the combination of high gate leakage and small junction capacitance can enhance circuit performance due to beneficial gate coupling. Ultra-low junction capacitance can be achieved by aggressive SOI thickness scaling, though, the proximity of source/drain extension and channel depletion to the buried oxide complicates device design and modeling.
0.13 /spl mu/m及以上一代所需的超薄栅极氧化物引入了大量的栅极到体隧穿电流。栅极电流调制体电压，从而调制历史效应。本文讨论了几种减小栅极电流影响的方法，栅极电流在0.10 /spl μ l /m SOI CMOS中会造成过大的历史效应。我们的研究结果表明，高栅漏和小结电容的结合可以提高电路的性能，因为有利的栅极耦合。超低结电容可以通过积极的SOI厚度缩放来实现，但是，源/漏极扩展和通道耗尽与埋藏氧化物的接近使器件设计和建模变得复杂。
{"title":"Controlling floating-body effects for 0.13 /spl mu/m and 0.10 /spl mu/m SOI CMOS","authors":"S. Fung, N. Zamdmer, P. Oldiges, J. Sleight, A. Mocuta, M. Sherony, S.-H. Lo, R. Joshi, C. Chuang, I. Yang, S. Crowder, T. Chen, F. Assaderaghi, G. Shahidi","doi":"10.1109/IEDM.2000.904299","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904299","url":null,"abstract":"The ultra-thin gate oxide required for the 0.13 /spl mu/m generation and beyond introduces a significant amount of gate-to-body tunneling current. The gate current modulates the body voltage and therefore the history effect. This paper discusses several methods to minimize the impact of gate current, which can cause excessive history effect in 0.10 /spl mu/m SOI CMOS. Our result demonstrates that the combination of high gate leakage and small junction capacitance can enhance circuit performance due to beneficial gate coupling. Ultra-low junction capacitance can be achieved by aggressive SOI thickness scaling, though, the proximity of source/drain extension and channel depletion to the buried oxide complicates device design and modeling.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115013382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904421
Sungjun Im, Kaustav Banerjee
This work presents a full chip thermal analysis of 2-D high performance ICs based on technological, structural, and material data from ITRS '99. It is shown that interconnect Joule heating in advanced technology nodes can strongly impact the magnitude of the maximum temperature within 2-D chips despite negligible change in the chip power density, as per the ITRS. This result has been shown to have significant implications for interconnect reliability and performance not foreseeable by the ITRS. Furthermore, detailed thermal analysis of vertically integrated (3-D) ICs has been carried out using analytical modeling and numerical simulations. Additionally, comparison between the thermal design of two alternative 3-D technologies has been presented for the first time using ITRS data.
{"title":"Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs","authors":"Sungjun Im, Kaustav Banerjee","doi":"10.1109/IEDM.2000.904421","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904421","url":null,"abstract":"This work presents a full chip thermal analysis of 2-D high performance ICs based on technological, structural, and material data from ITRS '99. It is shown that interconnect Joule heating in advanced technology nodes can strongly impact the magnitude of the maximum temperature within 2-D chips despite negligible change in the chip power density, as per the ITRS. This result has been shown to have significant implications for interconnect reliability and performance not foreseeable by the ITRS. Furthermore, detailed thermal analysis of vertically integrated (3-D) ICs has been carried out using analytical modeling and numerical simulations. Additionally, comparison between the thermal design of two alternative 3-D technologies has been presented for the first time using ITRS data.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114896390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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