Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904401
Q. Lu, R. Lin, P. Ranade, Y. Yeo, Xiaofan Meng, H. Takeuchi, T. King, C. Hu, H. Luan, Songjoo Lee, W. Bai, Choong-Ho Lee, D. Kwong, Xin Guo, Xiewen Wang, T. Ma
Mo metal gate p-MOSFETs with several advanced gate dielectrics were fabricated. A suitable p-MOSFET work function was achieved and good device characteristics were obtained in all cases. Thermodynamic stability of Mo on Si/sub 3/N/sub 4/, ZrO/sub 2/ and ZrSiO/sub 4/ was verified by good carrier mobility agreement with the universal mobility model.
{"title":"Molybdenum metal gate MOS technology for post-SiO/sub 2/ gate dielectrics","authors":"Q. Lu, R. Lin, P. Ranade, Y. Yeo, Xiaofan Meng, H. Takeuchi, T. King, C. Hu, H. Luan, Songjoo Lee, W. Bai, Choong-Ho Lee, D. Kwong, Xin Guo, Xiewen Wang, T. Ma","doi":"10.1109/IEDM.2000.904401","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904401","url":null,"abstract":"Mo metal gate p-MOSFETs with several advanced gate dielectrics were fabricated. A suitable p-MOSFET work function was achieved and good device characteristics were obtained in all cases. Thermodynamic stability of Mo on Si/sub 3/N/sub 4/, ZrO/sub 2/ and ZrSiO/sub 4/ was verified by good carrier mobility agreement with the universal mobility model.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123513828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904279
M. Carroll, T. Ivanov, S. Kuehne, J. Chu, C. King, M. Frei, M. Mastrapasqua, R. Johnson, K. Ng, S. Moinian, S. Martin, C. Huang, T. Hsu, D. Nguyen, R. Singh, L. Fritzinger, T. Esry, W. Moller, B. Kane, G. Abeln, D. Hwang, D. Orphee, S. Lytle, M. Roby, D. Vitkavage, D. Chesire, R. Ashton, D. Shuttleworth, M. Thoma, S. Choi, S. Lewllen, P. Mason, T. Lai, H. Hsieh, D. Dennis, E. Harris, S. Thomas, R. Gregor, P. Sana, W. Wu
The COM2 SiGe modular BiCMOS technology has been developed to allow efficient design and manufacturing of digital, mixed-signal, and RF integrated circuits, as well as enabling system-on-chip (SOC) integration. The technology is based on the 0.16 /spl mu/m COM2 digital CMOS process which features 1.5 V NMOS and PMOS transistors with 2.4 nm gate oxide, 0.135 /spl mu/m gate length, and up to 7 metal levels. Technology enhancement modules including dense SRAM, SiGe NPN bipolar transistor, and a variety of passive components have been developed to allow the COM2 technology to be cost-effectively optimized for a wide range of applications.
{"title":"COM2 SiGe modular BiCMOS technology for digital, mixed-signal, and RF applications","authors":"M. Carroll, T. Ivanov, S. Kuehne, J. Chu, C. King, M. Frei, M. Mastrapasqua, R. Johnson, K. Ng, S. Moinian, S. Martin, C. Huang, T. Hsu, D. Nguyen, R. Singh, L. Fritzinger, T. Esry, W. Moller, B. Kane, G. Abeln, D. Hwang, D. Orphee, S. Lytle, M. Roby, D. Vitkavage, D. Chesire, R. Ashton, D. Shuttleworth, M. Thoma, S. Choi, S. Lewllen, P. Mason, T. Lai, H. Hsieh, D. Dennis, E. Harris, S. Thomas, R. Gregor, P. Sana, W. Wu","doi":"10.1109/IEDM.2000.904279","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904279","url":null,"abstract":"The COM2 SiGe modular BiCMOS technology has been developed to allow efficient design and manufacturing of digital, mixed-signal, and RF integrated circuits, as well as enabling system-on-chip (SOC) integration. The technology is based on the 0.16 /spl mu/m COM2 digital CMOS process which features 1.5 V NMOS and PMOS transistors with 2.4 nm gate oxide, 0.135 /spl mu/m gate length, and up to 7 metal levels. Technology enhancement modules including dense SRAM, SiGe NPN bipolar transistor, and a variety of passive components have been developed to allow the COM2 technology to be cost-effectively optimized for a wide range of applications.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123686575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904289
R. Quay, V. Palankovski, M. Chertouk, A. Leuther, S. Selberherr
Simulation results of InAlAs/InGaAs High Electron Mobility Transistors based on both GaAs and InP substrates are presented using the two-dimensional device simulator MINIMOS-NT. Three different HEMT technologies are evaluated by simulation and a single set of physical parameters is verified. The critical interaction of self-heating, impact ionization, SiN surface effects, and material composition is incorporated, which renders the simulation results suitable for the evaluation of device reliability issues. Starting from the analysis of gate-currents the simulation model can quantitatively support the basic understanding of this advanced material system.
{"title":"Simulation of InAlAs/InGaAs high electron mobility transistors with a single set of physical parameters","authors":"R. Quay, V. Palankovski, M. Chertouk, A. Leuther, S. Selberherr","doi":"10.1109/IEDM.2000.904289","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904289","url":null,"abstract":"Simulation results of InAlAs/InGaAs High Electron Mobility Transistors based on both GaAs and InP substrates are presented using the two-dimensional device simulator MINIMOS-NT. Three different HEMT technologies are evaluated by simulation and a single set of physical parameters is verified. The critical interaction of self-heating, impact ionization, SiN surface effects, and material composition is incorporated, which renders the simulation results suitable for the evaluation of device reliability issues. Starting from the analysis of gate-currents the simulation model can quantitatively support the basic understanding of this advanced material system.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129378497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904442
K. Cao, W. Lee, Weidong Liu, X. Jin, P. Su, S. Fung, J. An, B. Yu, Chenming Hu
Gate dielectric leakage current becomes a serious concern as sub-20 /spl Aring/ gate oxide prevails in advanced CMOS processes. Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance. While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage. In this work, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed. This model has been implemented in BSIM4.
{"title":"BSIM4 gate leakage model including source-drain partition","authors":"K. Cao, W. Lee, Weidong Liu, X. Jin, P. Su, S. Fung, J. An, B. Yu, Chenming Hu","doi":"10.1109/IEDM.2000.904442","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904442","url":null,"abstract":"Gate dielectric leakage current becomes a serious concern as sub-20 /spl Aring/ gate oxide prevails in advanced CMOS processes. Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance. While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage. In this work, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed. This model has been implemented in BSIM4.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127315385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904280
T. Hashimoto, F. Sato, T. Aoyama, H. Suzuki, H. Yoshida, H. Fujii, T. Yamazaki
This paper describes a 73 GHz f/sub T/ 0.18 /spl mu/m SiGe BiCMOS technology. This BiCMOS technology has the following key points: (1) The 2-step annealing technique for CMOS is utilized to solve the thermal budget trade-off between SiGe HBTs and CMOS. (2) A robust Ge profile design is implemented to improve the thermal stability of the SiGe base layer. (3) The Si-spacer layer is inserted between the Si collector and the SiGe base layer in order to reduce undesirable boron-spike effect. This process yields the SiGe HBT with f/sub T/ of 73 GHz and f/sub max/ of 61 GHz without compromising 0.18 /spl mu/m p/sup +//n/sup +/ dual gate CMOS characteristics.
{"title":"A 73 GHz f/sub T/ 0.18 /spl mu/m RF-SiGe BiCMOS technology considering thermal budget trade-off and with reduced boron-spike effect on HBT characteristics","authors":"T. Hashimoto, F. Sato, T. Aoyama, H. Suzuki, H. Yoshida, H. Fujii, T. Yamazaki","doi":"10.1109/IEDM.2000.904280","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904280","url":null,"abstract":"This paper describes a 73 GHz f/sub T/ 0.18 /spl mu/m SiGe BiCMOS technology. This BiCMOS technology has the following key points: (1) The 2-step annealing technique for CMOS is utilized to solve the thermal budget trade-off between SiGe HBTs and CMOS. (2) A robust Ge profile design is implemented to improve the thermal stability of the SiGe base layer. (3) The Si-spacer layer is inserted between the Si collector and the SiGe base layer in order to reduce undesirable boron-spike effect. This process yields the SiGe HBT with f/sub T/ of 73 GHz and f/sub max/ of 61 GHz without compromising 0.18 /spl mu/m p/sup +//n/sup +/ dual gate CMOS characteristics.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128957067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904300
S. Song, J. Yi, W.S. Kim, J.S. Lee, K. Fujihara, H. Kang, J. Moon, M.Y. Lee
CMOS device scaling beyond 100 nm has been investigated. Issues on scaling and previous works to solve them were reviewed. Super steep retrograde channel formation using selective epitaxial growth of undoped silicon effectively suppressed short channel effect and improved transconductance. The stack gate dielectrics of oxynitride and nitride suppressed boron penetration and improved drive currents. Transistor characteristics and reliability issues on gate oxide scaling were investigated in the regime of large gate leakage currents. High performance CMOS transistors of L/sub gate/=70 nm and T/sub ox/=1.4 nm were fabricated, which showed current drives of 860 /spl mu/A//spl mu/m (NMOS) and 350 /spl mu/A//spl mu/m (PMOS) at I/sub off/=10 nA//spl mu/m and V/sub dd/=1.2 V.
{"title":"CMOS device scaling beyond 100 nm","authors":"S. Song, J. Yi, W.S. Kim, J.S. Lee, K. Fujihara, H. Kang, J. Moon, M.Y. Lee","doi":"10.1109/IEDM.2000.904300","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904300","url":null,"abstract":"CMOS device scaling beyond 100 nm has been investigated. Issues on scaling and previous works to solve them were reviewed. Super steep retrograde channel formation using selective epitaxial growth of undoped silicon effectively suppressed short channel effect and improved transconductance. The stack gate dielectrics of oxynitride and nitride suppressed boron penetration and improved drive currents. Transistor characteristics and reliability issues on gate oxide scaling were investigated in the regime of large gate leakage currents. High performance CMOS transistors of L/sub gate/=70 nm and T/sub ox/=1.4 nm were fabricated, which showed current drives of 860 /spl mu/A//spl mu/m (NMOS) and 350 /spl mu/A//spl mu/m (PMOS) at I/sub off/=10 nA//spl mu/m and V/sub dd/=1.2 V.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125668283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904418
Z. Ren, R. Venugopal, S. Datta, Mark S. Lundstrom, D. Jovanovic, J. Fossum
The device design and physics issues of ballistic double-gate (DG) MOSFETs are explored using semiclassical and quantum simulations. We find that tunneling from source-to-drain increases the off-current but decreases the on-current for an L=10 nm model transistor. We also show that source-to-drain tunneling sets a scaling limit at less than about L=10 nm, but to achieve this limit, ultra-thin bodies are necessary to control classical two-dimensional short-channel effects. Finally, we show that to meet performance targets at low voltages, near-ballistic performance is necessary, and we estimate the mobility that will be required for these ultra-thin silicon films.
{"title":"The ballistic nanotransistor: a simulation study","authors":"Z. Ren, R. Venugopal, S. Datta, Mark S. Lundstrom, D. Jovanovic, J. Fossum","doi":"10.1109/IEDM.2000.904418","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904418","url":null,"abstract":"The device design and physics issues of ballistic double-gate (DG) MOSFETs are explored using semiclassical and quantum simulations. We find that tunneling from source-to-drain increases the off-current but decreases the on-current for an L=10 nm model transistor. We also show that source-to-drain tunneling sets a scaling limit at less than about L=10 nm, but to achieve this limit, ultra-thin bodies are necessary to control classical two-dimensional short-channel effects. Finally, we show that to meet performance targets at low voltages, near-ballistic performance is necessary, and we estimate the mobility that will be required for these ultra-thin silicon films.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121159239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904268
C. Jungemann, B. Heinemann, K. Tittelbach-Helmrich, B. Meinerzhagen
The electron minority mobility in Si and SiGe is extracted from high-field magnetoconductance experiments on SiGe heterojunction bipolar transistors based on a new electron transport model. The transport model is verified by comparison with magnetoresistance experiments for lightly doped Si. After calibrating an empirical parameter of the impurity scattering model against data for highly doped Si, good results are obtained for SiGe without any further fitting.
{"title":"An accurate, experimentally verified electron minority carrier mobility model for Si and SiGe","authors":"C. Jungemann, B. Heinemann, K. Tittelbach-Helmrich, B. Meinerzhagen","doi":"10.1109/IEDM.2000.904268","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904268","url":null,"abstract":"The electron minority mobility in Si and SiGe is extracted from high-field magnetoconductance experiments on SiGe heterojunction bipolar transistors based on a new electron transport model. The transport model is verified by comparison with magnetoresistance experiments for lightly doped Si. After calibrating an empirical parameter of the impurity scattering model against data for highly doped Si, good results are obtained for SiGe without any further fitting.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116055446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904417
A. Pauchard, A. Rochas, Z. Randjelovic, P. Besse, R. Popovic
We present a simple method that allows the fabrication of ultraviolet-selective avalanche photodiodes in a standard CMOS technology. An efficient guard ring structure is created using the lateral diffusion of two n/sub well/ regions separated by a gap of 0.6 /spl mu/m. Our photodiodes achieve a very low dark current of only 400 pA/mm/sup 2/, an excess noise F=7 for a mean gain =20 at /spl lambda/=400 nm, and a good gain uniformity.
我们提出了一种简单的方法，允许在标准CMOS技术中制造紫外选择性雪崩光电二极管。通过0.6 /spl mu/m的间隙将两个n/子井/区域横向扩散，形成了一个有效的保护环结构。我们的光电二极管实现了非常低的暗电流，仅为400 pA/mm/sup 2/，平均增益=20 at /spl λ /=400 nm时的多余噪声F=7，以及良好的增益均匀性。
{"title":"Ultraviolet avalanche photodiode in CMOS technology","authors":"A. Pauchard, A. Rochas, Z. Randjelovic, P. Besse, R. Popovic","doi":"10.1109/IEDM.2000.904417","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904417","url":null,"abstract":"We present a simple method that allows the fabrication of ultraviolet-selective avalanche photodiodes in a standard CMOS technology. An efficient guard ring structure is created using the lateral diffusion of two n/sub well/ regions separated by a gap of 0.6 /spl mu/m. Our photodiodes achieve a very low dark current of only 400 pA/mm/sup 2/, an excess noise F=7 for a mean gain =20 at /spl lambda/=400 nm, and a good gain uniformity.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121844792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904354
K. Imai, K. Yamaguchi, T. Kudo, N. Kimizuka, H. Onishi, A. Ono, Y. Nakahara, Y. Goto, K. Noda, S. Masuoka, S. Ito, K. Matsui, K. Ando, E. Hasegawa, T. Ohashi, N. Oda, K. Yokoyama, T. Takewaki, S. Sone, T. Horiuchi
This paper describes a 0.13-/spl mu/m-generation CMOS technology optimized for system-on-a-chip (SoC) applications. The wide-range of performances obtained using a triple gate oxide and multiple threshold voltage control allows the SoC to operate at high speed with low standby power. Core CMOS transistors, which have a 1.9 nm gate oxide and a 95-nm physical gate length, show an excellent drive current of 740/335 /spl mu/A//spl mu/m at 1.2 V. Low power CMOS transistors have a standby current of only 2-0.2 pA//spl mu/m with a 2.6-nm gate oxide and a 120-nm gate length. This technology has also been used to make a 1.4-/spl mu/m/sup 2/ loadless 4T SRAM cell as well as a 2.5-/spl mu/m/sup 2/ 6T cell. The wiring RC delay has been reduced by integrating Cu interconnects with a low-k "ladder-oxide" layer.
{"title":"CMOS device optimization for system-on-a-chip applications","authors":"K. Imai, K. Yamaguchi, T. Kudo, N. Kimizuka, H. Onishi, A. Ono, Y. Nakahara, Y. Goto, K. Noda, S. Masuoka, S. Ito, K. Matsui, K. Ando, E. Hasegawa, T. Ohashi, N. Oda, K. Yokoyama, T. Takewaki, S. Sone, T. Horiuchi","doi":"10.1109/IEDM.2000.904354","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904354","url":null,"abstract":"This paper describes a 0.13-/spl mu/m-generation CMOS technology optimized for system-on-a-chip (SoC) applications. The wide-range of performances obtained using a triple gate oxide and multiple threshold voltage control allows the SoC to operate at high speed with low standby power. Core CMOS transistors, which have a 1.9 nm gate oxide and a 95-nm physical gate length, show an excellent drive current of 740/335 /spl mu/A//spl mu/m at 1.2 V. Low power CMOS transistors have a standby current of only 2-0.2 pA//spl mu/m with a 2.6-nm gate oxide and a 120-nm gate length. This technology has also been used to make a 1.4-/spl mu/m/sup 2/ loadless 4T SRAM cell as well as a 2.5-/spl mu/m/sup 2/ 6T cell. The wiring RC delay has been reduced by integrating Cu interconnects with a low-k \"ladder-oxide\" layer.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122640733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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