Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008220
T. Park, Soon-Bok Lee
To give a proper and accurate estimation of the fatigue life of solder joints, a mechanical fatigue test method under mixed-mode loading is proposed. The loading phase is controlled by the angle of loading direction. Experiments are conducted with 63Sn/37Pb and Sn/3.5Ag/0.75Cu solder joints. The isothermal mechanical low cycle fatigue tests were performed under several loading phases. Constant displacement controlled tests are performed using a micromechanical test apparatus. Failure patterns of the fatigue tests are observed and discussed. Morrow energy model was examined and found to be a proper low cycle fatigue model for solder joints.
{"title":"Isothermal low cycle fatigue tests of Sn/3.5Ag/0.75Cu and 63Sn/37Pb solder joints under mixed-mode loading cases","authors":"T. Park, Soon-Bok Lee","doi":"10.1109/ECTC.2002.1008220","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008220","url":null,"abstract":"To give a proper and accurate estimation of the fatigue life of solder joints, a mechanical fatigue test method under mixed-mode loading is proposed. The loading phase is controlled by the angle of loading direction. Experiments are conducted with 63Sn/37Pb and Sn/3.5Ag/0.75Cu solder joints. The isothermal mechanical low cycle fatigue tests were performed under several loading phases. Constant displacement controlled tests are performed using a micromechanical test apparatus. Failure patterns of the fatigue tests are observed and discussed. Morrow energy model was examined and found to be a proper low cycle fatigue model for solder joints.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134318509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008083
S. Takami, M. Hori, M. Arikawa, T. Matsuoka, Y. Hiramatsu, Y. Iwata, Masaharu Hotehama, K. Hayashi
By applying 'simultaneous curing' substrates for core substrates, we developed an ultra high transmission speed build up substrate (called Super HDBU/spl reg/) which is applicable for flip chip packages with over 3,000 I/O. Most build up interconnected substrates have been using a PWB with plated through holes (PTH) as the core substrate. Considering the form density of interconnects and transmission speed, this core with PTH has become a barrier by dividing the top and bottom surface of the substrate. Also, design interconnection lines are limited to the top side of the build up substrate which mounts the LSI devices. As for the solution to these issues, we have developed a new process of simultaneous curing with a copper foil transfer method onto an uncured prepreg. The simultaneous curing substrate method makes it possible to design signal interconnection lines on build up layers on both the top and bottom surfaces of the core substrate. In addition, it provides much finer via and narrower via pitch design on the core substrate which enables full grid area design instead of peripheral design.
{"title":"A new high density organic laminate for high pin-count flip chip packages","authors":"S. Takami, M. Hori, M. Arikawa, T. Matsuoka, Y. Hiramatsu, Y. Iwata, Masaharu Hotehama, K. Hayashi","doi":"10.1109/ECTC.2002.1008083","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008083","url":null,"abstract":"By applying 'simultaneous curing' substrates for core substrates, we developed an ultra high transmission speed build up substrate (called Super HDBU/spl reg/) which is applicable for flip chip packages with over 3,000 I/O. Most build up interconnected substrates have been using a PWB with plated through holes (PTH) as the core substrate. Considering the form density of interconnects and transmission speed, this core with PTH has become a barrier by dividing the top and bottom surface of the substrate. Also, design interconnection lines are limited to the top side of the build up substrate which mounts the LSI devices. As for the solution to these issues, we have developed a new process of simultaneous curing with a copper foil transfer method onto an uncured prepreg. The simultaneous curing substrate method makes it possible to design signal interconnection lines on build up layers on both the top and bottom surfaces of the core substrate. In addition, it provides much finer via and narrower via pitch design on the core substrate which enables full grid area design instead of peripheral design.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127587737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008092
Hai Ding, R. E. Powell, C. R. Hanna, I. C. Ume
Microelectronic and photonic packaging are progressing toward integrating more devices with more functions into a smaller confined space, while requiring higher yield and superior reliability. New electronic components, materials, fabrication processes, and configurations are emerging to achieve these goals. As expected, surface flatness is playing a more crucial role in integrated circuits and integrated optics manufacturing. Out-of-plane displacement (warpage) is a global effect of interfacial stress and displacement. It is also the cause of mis-registration and non-contact between components and their substrates. Moire methods offer noncontact, full-field, high-resolution approaches for measuring warpage. In this paper, two types of moire methods are introduced and analyzed. They carry distinct features and grant more options to measure warpage under various scenarios. It has been shown through system analysis and experimental results that these systems are powerful tools for studying warpage mechanisms. Specifically, they can help to investigate the effects of materials, manufacturing processes, and packaging configurations on warpage.
{"title":"Warpage measurement comparison using shadow moire and projection moire methods","authors":"Hai Ding, R. E. Powell, C. R. Hanna, I. C. Ume","doi":"10.1109/ECTC.2002.1008092","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008092","url":null,"abstract":"Microelectronic and photonic packaging are progressing toward integrating more devices with more functions into a smaller confined space, while requiring higher yield and superior reliability. New electronic components, materials, fabrication processes, and configurations are emerging to achieve these goals. As expected, surface flatness is playing a more crucial role in integrated circuits and integrated optics manufacturing. Out-of-plane displacement (warpage) is a global effect of interfacial stress and displacement. It is also the cause of mis-registration and non-contact between components and their substrates. Moire methods offer noncontact, full-field, high-resolution approaches for measuring warpage. In this paper, two types of moire methods are introduced and analyzed. They carry distinct features and grant more options to measure warpage under various scenarios. It has been shown through system analysis and experimental results that these systems are powerful tools for studying warpage mechanisms. Specifically, they can help to investigate the effects of materials, manufacturing processes, and packaging configurations on warpage.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133059782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008307
M. Caggiano, K. M. Ho
The authors profile a course that is a Web-based enhancement of a new graduate. course entitled "Electronics Packaging" that was developed and introduced into the ECE Department at Rutgers University during the spring of 2001. This new course deals with the electrical characterization and modeling of the parasitics for integrated circuit packaging. The course is targeted to the electrical engineering graduate population of full-time students and industry part-time graduate students that have a background in circuit analysis. The authors discuss the status of the course and demonstrate a sample of the Web designed lectures related to the electrical parasitics of the package.
{"title":"Electronics packaging - a Web-based course for the IEEE community","authors":"M. Caggiano, K. M. Ho","doi":"10.1109/ECTC.2002.1008307","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008307","url":null,"abstract":"The authors profile a course that is a Web-based enhancement of a new graduate. course entitled \"Electronics Packaging\" that was developed and introduced into the ECE Department at Rutgers University during the spring of 2001. This new course deals with the electrical characterization and modeling of the parasitics for integrated circuit packaging. The course is targeted to the electrical engineering graduate population of full-time students and industry part-time graduate students that have a background in circuit analysis. The authors discuss the status of the course and demonstrate a sample of the Web designed lectures related to the electrical parasitics of the package.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124558458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008128
Zhuqing Zhang, C. Wong
No-flow underfill has been invented and practised in the industry for a few years. However, due to the interfering of silica fillers with solder joint formation, most no-flow underfills are not filled with silica fillers and hence have a high coefficient of thermal expansion (CTE), which is undesirable for high reliability. In a novel invention, a double-layer no-flow underfill is implemented to the flip-chip process and allows fillers to be incorporated into the no-flow underfill. The effects of bottom layer underfill thickness, bottom layer underfill viscosity, and reflow profile on the solder wetting properties are investigated in a design of experiment (DOE) using quartz chips. It is found that the thickness and viscosity of the bottom layer underfill are essential to the wetting of the solder bumps. CSP components are assembled using the double-layer no-flow underfill process. Silica fillers of different sizes and weight percentages are incorporated into the upper layer underfill. With high viscosity bottom layer underfill, up to 40 wt% fillers can be added into the upper layer underfill and do not interfere with solder joint formation.
{"title":"Double-layer no-flow underfill materials and process","authors":"Zhuqing Zhang, C. Wong","doi":"10.1109/ECTC.2002.1008128","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008128","url":null,"abstract":"No-flow underfill has been invented and practised in the industry for a few years. However, due to the interfering of silica fillers with solder joint formation, most no-flow underfills are not filled with silica fillers and hence have a high coefficient of thermal expansion (CTE), which is undesirable for high reliability. In a novel invention, a double-layer no-flow underfill is implemented to the flip-chip process and allows fillers to be incorporated into the no-flow underfill. The effects of bottom layer underfill thickness, bottom layer underfill viscosity, and reflow profile on the solder wetting properties are investigated in a design of experiment (DOE) using quartz chips. It is found that the thickness and viscosity of the bottom layer underfill are essential to the wetting of the solder bumps. CSP components are assembled using the double-layer no-flow underfill process. Silica fillers of different sizes and weight percentages are incorporated into the upper layer underfill. With high viscosity bottom layer underfill, up to 40 wt% fillers can be added into the upper layer underfill and do not interfere with solder joint formation.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116989050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008292
D. Andoh, Y. Tomita, T. Nakamura, F. Echigo
The next generation ALIVH substrates were developed named ALIVH G-type for the motherboard use and ALIVH-FB for semiconductor package use. The ALIVH G-type has lower moisture absorption and higher rigidity than the conventional ALIVH. The insulator material of conventional ALIVH is a non-woven aramid-epoxy prepreg. On the other hand, the ALIVH G-type uses glass-epoxy prepreg. We developed the resin flow control technology during the hot press lamination process for hindering the conductive particle in the via paste diffusion. We expect to realize the halogen free ALIVH and liberate the ALIVH from the moisture control, using the glass-epoxy prepreg. The ALIVH-FB has the same structure as the ALIVH. The design rule is minimised for the semiconductor package. The design rule of ALIVH-FB is Line/Space=25/25 /spl mu/m and Via Diameter/Land Diameter=50/150 /spl mu/m. The ALIVH-FB uses three new technologies of: (1) film insulator; (2) YAG THG laser drilling process; and (3) accurate alignment process. The ALIVH-FB is very suitable for semiconductor package use by the fine via on via structure and the properties of the film insulator.
{"title":"The progress of the ALIVH substrate","authors":"D. Andoh, Y. Tomita, T. Nakamura, F. Echigo","doi":"10.1109/ECTC.2002.1008292","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008292","url":null,"abstract":"The next generation ALIVH substrates were developed named ALIVH G-type for the motherboard use and ALIVH-FB for semiconductor package use. The ALIVH G-type has lower moisture absorption and higher rigidity than the conventional ALIVH. The insulator material of conventional ALIVH is a non-woven aramid-epoxy prepreg. On the other hand, the ALIVH G-type uses glass-epoxy prepreg. We developed the resin flow control technology during the hot press lamination process for hindering the conductive particle in the via paste diffusion. We expect to realize the halogen free ALIVH and liberate the ALIVH from the moisture control, using the glass-epoxy prepreg. The ALIVH-FB has the same structure as the ALIVH. The design rule is minimised for the semiconductor package. The design rule of ALIVH-FB is Line/Space=25/25 /spl mu/m and Via Diameter/Land Diameter=50/150 /spl mu/m. The ALIVH-FB uses three new technologies of: (1) film insulator; (2) YAG THG laser drilling process; and (3) accurate alignment process. The ALIVH-FB is very suitable for semiconductor package use by the fine via on via structure and the properties of the film insulator.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117303614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008255
Chul-Won Ju, S. Kim, Kyu-Ha Pack, H. Lee, Young-Chul Hyun, Seong-Su Park
This study investigated how the shapes of high density electroplated bump and reflowed bumps depend on via size. The solder bump was fabricated by subsequent processes as follows. After sputtering a Ti/Cu seed layer on a 5-inch Si-wafer, a thick photoresist for via formation was obtained by multi-coating, and vias with various diameters were defined by a conventional photolithography technique using a contact aligner with an I-line source. After via formation, eutectic solder bumps were electroplated. After reflow, the reflowed bump diameters at the bottom were unchanged compared with the electroplated diameters. The electroplated bump and reflowed bump shapes, however, depended significantly on the via size. The heights of the electroplated bumps and reflowed bumps increased with a larger via, while the aspect ratio of bumps decreased. To obtain high density bumps, the bump pitch was decreased so that the nearest bumps touched. The touching between the nearest bumps occurred during the over-plating procedure but not during the reflowing procedure because the mushroom diameter formed by over-plating was larger than the reflowed bump diameter. This study demonstrated that an arrangement in zig-zag rows is effective in realizing flip chip interconnect bumps with both a high density and high aspect ratio.
{"title":"The effect of via size on fine pitch and high density solder bumps for wafer level packaging","authors":"Chul-Won Ju, S. Kim, Kyu-Ha Pack, H. Lee, Young-Chul Hyun, Seong-Su Park","doi":"10.1109/ECTC.2002.1008255","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008255","url":null,"abstract":"This study investigated how the shapes of high density electroplated bump and reflowed bumps depend on via size. The solder bump was fabricated by subsequent processes as follows. After sputtering a Ti/Cu seed layer on a 5-inch Si-wafer, a thick photoresist for via formation was obtained by multi-coating, and vias with various diameters were defined by a conventional photolithography technique using a contact aligner with an I-line source. After via formation, eutectic solder bumps were electroplated. After reflow, the reflowed bump diameters at the bottom were unchanged compared with the electroplated diameters. The electroplated bump and reflowed bump shapes, however, depended significantly on the via size. The heights of the electroplated bumps and reflowed bumps increased with a larger via, while the aspect ratio of bumps decreased. To obtain high density bumps, the bump pitch was decreased so that the nearest bumps touched. The touching between the nearest bumps occurred during the over-plating procedure but not during the reflowing procedure because the mushroom diameter formed by over-plating was larger than the reflowed bump diameter. This study demonstrated that an arrangement in zig-zag rows is effective in realizing flip chip interconnect bumps with both a high density and high aspect ratio.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123210022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008238
W. Kritzler, P. Bronecke, P. Kraft, G. Yan
Lockheed Martin Naval Electronics & Surveillance Systems - Surface Systems (LM NE&SS-SS) developed a unique multichip module (MCM) packaging system designed to support low cost manufacturing of electronics for advanced defense and commercial applications. This technology, plastic chip-on-flex (PCOF), is based on the baseline high density interconnect (HDI) technology, invented by General Electric Aerospace (now Lockheed Martin) and perfected as a result of on-going collaboration between Lockheed Martin (LM) and GE. The Lockheed Martin PCOF technology is a key element in reducing costs of microelectronic modules. The HDI interconnect structure is rugged (no wirebonds) and can be designed with controlled impedance transmission lines for sensitive RF interconnections. HDI technology makes it possible to design and manufacture microelectronic modules which are smaller, lighter weight, highly integrated, highly reliable, with predictable/reproducible electrical performance. This paper emphasises several novel aspects of the technology. Benefits include reduced manufacturing cost, increased reliability, and reduced module size and weight.
{"title":"A low cost COTS-based microwave packaging methodology","authors":"W. Kritzler, P. Bronecke, P. Kraft, G. Yan","doi":"10.1109/ECTC.2002.1008238","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008238","url":null,"abstract":"Lockheed Martin Naval Electronics & Surveillance Systems - Surface Systems (LM NE&SS-SS) developed a unique multichip module (MCM) packaging system designed to support low cost manufacturing of electronics for advanced defense and commercial applications. This technology, plastic chip-on-flex (PCOF), is based on the baseline high density interconnect (HDI) technology, invented by General Electric Aerospace (now Lockheed Martin) and perfected as a result of on-going collaboration between Lockheed Martin (LM) and GE. The Lockheed Martin PCOF technology is a key element in reducing costs of microelectronic modules. The HDI interconnect structure is rugged (no wirebonds) and can be designed with controlled impedance transmission lines for sensitive RF interconnections. HDI technology makes it possible to design and manufacture microelectronic modules which are smaller, lighter weight, highly integrated, highly reliable, with predictable/reproducible electrical performance. This paper emphasises several novel aspects of the technology. Benefits include reduced manufacturing cost, increased reliability, and reduced module size and weight.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123919312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008170
K. Brownlee, P. Raj, S. Bhattacharya, K. Shinotani, C. Wong, R. Tummala
Electronic devices increasingly rely on new materials with improved properties such as lower coefficient of thermal expansion (preferably close to silicon), higher modulus, lower permittivity and dielectric loss, lower moisture absorption better thermal conductivity, higher dimensional stability, and most importantly reduced warpage particularly after the build-up process. Liquid crystal polymers (LCPs) have led to increasing interest for the packaging community due to their superior thermal and electrical properties. The targeted applications areas for LCPs are RF packaging, due to their low loss and low dielectric constant over a wide frequency range (Fukutake and Inoue, 2002; Fukutake, 1998; Jayaraj et al, 1995; Lawrence, 2000; Jayaraj et al, 1996; Yue et al, 1999,), near hermitic plastic sealing due to superior moisture barrier properties (Jayaraj et al, 1997), flex circuits and microvia laminates for high density interconnection (Corbett et al, 2000; Yue and Chan, 1998). This paper is focused toward possible application of LCP as a dielectric material for lamination on PWB and other engineered organic substrates. Commercially available LCP samples were analyzed using a variety of thermal analysis techniques. Based on thermal properties such as coefficient of thermal expansion (CTE), thermal degradation temperature and modulus, samples were selected for applications as a dielectric material. It is expected that a low CTE dielectric such as LCP will further reduce the dielectric film stress even when the CTE of the chip is matched with that of the substrate.
电子器件越来越依赖于具有改进性能的新材料，如更低的热膨胀系数(最好接近硅)，更高的模量，更低的介电常数和介电损耗，更低的吸湿性，更好的导热性，更高的尺寸稳定性，最重要的是减少翘曲，特别是在积累过程之后。液晶聚合物(lcp)由于其优越的热学和电学性能而引起了包装界越来越多的兴趣。lpc的目标应用领域是射频封装，因为它们在宽频率范围内具有低损耗和低介电常数(Fukutake和Inoue, 2002;Fukutake, 1998;Jayaraj et al, 1995;劳伦斯,2000;Jayaraj et al, 1996;Yue等人，1999年)，由于优越的防潮性能而形成的近绝缘塑料密封(Jayaraj等人，1997年)，用于高密度互连的柔性电路和微孔层压板(Corbett等人，2000年);Yue and Chan, 1998)。本文的重点是LCP作为一种介电材料在压路板和其他工程有机衬底上的层压应用。市售LCP样品使用各种热分析技术进行分析。根据热膨胀系数(CTE)、热降解温度和模量等热性能，选择样品作为介电材料。可以预期，即使芯片的CTE与衬底的CTE相匹配，LCP等低CTE电介质也会进一步降低介电膜应力。
{"title":"Evaluation of liquid crystal polymers for high performance SOP application","authors":"K. Brownlee, P. Raj, S. Bhattacharya, K. Shinotani, C. Wong, R. Tummala","doi":"10.1109/ECTC.2002.1008170","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008170","url":null,"abstract":"Electronic devices increasingly rely on new materials with improved properties such as lower coefficient of thermal expansion (preferably close to silicon), higher modulus, lower permittivity and dielectric loss, lower moisture absorption better thermal conductivity, higher dimensional stability, and most importantly reduced warpage particularly after the build-up process. Liquid crystal polymers (LCPs) have led to increasing interest for the packaging community due to their superior thermal and electrical properties. The targeted applications areas for LCPs are RF packaging, due to their low loss and low dielectric constant over a wide frequency range (Fukutake and Inoue, 2002; Fukutake, 1998; Jayaraj et al, 1995; Lawrence, 2000; Jayaraj et al, 1996; Yue et al, 1999,), near hermitic plastic sealing due to superior moisture barrier properties (Jayaraj et al, 1997), flex circuits and microvia laminates for high density interconnection (Corbett et al, 2000; Yue and Chan, 1998). This paper is focused toward possible application of LCP as a dielectric material for lamination on PWB and other engineered organic substrates. Commercially available LCP samples were analyzed using a variety of thermal analysis techniques. Based on thermal properties such as coefficient of thermal expansion (CTE), thermal degradation temperature and modulus, samples were selected for applications as a dielectric material. It is expected that a low CTE dielectric such as LCP will further reduce the dielectric film stress even when the CTE of the chip is matched with that of the substrate.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127202656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008295
P. Lindner, V. Dragoi, T. Glinsner, C. Schaefer, R. Islam
Wafer level packaging and 3D interconnect technologies are driven by increasing device density and functionality as well as reduction of total packaging cost. Key enabling technologies for 3D interconnect are high precision alignment and bonding systems and thick resist processing. A unique processing equipment has been developed to meet high volume production requirements. This paper reviews advances in equipment processing capabilities and provides a guideline for new processing techniques available. Wafer to wafer alignment can be carried out in various ways. Traditionally aligned wafer bonding is a well-established technology in the MEMS industry. Special requirements for 3D interconnects are high accuracy, the use of single side processed wafers and 8 inch capability. A comparison of wafer alignment technologies is presented. Also, a novel face-to-face alignment method is described and analyzed in terms of alignment accuracy before and after bonding. Wafer bonding is carried out subsequent to the alignment step in a separate process module. A summary of different bonding methods is given. Intermediate layers that act as bonding agent can be spun on to the wafer. Such coating processes for wafer level packaging applications vary greatly from the requirements for VLSI processing. VLSI photoresist processes use thin layers to transfer small features with sub-micron tolerances. Wafer level bumping typically is performed with 5-150 /spl mu/m films, to transfer large (20-250 /spl mu/m) features, with tolerances approaching micron scale. HDI applications require thicker adhesive layers. The paper concludes with application examples with different intermediate layers such as BCB.
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