Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008269
c.t. Lim, Y. J. Low
One of the most common causes of failure for portable electronic products is from drop impact. Impact and shock to such products can cause significant functional and physical damage. They can cause external housing, internal electronic component or package-to-board interconnection failure. This paper examines the drop impact response of portable electronic products at different impact orientations and drop heights. A method whereby actual drop test using a cellular phone as an example is proposed. Of interest is the measurement of the level of shock experienced by the electronic components on the printed circuit board (PCB) during impact. A patent pending drop tester which allows drop impact of the cellular phone at any orientation and drop height is used. A high-speed video camera is also utilized to verify the impact orientation. The drop impact responses examined are the impact force and the strains and level of shock induced at the PCB. A better understanding of the shock induced at the electronic components and packages in the products can assist manufacturers not only in designing better components and electronic packages but also products which are more robust and reliable, to handle shock and impact loading.
{"title":"Investigating the drop impact of portable electronic products","authors":"c.t. Lim, Y. J. Low","doi":"10.1109/ECTC.2002.1008269","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008269","url":null,"abstract":"One of the most common causes of failure for portable electronic products is from drop impact. Impact and shock to such products can cause significant functional and physical damage. They can cause external housing, internal electronic component or package-to-board interconnection failure. This paper examines the drop impact response of portable electronic products at different impact orientations and drop heights. A method whereby actual drop test using a cellular phone as an example is proposed. Of interest is the measurement of the level of shock experienced by the electronic components on the printed circuit board (PCB) during impact. A patent pending drop tester which allows drop impact of the cellular phone at any orientation and drop height is used. A high-speed video camera is also utilized to verify the impact orientation. The drop impact responses examined are the impact force and the strains and level of shock induced at the PCB. A better understanding of the shock induced at the electronic components and packages in the products can assist manufacturers not only in designing better components and electronic packages but also products which are more robust and reliable, to handle shock and impact loading.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130073631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008102
L. Wu, Y. Wang, C. Hsiao
The stack-die package concept emerged 2/spl sim/3 years ago. The major product a stack-die package with flash and SRAM chips integrated together, used in cellular phones for the purpose of size and weight reduction. The basic requirement for these two dies in a stacked package is that the size difference must be large enough to allow a wire bonding process at the bottom die, if we still want to utilize the low cost, mature wire bonding technology in interconnections. However, this requirement will limit the application in trying to integrate two similar or same sized dies into a single stack-die package. One solution for this application is to utilize flip chip technology in the interconnection, to solve the die size difference requirement. One of the concerns for this package is the higher assembly cost due to flip chip interconnection. Therefore, a low cost, high reliability alternative package structure is created, it is named S2BGA (spacer stacked ball grid array). In this package, a silicon spacer is deposited between top and bottom dies to offer enough space for the wire bonding process. Since mature wire bonding technology is still utilized, a reliable and cost effective stack-die package is provided but maintains the same package size.
{"title":"Innovative stack-die package - S2BGA","authors":"L. Wu, Y. Wang, C. Hsiao","doi":"10.1109/ECTC.2002.1008102","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008102","url":null,"abstract":"The stack-die package concept emerged 2/spl sim/3 years ago. The major product a stack-die package with flash and SRAM chips integrated together, used in cellular phones for the purpose of size and weight reduction. The basic requirement for these two dies in a stacked package is that the size difference must be large enough to allow a wire bonding process at the bottom die, if we still want to utilize the low cost, mature wire bonding technology in interconnections. However, this requirement will limit the application in trying to integrate two similar or same sized dies into a single stack-die package. One solution for this application is to utilize flip chip technology in the interconnection, to solve the die size difference requirement. One of the concerns for this package is the higher assembly cost due to flip chip interconnection. Therefore, a low cost, high reliability alternative package structure is created, it is named S2BGA (spacer stacked ball grid array). In this package, a silicon spacer is deposited between top and bottom dies to offer enough space for the wire bonding process. Since mature wire bonding technology is still utilized, a reliable and cost effective stack-die package is provided but maintains the same package size.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132055160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008225
Jongsoo Lee, Young-Min Lee, Choong-Mo Nam, I. Jeong, Dong-Wook Kim, Y. Kwon
An RF receiver module including a SAW filter in a package has been developed for providing a system in a package (SIP) solution. The most significant feature for the receiver module is that the RF SAW (surface acoustic wave) filter is integrated within the package. A typical silicon substate with thick oxide on top (/spl sim/25 /spl mu/m) made it possible to implement the different technologies such as GaAs MMIC and SAW filter on a single substate. MCM-D technology using a silicon substrate in this paper shows the proper solution for a SIP. RF performance and basic circuit components such as inductors, capacitors, resistors and transmission lines are developed. To verify the application of a silicon substrate to a system, an RF receiver module having dual band/tri-mode functions (CDMA, AMPS, and PCS) is implemented on a silicon substrate. A low noise amplifier, RF SAW filter and mixer are integrated on a specialized silicon substrate and show 2.4/spl sim/3 dB NF and 27/spl sim/28 dB gain for PCS (1840/spl sim/1870 MHz) and CDMA (869/spl sim/894 MHz), respectively.
{"title":"System in a package solution for RF receiver with SAW filter integration","authors":"Jongsoo Lee, Young-Min Lee, Choong-Mo Nam, I. Jeong, Dong-Wook Kim, Y. Kwon","doi":"10.1109/ECTC.2002.1008225","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008225","url":null,"abstract":"An RF receiver module including a SAW filter in a package has been developed for providing a system in a package (SIP) solution. The most significant feature for the receiver module is that the RF SAW (surface acoustic wave) filter is integrated within the package. A typical silicon substate with thick oxide on top (/spl sim/25 /spl mu/m) made it possible to implement the different technologies such as GaAs MMIC and SAW filter on a single substate. MCM-D technology using a silicon substrate in this paper shows the proper solution for a SIP. RF performance and basic circuit components such as inductors, capacitors, resistors and transmission lines are developed. To verify the application of a silicon substrate to a system, an RF receiver module having dual band/tri-mode functions (CDMA, AMPS, and PCS) is implemented on a silicon substrate. A low noise amplifier, RF SAW filter and mixer are integrated on a specialized silicon substrate and show 2.4/spl sim/3 dB NF and 27/spl sim/28 dB gain for PCS (1840/spl sim/1870 MHz) and CDMA (869/spl sim/894 MHz), respectively.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130465992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008210
Y. Rao, C. Wong
Embedded capacitor technology can increase silicon packaging efficiency, improve electrical performance, and reduce electronic assembly cost compared with traditional discrete capacitor technology. Developing a suitable material that satisfies electrical, reliability and processing requirements is one of the major challenges of incorporating capacitors into a printed wiring board (PWB) for demanding wireless, RF portable telecommunication products. A novel epoxy-based composite with very ultra high dielectric constant (/spl epsiv//sub r//spl sim/1000) has been developed in this work. The previous record of /spl epsiv//sub r/=150 was only recently reported. To our best knowledge, this is the highest K value of the polymer-based composite ever reported. High dielectric constant is obtained by increasing the concentration of conductive filler close to but not exceed the percolation threshold within the polymer matrix. This novel ultra high K material also has low dielectric loss (<0.02), good adhesion and perfect multi-chip-module laminate (MCM-L) process compatibility. This novel composite is the perfect material candidate for the integral embedded capacitor applications for next generation electronic products.
{"title":"Ultra high dielectric constant epoxy silver composite for embedded capacitor application","authors":"Y. Rao, C. Wong","doi":"10.1109/ECTC.2002.1008210","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008210","url":null,"abstract":"Embedded capacitor technology can increase silicon packaging efficiency, improve electrical performance, and reduce electronic assembly cost compared with traditional discrete capacitor technology. Developing a suitable material that satisfies electrical, reliability and processing requirements is one of the major challenges of incorporating capacitors into a printed wiring board (PWB) for demanding wireless, RF portable telecommunication products. A novel epoxy-based composite with very ultra high dielectric constant (/spl epsiv//sub r//spl sim/1000) has been developed in this work. The previous record of /spl epsiv//sub r/=150 was only recently reported. To our best knowledge, this is the highest K value of the polymer-based composite ever reported. High dielectric constant is obtained by increasing the concentration of conductive filler close to but not exceed the percolation threshold within the polymer matrix. This novel ultra high K material also has low dielectric loss (<0.02), good adhesion and perfect multi-chip-module laminate (MCM-L) process compatibility. This novel composite is the perfect material candidate for the integral embedded capacitor applications for next generation electronic products.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126903555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008314
T. Y. Tee, H. Ng
A comprehensive and integrated package stress model is established for QFN (Quad Flat Non-lead) packages with consideration of the effects of moisture diffusion, heat transfer, thermo-mechanical stress, hygro-mechanical stress, and vapor pressure induced during reflow. The critical plastic materials, i.e. mold compound and die attach, are characterized for hygroswelling and moisture properties. The moisture absorption during preconditioning at JEDEC Level 1, and moisture desorption at various high temperatures are characterized. The vapor pressure modeling applies the micro-mechanics approach, the Representative Volume Element (RVE), with consideration of the micro-void effect. The vapor pressure can be calculated based on the local moisture concentration after preconditioning. Results show that the vapor pressure saturates much faster than the moisture diffusion, and a near uniform vapor pressure is reached in the package. The vapor pressure introduces additional strain of the same order as the thermal strain and hygro strain to the package. Vapor pressure-induced expansion is directly related to the vapor pressure distribution, rather than the moisture distribution.
{"title":"Whole field vapor pressure modeling of QFN during reflow with coupled hygro-mechanical and thermo-mechanical stresses","authors":"T. Y. Tee, H. Ng","doi":"10.1109/ECTC.2002.1008314","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008314","url":null,"abstract":"A comprehensive and integrated package stress model is established for QFN (Quad Flat Non-lead) packages with consideration of the effects of moisture diffusion, heat transfer, thermo-mechanical stress, hygro-mechanical stress, and vapor pressure induced during reflow. The critical plastic materials, i.e. mold compound and die attach, are characterized for hygroswelling and moisture properties. The moisture absorption during preconditioning at JEDEC Level 1, and moisture desorption at various high temperatures are characterized. The vapor pressure modeling applies the micro-mechanics approach, the Representative Volume Element (RVE), with consideration of the micro-void effect. The vapor pressure can be calculated based on the local moisture concentration after preconditioning. Results show that the vapor pressure saturates much faster than the moisture diffusion, and a near uniform vapor pressure is reached in the package. The vapor pressure introduces additional strain of the same order as the thermal strain and hygro strain to the package. Vapor pressure-induced expansion is directly related to the vapor pressure distribution, rather than the moisture distribution.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123307991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008127
C. Hatano, H. Takahashi, T. Ichida
Controlled collapse chip connection (C4) and Gold to gold interconnection (GGI) are the typical processes of the flip chip interconnection. In these processes, solder balls or gold bumps formed on the IC chip and the circuit on the interposer substrate are metallurgically connected with each other. Next the metal-metal connection is encapsulated with the underfill material. These flip chip surface mounting processes give excellent contact reliability. However, two separate steps are required at the underfilling process, such as "Encapsulation" and "Curing". Accordingly, it takes relatively longer process time and lower cost performance. On the contrary, "One-step compression attach process" is a simple surface mounting process with high cost performance. "One-step process" utilizes the thermal shrinkage of the connecting materials and no metallurgical connection is attained. Typical materials used for these processes are ACF (anisotropic conductive film), ACP (anisotropic conductive paste), NCP (non conductive paste) and NCF (non conductive film). Unfortunately, reliability of this process is not fully established yet. As no metallurgical connection exists, reliability of One-step process depends on binding force, generated by material's shrinkage. Therefore reliability of One-step process is considered to be inferior to the underfill encapsulation (Two-step) process, especially under the severe level reliability test condition. We investigated both processes and then developed "Modified one step compression attach process" for Chip On Film (COF) applications. This process achieved metallurgical connection, using non-flow underfill. This means, metal-metal interconnection, encapsulation and cure of the underfill are processed in a single step. This "Modified one step compression attach process" used "ESPANEX" as flexible printed circuit board (FPC). "ESPANEX" is adhesive-less Copper Clad Laminate material which has good heat resistance and dimensional stability. New grade of the non-flow underfill material, "ESAREX" is developed for this process. "ESAREX" has high adhesive strength and long pot life at room temperature. As combined of these two materials, interconnection between gold and tin, encapsulation and curing of non-flow underfill are processed in a single step. We achieved excellent reliability results in the thermal cycle, pressure cooker (PCT) and the high temperature and high humidity (HHT) tests, using "Modified one step compression attach process".
{"title":"Modified flip-chip attach process using high performance non-flow underfill paste","authors":"C. Hatano, H. Takahashi, T. Ichida","doi":"10.1109/ECTC.2002.1008127","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008127","url":null,"abstract":"Controlled collapse chip connection (C4) and Gold to gold interconnection (GGI) are the typical processes of the flip chip interconnection. In these processes, solder balls or gold bumps formed on the IC chip and the circuit on the interposer substrate are metallurgically connected with each other. Next the metal-metal connection is encapsulated with the underfill material. These flip chip surface mounting processes give excellent contact reliability. However, two separate steps are required at the underfilling process, such as \"Encapsulation\" and \"Curing\". Accordingly, it takes relatively longer process time and lower cost performance. On the contrary, \"One-step compression attach process\" is a simple surface mounting process with high cost performance. \"One-step process\" utilizes the thermal shrinkage of the connecting materials and no metallurgical connection is attained. Typical materials used for these processes are ACF (anisotropic conductive film), ACP (anisotropic conductive paste), NCP (non conductive paste) and NCF (non conductive film). Unfortunately, reliability of this process is not fully established yet. As no metallurgical connection exists, reliability of One-step process depends on binding force, generated by material's shrinkage. Therefore reliability of One-step process is considered to be inferior to the underfill encapsulation (Two-step) process, especially under the severe level reliability test condition. We investigated both processes and then developed \"Modified one step compression attach process\" for Chip On Film (COF) applications. This process achieved metallurgical connection, using non-flow underfill. This means, metal-metal interconnection, encapsulation and cure of the underfill are processed in a single step. This \"Modified one step compression attach process\" used \"ESPANEX\" as flexible printed circuit board (FPC). \"ESPANEX\" is adhesive-less Copper Clad Laminate material which has good heat resistance and dimensional stability. New grade of the non-flow underfill material, \"ESAREX\" is developed for this process. \"ESAREX\" has high adhesive strength and long pot life at room temperature. As combined of these two materials, interconnection between gold and tin, encapsulation and curing of non-flow underfill are processed in a single step. We achieved excellent reliability results in the thermal cycle, pressure cooker (PCT) and the high temperature and high humidity (HHT) tests, using \"Modified one step compression attach process\".","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123098858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008178
Fan Zhang, C. Chum, Ming Li
Effect of various amounts of Au on the interfacial reactions of SnPb and SnAgCu solders and Al/Ni(V)/Cu underbump metallurgy were investigated after high temperature storage and multiple reflows. During high temperature storage, the presence of Au varied the formation of intermetallic compounds at solder/UBM interfaces from a binary Cu/sub 6/Sn/sub 5/ phase to a ternary Cu-Sn-Au or quarternary Cu-Sn-Ni-Au phase. The phase transformation was a diffusion controlled process, which was influenced by Au amount, aging temperature and solder composition. The effectiveness of the diffusion barrier layer of UBM was also weakened, since Ni and Sri could diffuse and react through a ternary or quarternary phase. Up to 500 hours at 150/spl deg/C all samples showed a ductile failure inside solder under the ball shear test, which indicated a relatively good bonding between the solder and UBM. From these results it was concluded that detrimental effect of Au on the stability of Ni was not as significant as that of Ni/Au substrate metallization. Ni from substrate finish may also play an important role in the interfacial reaction between the solder and Al/Ni(V)/Cu UBM.
在高温贮存和多次回流后，研究了不同Au用量对SnPb和SnAgCu钎料界面反应和Al/Ni(V)/Cu碰撞下冶金的影响。在高温储存过程中，Au的存在改变了钎料/UBM界面金属间化合物的形成，从二元Cu/sub - 6/Sn/sub - 5/相转变为三元Cu-Sn-Au或四元Cu-Sn- ni -Au相。相变是一个扩散控制的过程，受Au用量、时效温度和焊料成分的影响。由于Ni和Sri可以通过三元或四相扩散和反应，UBM的扩散阻挡层的有效性也被削弱。在150/spl度/C下，在500小时的球剪试验中，所有样品的焊料内部都出现了延展性破坏，这表明焊料与UBM之间的结合相对较好。从这些结果可以看出，Au对Ni稳定性的不利影响不如Ni/Au基底金属化对Ni稳定性的不利影响显著。衬底表面的Ni也可能在钎料与Al/Ni(V)/Cu UBM之间的界面反应中起重要作用。
{"title":"Effect of Au on interfacial reactions of eutectic SnPb and SnAgCu solders with Al/Ni(V)/Cu thin film metallization","authors":"Fan Zhang, C. Chum, Ming Li","doi":"10.1109/ECTC.2002.1008178","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008178","url":null,"abstract":"Effect of various amounts of Au on the interfacial reactions of SnPb and SnAgCu solders and Al/Ni(V)/Cu underbump metallurgy were investigated after high temperature storage and multiple reflows. During high temperature storage, the presence of Au varied the formation of intermetallic compounds at solder/UBM interfaces from a binary Cu/sub 6/Sn/sub 5/ phase to a ternary Cu-Sn-Au or quarternary Cu-Sn-Ni-Au phase. The phase transformation was a diffusion controlled process, which was influenced by Au amount, aging temperature and solder composition. The effectiveness of the diffusion barrier layer of UBM was also weakened, since Ni and Sri could diffuse and react through a ternary or quarternary phase. Up to 500 hours at 150/spl deg/C all samples showed a ductile failure inside solder under the ball shear test, which indicated a relatively good bonding between the solder and UBM. From these results it was concluded that detrimental effect of Au on the stability of Ni was not as significant as that of Ni/Au substrate metallization. Ni from substrate finish may also play an important role in the interfacial reaction between the solder and Al/Ni(V)/Cu UBM.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116629744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008278
Y. Yano, T. Sugiyama, S. Ishihara, Y. Fukui, H. Juso, K. Miyata, Y. Sota, K. Fujita
In order to achieve the greater compactness, lightness, high- and multi-functionality required of mobile equipment and other electronic devices, we have developed 3D packaging technology which enables free stacking, at the package level, of ultra-thin CSP (which contain 2 or 1 LSI chip(s)). By stacking at the package level, there are no yield problems, and it is easy to perform independent electrical testing, so it is possible to achieve multi-level stacking while freely combining different kinds of LSI chips like memory or ASIC. By making chips and resin molding thinner, lowering wire loops and optimizing the package structure, we achieved higher package density: a single unit (2 chips) package height of 0.55 mmMax., 2 layers (4 chips) with a unit package height of 1.0 mmMax., and 3 layers (6 chips) with a unit package height of 1.5 mmMax. This technology makes it possible to offer ultra-compact systems-in-package (logic + memory) and high-capacity composite memories.
{"title":"Three-dimensional very thin stacked packaging technology for SiP","authors":"Y. Yano, T. Sugiyama, S. Ishihara, Y. Fukui, H. Juso, K. Miyata, Y. Sota, K. Fujita","doi":"10.1109/ECTC.2002.1008278","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008278","url":null,"abstract":"In order to achieve the greater compactness, lightness, high- and multi-functionality required of mobile equipment and other electronic devices, we have developed 3D packaging technology which enables free stacking, at the package level, of ultra-thin CSP (which contain 2 or 1 LSI chip(s)). By stacking at the package level, there are no yield problems, and it is easy to perform independent electrical testing, so it is possible to achieve multi-level stacking while freely combining different kinds of LSI chips like memory or ASIC. By making chips and resin molding thinner, lowering wire loops and optimizing the package structure, we achieved higher package density: a single unit (2 chips) package height of 0.55 mmMax., 2 layers (4 chips) with a unit package height of 1.0 mmMax., and 3 layers (6 chips) with a unit package height of 1.5 mmMax. This technology makes it possible to offer ultra-compact systems-in-package (logic + memory) and high-capacity composite memories.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116645548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008274
G. Ramakrishna, R. Pucha, S. Sitaraman
Microvias play a key role in high density wiring substrates. To theoretically predict the fatigue life of the microvias, accurate estimation of plastic strain evolution in microvias is critical. Due to the temperature-dependent material properties and high cyclic strains induced due to thermal excursions in electronic packaging interconnects and components, plasticity theories are extensively used to predict the low-cycle fatigue life. Experimental evidence indicates that plastic deformation in metals and polymers at small scales depends not only on the state variables of stress and strain, but also on their higher order gradients. As the diameter of the microvia reduces, the wall thickness correspondingly reduces and hence the minimum feature size reduces to the order of microns, where scale effects in plasticity are predominant. A plastic strain gradient-based computational algorithm is employed in this work to study the thermo-mechanical deformation of microvia structure. The thermo-mechanical reliability analysis demonstrates the influence of incorporating strain gradient effects in predicting the evolution of plastic deformation in microvia structures.
{"title":"Micro-scale plasticity effects in microvia reliability analysis","authors":"G. Ramakrishna, R. Pucha, S. Sitaraman","doi":"10.1109/ECTC.2002.1008274","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008274","url":null,"abstract":"Microvias play a key role in high density wiring substrates. To theoretically predict the fatigue life of the microvias, accurate estimation of plastic strain evolution in microvias is critical. Due to the temperature-dependent material properties and high cyclic strains induced due to thermal excursions in electronic packaging interconnects and components, plasticity theories are extensively used to predict the low-cycle fatigue life. Experimental evidence indicates that plastic deformation in metals and polymers at small scales depends not only on the state variables of stress and strain, but also on their higher order gradients. As the diameter of the microvia reduces, the wall thickness correspondingly reduces and hence the minimum feature size reduces to the order of microns, where scale effects in plasticity are predominant. A plastic strain gradient-based computational algorithm is employed in this work to study the thermo-mechanical deformation of microvia structure. The thermo-mechanical reliability analysis demonstrates the influence of incorporating strain gradient effects in predicting the evolution of plastic deformation in microvia structures.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123889294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008116
L. Smith, D. Hockanson, K. Kothari
An efficient and accurate transmission-line model for discrete MLC capacitors is developed. Hardware measurement techniques are used to obtain the circuit parameters for the model components. Low inductance measurement fixtures are required to observe and measure the transmission line parameters. The simulated impedance vs frequency results match closely with hardware measurements in the capacitance, resistance and inductance portions of the transfer impedance curve. The transmission-line model is well suited for CAD tools that are used to design power distribution systems.
{"title":"A transmission-line model for ceramic capacitors for CAD tools based on measured parameters","authors":"L. Smith, D. Hockanson, K. Kothari","doi":"10.1109/ECTC.2002.1008116","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008116","url":null,"abstract":"An efficient and accurate transmission-line model for discrete MLC capacitors is developed. Hardware measurement techniques are used to obtain the circuit parameters for the model components. Low inductance measurement fixtures are required to observe and measure the transmission line parameters. The simulated impedance vs frequency results match closely with hardware measurements in the capacitance, resistance and inductance portions of the transfer impedance curve. The transmission-line model is well suited for CAD tools that are used to design power distribution systems.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122652679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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