Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008155
M. Joodaki, T. Senyildiz, G. Kompa
Static heat transfer and thermal stress analysis for the new generation quasi-monolithic integration technology (QMIT) have been performed using a three-dimensional finite element simulator. To confirm the simulation results, white-light interferometry measurement along with a Peltier element and a Pt-temperature sensor have been used. It has been shown that thermal resistances of 11/spl deg/C/W and 8.5/spl deg/C/W are possible using 200 /spl mu/m electroplated gold heat-spreader and diamond-filled polyimide on the backside of the active device, respectively. This promises successful realization of the high frequency circuits containing power active devices using the novel QMIT. Simulation and measurement results demonstrate a great decrease of thermal stress in the new generation QMIT in comparison to the earlier concept which extremely improves life-time of the packaging. A remarkable agreement between calculated and measured results was found.
{"title":"Heat transfer and thermal stress analysis in the new generation quasi-monolithic integration technology (QMIT)","authors":"M. Joodaki, T. Senyildiz, G. Kompa","doi":"10.1109/ECTC.2002.1008155","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008155","url":null,"abstract":"Static heat transfer and thermal stress analysis for the new generation quasi-monolithic integration technology (QMIT) have been performed using a three-dimensional finite element simulator. To confirm the simulation results, white-light interferometry measurement along with a Peltier element and a Pt-temperature sensor have been used. It has been shown that thermal resistances of 11/spl deg/C/W and 8.5/spl deg/C/W are possible using 200 /spl mu/m electroplated gold heat-spreader and diamond-filled polyimide on the backside of the active device, respectively. This promises successful realization of the high frequency circuits containing power active devices using the novel QMIT. Simulation and measurement results demonstrate a great decrease of thermal stress in the new generation QMIT in comparison to the earlier concept which extremely improves life-time of the packaging. A remarkable agreement between calculated and measured results was found.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121672868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008328
S. Kang, D. Baldwin
A new analysis methodology to predict solder interconnect wetting is developed to reveal the causes of poor wetting during flip chip assembly and to provide solutions. The analysis methodology characterizes solder wetting as two different processes: the wetting dynamics of the solder contact line and the generation of the minimum energy surface of the molten solder. Surface Evolver is implemented to generate the surface shape of solder during wetting. Since there are no quantified dynamics models for solder materials, a solder wetting dynamics model is developed based on former wetting models proposed for other materials. The contact angle relaxation of spreading over time is measured in specially designed experimental setup for model development. As a result of experiment and model evaluation, a best wetting dynamics model is developed and the development of analysis methodology is completed. The study of reflow process parameter effects is ongoing.
{"title":"Prediction of solder interconnects wetting and experimental evaluation","authors":"S. Kang, D. Baldwin","doi":"10.1109/ECTC.2002.1008328","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008328","url":null,"abstract":"A new analysis methodology to predict solder interconnect wetting is developed to reveal the causes of poor wetting during flip chip assembly and to provide solutions. The analysis methodology characterizes solder wetting as two different processes: the wetting dynamics of the solder contact line and the generation of the minimum energy surface of the molten solder. Surface Evolver is implemented to generate the surface shape of solder during wetting. Since there are no quantified dynamics models for solder materials, a solder wetting dynamics model is developed based on former wetting models proposed for other materials. The contact angle relaxation of spreading over time is measured in specially designed experimental setup for model development. As a result of experiment and model evaluation, a best wetting dynamics model is developed and the development of analysis methodology is completed. The study of reflow process parameter effects is ongoing.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114751679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008240
S. Spiesshoefer, L. Schaper, K. Maner, E. Porter, F. Barlow, M. Glover, W. Marsh, G. Bates, M. Lucas
This paper addresses the result of research on Z-axis interconnects suitable for 3-D processor modules. We discuss the advantages and disadvantages for the intended system. One selected interconnection medium, which is manufactured by Shin-Etsu, is based on metal wires embedded in a matrix of polymeric material. The wires protrude from the surface of the polymer film. By compressing this material between substrates, contact is made between metallized gold pads on the substrates via the embedded wires. The Shin-Etsu connector allows connections among multiple substrates at 0.5-mm pitch without the need for precision connector alignment because it contains redundant wires at very fine pitch. The second interconnection method, which is manufactured by FormFactor, uses a wire bonder to create gold wires with spring-like geometries on an array of metallized pads, fabricated on a test socket or interposer. This paper describes the testing program to determine connector performance and reliability.
{"title":"Alternative Z-axis connector technologies for high-density 3-D packaging","authors":"S. Spiesshoefer, L. Schaper, K. Maner, E. Porter, F. Barlow, M. Glover, W. Marsh, G. Bates, M. Lucas","doi":"10.1109/ECTC.2002.1008240","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008240","url":null,"abstract":"This paper addresses the result of research on Z-axis interconnects suitable for 3-D processor modules. We discuss the advantages and disadvantages for the intended system. One selected interconnection medium, which is manufactured by Shin-Etsu, is based on metal wires embedded in a matrix of polymeric material. The wires protrude from the surface of the polymer film. By compressing this material between substrates, contact is made between metallized gold pads on the substrates via the embedded wires. The Shin-Etsu connector allows connections among multiple substrates at 0.5-mm pitch without the need for precision connector alignment because it contains redundant wires at very fine pitch. The second interconnection method, which is manufactured by FormFactor, uses a wire bonder to create gold wires with spring-like geometries on an array of metallized pads, fabricated on a test socket or interposer. This paper describes the testing program to determine connector performance and reliability.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126319948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008199
M. Modi, S. Sitaraman
Delamination of intrinsically stressed films is commonly encountered in microelectronic systems. Thin films deposited through physical vapor deposition processes typically accrue intrinsic stresses through the micro structural variations caused by deposition or through thermally induced stresses imposed during cool-down from deposition temperatures. These intrinsic stresses can have a peak magnitude upwards of I GPa. To help prevent delamination, Ti or Cr "adhesive" layers, with microscale or nanoscale thickness, are used to increase the adhesion between the thin film and substrate. This study applies the Finite Element Method (FEM) to study the resistance to delamination of an innovative, stress-engineered, thin film interconnect. Adhesive layer parameters such as thickness, deposition-induced intrinsic stress, and material properties are examined. Fracture criteria (energy release rate and mode mixity) are used to quantify the effect of varying adhesive layer properties on interfacial fracture. The finite element study results are compared to a previously developed plate theory model, which does not account for the large deflection present in highly stressed film delamination. To determine whether a delamination will propagate, it is imperative that the interfacial fracture toughness be experimentally measured for the interface under study. Experimental measurement of interfacial fracture toughness and the associated mode mixity is currently a challenge for thin film interfaces. In addition to the numerical simulation, this paper discusses modifications to the decohesion test that yields a method that can tightly bound the interfacial fracture toughness using a single test wafer. Further it is a method that uses common IC fabrication techniques, can achieve low mode mixities easily and efficiently, and can be used with titanium interfaces. Results for Ti/Alumina interfacial fracture toughness are discussed and applied to the numerical study.
{"title":"Effect of adhesive layer properties on interfacial fracture in thin-film high-density interconnects","authors":"M. Modi, S. Sitaraman","doi":"10.1109/ECTC.2002.1008199","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008199","url":null,"abstract":"Delamination of intrinsically stressed films is commonly encountered in microelectronic systems. Thin films deposited through physical vapor deposition processes typically accrue intrinsic stresses through the micro structural variations caused by deposition or through thermally induced stresses imposed during cool-down from deposition temperatures. These intrinsic stresses can have a peak magnitude upwards of I GPa. To help prevent delamination, Ti or Cr \"adhesive\" layers, with microscale or nanoscale thickness, are used to increase the adhesion between the thin film and substrate. This study applies the Finite Element Method (FEM) to study the resistance to delamination of an innovative, stress-engineered, thin film interconnect. Adhesive layer parameters such as thickness, deposition-induced intrinsic stress, and material properties are examined. Fracture criteria (energy release rate and mode mixity) are used to quantify the effect of varying adhesive layer properties on interfacial fracture. The finite element study results are compared to a previously developed plate theory model, which does not account for the large deflection present in highly stressed film delamination. To determine whether a delamination will propagate, it is imperative that the interfacial fracture toughness be experimentally measured for the interface under study. Experimental measurement of interfacial fracture toughness and the associated mode mixity is currently a challenge for thin film interfaces. In addition to the numerical simulation, this paper discusses modifications to the decohesion test that yields a method that can tightly bound the interfacial fracture toughness using a single test wafer. Further it is a method that uses common IC fabrication techniques, can achieve low mode mixities easily and efficiently, and can be used with titanium interfaces. Results for Ti/Alumina interfacial fracture toughness are discussed and applied to the numerical study.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125639519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008218
Xingjia Huang, S. Lee, C. Yan
The present study is aimed at establishing the mechanics foundation of solder ball shear tests for evaluating the solder ball attachment strength of BGA packages. In particular, the emphasis is placed on understanding the progressive failure mechanism during the ball shear test. In this paper, an experimental investigation is presented. Specimens with BGA solder balls are fabricated and a series of ball shear tests is conducted. The shear ram is stopped at various stages during the ball shear test. The specimens are cross-sectioned for SEM inspection. The observed failure modes are characterized and correlated to the corresponding shear loading curves. The current experimental results can lead to a profound understanding in the failure mechanism of solder balls under mechanical shear loading. Furthermore, the outcome of the present study may provide a valuable database for the validation of computational modeling.
{"title":"Experimental investigation on the progressive failure mechanism of solder balls during ball shear test","authors":"Xingjia Huang, S. Lee, C. Yan","doi":"10.1109/ECTC.2002.1008218","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008218","url":null,"abstract":"The present study is aimed at establishing the mechanics foundation of solder ball shear tests for evaluating the solder ball attachment strength of BGA packages. In particular, the emphasis is placed on understanding the progressive failure mechanism during the ball shear test. In this paper, an experimental investigation is presented. Specimens with BGA solder balls are fabricated and a series of ball shear tests is conducted. The shear ram is stopped at various stages during the ball shear test. The specimens are cross-sectioned for SEM inspection. The observed failure modes are characterized and correlated to the corresponding shear loading curves. The current experimental results can lead to a profound understanding in the failure mechanism of solder balls under mechanical shear loading. Furthermore, the outcome of the present study may provide a valuable database for the validation of computational modeling.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125796550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008085
S. Akhlaghi, J. Broughton, D. Ivey
The eutectic gold-tin solder has been widely used in the optoelectronics/electronics industry. The prominent characteristics of this solder include high thermal fatigue resistance in addition to excellent thermal properties. An electroplating process was used in this study to deposit Au-30Sn (at%) solder on photoresist laminated substrates, based on previous successful attempts at depositing this alloy on unpatterned, metallized substrates. Difficulties were encountered in the course of electroplating photoresist patterned substrates. The problems were resolved by changing the chemistry of the electroplating solution through decreasing the gold:tin ratio. The problems arose because of penetration of the electroplating solution through pinholes in the photoresist, thus increasing the actual opening area for electroplating.
{"title":"Gold-tin solder electroplating of photo-resist laminated AlN ceramics","authors":"S. Akhlaghi, J. Broughton, D. Ivey","doi":"10.1109/ECTC.2002.1008085","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008085","url":null,"abstract":"The eutectic gold-tin solder has been widely used in the optoelectronics/electronics industry. The prominent characteristics of this solder include high thermal fatigue resistance in addition to excellent thermal properties. An electroplating process was used in this study to deposit Au-30Sn (at%) solder on photoresist laminated substrates, based on previous successful attempts at depositing this alloy on unpatterned, metallized substrates. Difficulties were encountered in the course of electroplating photoresist patterned substrates. The problems were resolved by changing the chemistry of the electroplating solution through decreasing the gold:tin ratio. The problems arose because of penetration of the electroplating solution through pinholes in the photoresist, thus increasing the actual opening area for electroplating.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132021578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008149
P. Berthier, D. Laffitte, J. Périnet, J. Goudard, X. Boddaert, P. Chazan
Qualification of opto-electronic devices is a mandatory but complex activity to perform in a fast changing technical environment and under a strong market pressure. In this paper, we analyze the advantages and drawbacks of the traditional qualification approach based on both end-development tests defined by international standards and statistical reliability calculations. We explain how we are adapting our qualification practices towards risk assessment methods and design for reliability process. Looking at the future trends or telecom opto-electronic devices, possible challenges that qualification activity will have to face are finally discussed.
{"title":"New qualification approaches for opto-electronic devices","authors":"P. Berthier, D. Laffitte, J. Périnet, J. Goudard, X. Boddaert, P. Chazan","doi":"10.1109/ECTC.2002.1008149","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008149","url":null,"abstract":"Qualification of opto-electronic devices is a mandatory but complex activity to perform in a fast changing technical environment and under a strong market pressure. In this paper, we analyze the advantages and drawbacks of the traditional qualification approach based on both end-development tests defined by international standards and statistical reliability calculations. We explain how we are adapting our qualification practices towards risk assessment methods and design for reliability process. Looking at the future trends or telecom opto-electronic devices, possible challenges that qualification activity will have to face are finally discussed.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132391917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008276
N. Iwamoto, L. Moro, B. Bedwell, P. Apen
Molecular modeling has previously been used to study adhesion and surface energy effects of die attach, underfill and viafill formulations, and is currently being used to study the mechanical property trends of the new class of ultra low k nanoporous dielectric materials, NANOGLASS/spl reg/ porous spin-on-glass (SOG) and GX3-P/sup TM/ porous organic, being developed within Honeywell. The need to understand material performance from a molecular level is especially understandable when considering the target application in IC fabrication. With such small microstructures, the impact of the molecular mechanical properties imparted by the molecular structure and architecture become more and more important. In addition, we are finding that by understanding the effects of the formulation on the mechanical properties from the molecular level, formulation changes can be planned directly targeted at specific properties. Although we are using many aspects of molecular modeling to help us understand SOG and organic dielectric properties such as density, wetting, solubility and adhesion, for this paper we have concentrated on reporting our observations on modulus. Our studies have found that we can correlate the experimental modulus of these materials very simply with a molecularly derived modulus.
{"title":"Understanding modulus trends in ultra low K dielectric materials through the use of molecular modeling","authors":"N. Iwamoto, L. Moro, B. Bedwell, P. Apen","doi":"10.1109/ECTC.2002.1008276","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008276","url":null,"abstract":"Molecular modeling has previously been used to study adhesion and surface energy effects of die attach, underfill and viafill formulations, and is currently being used to study the mechanical property trends of the new class of ultra low k nanoporous dielectric materials, NANOGLASS/spl reg/ porous spin-on-glass (SOG) and GX3-P/sup TM/ porous organic, being developed within Honeywell. The need to understand material performance from a molecular level is especially understandable when considering the target application in IC fabrication. With such small microstructures, the impact of the molecular mechanical properties imparted by the molecular structure and architecture become more and more important. In addition, we are finding that by understanding the effects of the formulation on the mechanical properties from the molecular level, formulation changes can be planned directly targeted at specific properties. Although we are using many aspects of molecular modeling to help us understand SOG and organic dielectric properties such as density, wetting, solubility and adhesion, for this paper we have concentrated on reporting our observations on modulus. Our studies have found that we can correlate the experimental modulus of these materials very simply with a molecularly derived modulus.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134058778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008122
D. Mccann, Su-Min Ha
Describes the performance of a low cost molded package using flip chip interconnections on a copper lead frame substrate. Two flip chip interconnect metallurgies were evaluated: High Pb bumps attached to the lead frame using eutectic Sn37Pb solder paste; Au bumps attached to the leadframe using eutectic Sn3.5Ag solder paste. This package format is identified as the flip chip MicroLeadframe (fcMLF) package family (QFN) in this presentation. Temperature cycle, HAST, storage, and MRT testing were performed. All reliability requirements were achieved. Level 1 260/spl deg/C J-STD-020A moisture classification was achieved. This fcMLF package was also evaluated with and without an exposed thermal pad. Electrical model simulations were completed showing the package was applicable for use up to 40 GHz, depending upon die to package size ratio. Thermal models were completed that demonstrated thermal dissipation of 35/spl deg/C/W theta JA for a 4.00 /spl times/ 4.00 mm body size with an exposed pad.
{"title":"Package characterization and development of a flip chip QFN package: fcMLF","authors":"D. Mccann, Su-Min Ha","doi":"10.1109/ECTC.2002.1008122","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008122","url":null,"abstract":"Describes the performance of a low cost molded package using flip chip interconnections on a copper lead frame substrate. Two flip chip interconnect metallurgies were evaluated: High Pb bumps attached to the lead frame using eutectic Sn37Pb solder paste; Au bumps attached to the leadframe using eutectic Sn3.5Ag solder paste. This package format is identified as the flip chip MicroLeadframe (fcMLF) package family (QFN) in this presentation. Temperature cycle, HAST, storage, and MRT testing were performed. All reliability requirements were achieved. Level 1 260/spl deg/C J-STD-020A moisture classification was achieved. This fcMLF package was also evaluated with and without an exposed thermal pad. Electrical model simulations were completed showing the package was applicable for use up to 40 GHz, depending upon die to package size ratio. Thermal models were completed that demonstrated thermal dissipation of 35/spl deg/C/W theta JA for a 4.00 /spl times/ 4.00 mm body size with an exposed pad.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134229129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008153
P.S. Whitney
AXSUN Technologies has developed technology for hybrid integration of photonic components and subsystems based on a set of platform enablers which allow for rapid prototyping of new concepts for product development, and rapid realization of a wide range of functions required for optical networking. A description of the key technologies comprising the "toolbox" will be given along with a discussion of the hybrid assembly processes and comparisons to competing technologies.
{"title":"Hybrid integration of photonic subsystems","authors":"P.S. Whitney","doi":"10.1109/ECTC.2002.1008153","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008153","url":null,"abstract":"AXSUN Technologies has developed technology for hybrid integration of photonic components and subsystems based on a set of platform enablers which allow for rapid prototyping of new concepts for product development, and rapid realization of a wide range of functions required for optical networking. A description of the key technologies comprising the \"toolbox\" will be given along with a discussion of the hybrid assembly processes and comparisons to competing technologies.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134232875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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