Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008233
D. Kam, Heeseok Lee, Seungyong Baek, Bongcheol Park, Joungho Kim
The concept of twisted pair on the cable interconnection can be readily applied to the differential lines on printed circuit board (PCB), which enables enhanced immunity against crosstalk and radiated emission. In this paper, twisted differential line (TDL) is implemented on PCB and fully characterized. First, the transmission characteristics of TDL including propagation constant and differential impedance are extracted by using 3D full-wave analysis. The potential of TDL for the transmission of over GHz signal and enhanced immunity against crosstalk and radiated emission is clearly shown. Second, the measurement results reconfirm TDL's capability as a good transmission line structure over several GHz. Also, it is modeled by a simple equivalent circuit, based on measurement results. Third, the enhanced immunity of TDL against crosstalk and radiated emission is clearly demonstrated by measurement results. TDL is compared with other transmission line structures showing its superiority. Finally, several ideas to improve TDL's performance are suggested and verified to be useful.
{"title":"GHz twisted differential line structure on printed circuit board to minimize EMI and crosstalk noises","authors":"D. Kam, Heeseok Lee, Seungyong Baek, Bongcheol Park, Joungho Kim","doi":"10.1109/ECTC.2002.1008233","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008233","url":null,"abstract":"The concept of twisted pair on the cable interconnection can be readily applied to the differential lines on printed circuit board (PCB), which enables enhanced immunity against crosstalk and radiated emission. In this paper, twisted differential line (TDL) is implemented on PCB and fully characterized. First, the transmission characteristics of TDL including propagation constant and differential impedance are extracted by using 3D full-wave analysis. The potential of TDL for the transmission of over GHz signal and enhanced immunity against crosstalk and radiated emission is clearly shown. Second, the measurement results reconfirm TDL's capability as a good transmission line structure over several GHz. Also, it is modeled by a simple equivalent circuit, based on measurement results. Third, the enhanced immunity of TDL against crosstalk and radiated emission is clearly demonstrated by measurement results. TDL is compared with other transmission line structures showing its superiority. Finally, several ideas to improve TDL's performance are suggested and verified to be useful.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131128804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008245
W. Kwon, K. Paik
In this paper the maximum current carrying capability of ACAs flip chip joint is investigated based on two failure mechanisms: (1) degradation of the interface between gold stud bumps and aluminum pads; and (2) ACA swelling between chips and substrates under high current stress. For the determination of the maximum allowable current, bias stressing was applied to ACAs flip chip joint. The current level at which current carrying capability is saturated is defined as the maximum allowable current. The degradation mechanism under high current stress was studied by in-situ monitoring of gold stud bump-aluminum pad ACA contact resistance and also ACA junction temperature at various current level. The cumulative failure distributions were used to predict the lifetime of ACAs flip chip joint under high current stressing. These experimental results can be used to better understand and to improve the current carrying capability of ACA flip chip joint.
{"title":"High current induced failure of ACAs flip chip joint","authors":"W. Kwon, K. Paik","doi":"10.1109/ECTC.2002.1008245","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008245","url":null,"abstract":"In this paper the maximum current carrying capability of ACAs flip chip joint is investigated based on two failure mechanisms: (1) degradation of the interface between gold stud bumps and aluminum pads; and (2) ACA swelling between chips and substrates under high current stress. For the determination of the maximum allowable current, bias stressing was applied to ACAs flip chip joint. The current level at which current carrying capability is saturated is defined as the maximum allowable current. The degradation mechanism under high current stress was studied by in-situ monitoring of gold stud bump-aluminum pad ACA contact resistance and also ACA junction temperature at various current level. The cumulative failure distributions were used to predict the lifetime of ACAs flip chip joint under high current stressing. These experimental results can be used to better understand and to improve the current carrying capability of ACA flip chip joint.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134447145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008184
Anh-Vu Pham
Major educational barriers exist in providing both quality and quantity of RF and electronic packaging engineers to meet industry needs. Although the National Science Foundation Microsystems Packaging Research Center has done excellent work in revolutionizing its education program with an outreach component, nation-wide students still have limited exposure to the field. For example, students at a nearby engineering institution, Clemson University (1.5-hour drive to Georgia Tech) do not have any courses in electronics packaging. This has been due to the lack of experts in the rapid growth of electronic technology. This is true in the RF electronics and MEMS that represent emerging technologies for developing the next-generation microsystems. Other barriers include the lack of departmental support for offering courses in electronics packaging, where the needs are to fulfil the core and traditional courses.
{"title":"Educational project: development of a seminar course on RF MEMS and RF microsystems","authors":"Anh-Vu Pham","doi":"10.1109/ECTC.2002.1008184","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008184","url":null,"abstract":"Major educational barriers exist in providing both quality and quantity of RF and electronic packaging engineers to meet industry needs. Although the National Science Foundation Microsystems Packaging Research Center has done excellent work in revolutionizing its education program with an outreach component, nation-wide students still have limited exposure to the field. For example, students at a nearby engineering institution, Clemson University (1.5-hour drive to Georgia Tech) do not have any courses in electronics packaging. This has been due to the lack of experts in the rapid growth of electronic technology. This is true in the RF electronics and MEMS that represent emerging technologies for developing the next-generation microsystems. Other barriers include the lack of departmental support for offering courses in electronics packaging, where the needs are to fulfil the core and traditional courses.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134643173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008091
C. Key Chung, R. Aspandiar, K. Foo Leong, Cheng Siew Tay
The solder interaction of Pb within the Sn/Ag/Cu system was characterized using Differential Scanning Calorimetry (DSC). Components were then assembled with the Pb-free solder. Cross-sectioning and fine polishing were performed on the solder joints at the as-soldered stage and after temperature cycle readouts at 250, 500, 750, and 1000 cycles. The microstructure of the solder joints was examined using Scanning Electron Microscopy (SEM), and solder elements were mapped and identified by Energy-Dispersive X-ray (EDX) analysis. DSC detected Pb reaction with Sn/Ag at 179/spl deg/C and ternary compound formation. SEM/EDX found that Pb diffused into the Sn/Ag/Cu matrix during reflow soldering to form different microstructures, namely CuSn, SnAg, SnPbAg, and Pb-rich phases. The SnAg structure was found as a rod/needle morphology that was detrimental to solder joint reliability. During temperature cycling, this structure loosened its embedding effects due to grain-boundary sliding in the solder matrix, which accelerated solder fatigue crack propagation. Solutions to this problem are discussed.
{"title":"The interactions of lead (Pb) in lead free solder (Sn/Ag/Cu) system","authors":"C. Key Chung, R. Aspandiar, K. Foo Leong, Cheng Siew Tay","doi":"10.1109/ECTC.2002.1008091","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008091","url":null,"abstract":"The solder interaction of Pb within the Sn/Ag/Cu system was characterized using Differential Scanning Calorimetry (DSC). Components were then assembled with the Pb-free solder. Cross-sectioning and fine polishing were performed on the solder joints at the as-soldered stage and after temperature cycle readouts at 250, 500, 750, and 1000 cycles. The microstructure of the solder joints was examined using Scanning Electron Microscopy (SEM), and solder elements were mapped and identified by Energy-Dispersive X-ray (EDX) analysis. DSC detected Pb reaction with Sn/Ag at 179/spl deg/C and ternary compound formation. SEM/EDX found that Pb diffused into the Sn/Ag/Cu matrix during reflow soldering to form different microstructures, namely CuSn, SnAg, SnPbAg, and Pb-rich phases. The SnAg structure was found as a rod/needle morphology that was detrimental to solder joint reliability. During temperature cycling, this structure loosened its embedding effects due to grain-boundary sliding in the solder matrix, which accelerated solder fatigue crack propagation. Solutions to this problem are discussed.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"06 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124469620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008145
G. Wang, F. Barlow, A. Elshabini
For embedded resistors in LTCC, the challenge is the high resistance tolerance, normally 20/spl sim/30%. This paper is aimed at modeling and reduction of the tolerance to meet the requirements for high frequency applications; less than 10% resistance tolerance. A mathematical equation for resistance tolerance was derived and experimentally validated. The predicted resistance tolerance agrees with the measured value. With the aid of this equation, resistance tolerance can be related to the tolerance of the print geometry, which is measurable and adjustable prior to firing. It is predicted that for the 10% resistance tolerance goal, print thickness tolerance must be no more than 8%. A comprehensive analysis and step-by-step strategy for tolerance reduction is presented in this work. Some experimental studies have been performed to determine the major factors affecting tolerance. Non-process related factors include resistor size (width and aspect ratio), number of resistor layers in the substrate, location of the resistors on a layer, and printer set-up. As for processing, if the printing is performed in a period of 7 to 17 minutes after paste is applied on the screen, consistent print geometry can be obtained. In addition, a 3-level and 5 factors design of experiments (DOE) shows that the printing parameters, except the low level of squeegee travel, have no significant effect on tolerance of print thickness and width. These results indicate that tolerance control must begin with the design, and include an optimized printer set-up for uniform print thickness across a large printed area. In addition, an appropriate printing process must be used to obtain high resolution rectangular resistors. Through these efforts, 6% to 10% thickness tolerance have been achieved for various print runs and process combinations. Further experiments are underway to evaluate tolerances from high volume production.
{"title":"Modeling and control of resistance tolerance for embedded resistors in LTCC","authors":"G. Wang, F. Barlow, A. Elshabini","doi":"10.1109/ECTC.2002.1008145","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008145","url":null,"abstract":"For embedded resistors in LTCC, the challenge is the high resistance tolerance, normally 20/spl sim/30%. This paper is aimed at modeling and reduction of the tolerance to meet the requirements for high frequency applications; less than 10% resistance tolerance. A mathematical equation for resistance tolerance was derived and experimentally validated. The predicted resistance tolerance agrees with the measured value. With the aid of this equation, resistance tolerance can be related to the tolerance of the print geometry, which is measurable and adjustable prior to firing. It is predicted that for the 10% resistance tolerance goal, print thickness tolerance must be no more than 8%. A comprehensive analysis and step-by-step strategy for tolerance reduction is presented in this work. Some experimental studies have been performed to determine the major factors affecting tolerance. Non-process related factors include resistor size (width and aspect ratio), number of resistor layers in the substrate, location of the resistors on a layer, and printer set-up. As for processing, if the printing is performed in a period of 7 to 17 minutes after paste is applied on the screen, consistent print geometry can be obtained. In addition, a 3-level and 5 factors design of experiments (DOE) shows that the printing parameters, except the low level of squeegee travel, have no significant effect on tolerance of print thickness and width. These results indicate that tolerance control must begin with the design, and include an optimized printer set-up for uniform print thickness across a large printed area. In addition, an appropriate printing process must be used to obtain high resolution rectangular resistors. Through these efforts, 6% to 10% thickness tolerance have been achieved for various print runs and process combinations. Further experiments are underway to evaluate tolerances from high volume production.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125479308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008319
T.Y. Lin, K. Davison, W. Leong, S. Chua, J. S. Pan, J. Chai, K. Toh, W. C. Tjiu
The copper migration on the silver plated surface of the lead-frames with various heat treatments was evaluated by X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM) and atomic force microscopy (AFM) methodologies. The copper migration may introduce copper oxidation and result in the wedge bonding failures due to the non-stick on lead (NSOL). The experiment was performed on the two kinds of TQFP leadframes with the stamped and etched manufacturing processes. XPS results showed that the etched leadframe was the relatively better one in that less copper oxide was detected on silver surface after annealing process. However, more copper was clearly observed to diffuse onto the silver surface after annealing process in the stamped leadframe. In comparison between the stamped and etched lead-frames, the silver plated layer in latter more efficiently blocks the copper diffusion - either surface or bulk diffusion. In addition, TEM and AFM provided the additional insight of the grain structure and surface roughness measurement of silver.
{"title":"The evaluation of copper migration during the die attach curing and second wire bonding process","authors":"T.Y. Lin, K. Davison, W. Leong, S. Chua, J. S. Pan, J. Chai, K. Toh, W. C. Tjiu","doi":"10.1109/ECTC.2002.1008319","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008319","url":null,"abstract":"The copper migration on the silver plated surface of the lead-frames with various heat treatments was evaluated by X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM) and atomic force microscopy (AFM) methodologies. The copper migration may introduce copper oxidation and result in the wedge bonding failures due to the non-stick on lead (NSOL). The experiment was performed on the two kinds of TQFP leadframes with the stamped and etched manufacturing processes. XPS results showed that the etched leadframe was the relatively better one in that less copper oxide was detected on silver surface after annealing process. However, more copper was clearly observed to diffuse onto the silver surface after annealing process in the stamped leadframe. In comparison between the stamped and etched lead-frames, the silver plated layer in latter more efficiently blocks the copper diffusion - either surface or bulk diffusion. In addition, TEM and AFM provided the additional insight of the grain structure and surface roughness measurement of silver.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131510767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008244
S. Fujiwara, M. Harada, Y. Fujita, T. Hachiya, M. Muramatsu
The flip-chip technique, in which a bare chip is directly connected to a substrate, has become a key technology in producing compact electronic products, including cellular phones. In particular, the technique of using Au bumps to connect the bare chip with the substrate, with the aid of an anisotropic conductive film (ACF), is one of the most useful technologies. The most serious problem with ACF bonding technology today is that the deterioration mechanism of interconnections is not clear. This study is motivated to clarify the mechanism of deterioration and to establish the method of obtaining reliability in the design of interconnections for which ACF is used.
{"title":"Deterioration mechanism of flip chip attachment using an anisotropic conductive film and design technology for high reliability","authors":"S. Fujiwara, M. Harada, Y. Fujita, T. Hachiya, M. Muramatsu","doi":"10.1109/ECTC.2002.1008244","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008244","url":null,"abstract":"The flip-chip technique, in which a bare chip is directly connected to a substrate, has become a key technology in producing compact electronic products, including cellular phones. In particular, the technique of using Au bumps to connect the bare chip with the substrate, with the aid of an anisotropic conductive film (ACF), is one of the most useful technologies. The most serious problem with ACF bonding technology today is that the deterioration mechanism of interconnections is not clear. This study is motivated to clarify the mechanism of deterioration and to establish the method of obtaining reliability in the design of interconnections for which ACF is used.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134160187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008197
H. Fan, P. Chung, M. Yuen, P. Chan
The propensity and significance of interfacial delamination as a crucial failure mechanism in electronic packaging have been well documented in many papers. Many of the failure criteria were used to solve 2-dimensional problem with a pre-crack. However, in real electronic packages, the size and location of the cracks or/and delamination cannot be predicted. It is not easy to use the traditional fracture criteria to deal with more complicated 3-D delamination problems. The potential delamination interface of copper leadframe/Epoxy Molding Compound (EMC) was selected in the study. The stresses of the interface were evaluated by the Button Shear Test. A series of Button Shear Tests was conducted to evaluate the adhesion properties of Epoxy Molding Compounds (EMCs) on copper substrate. In each of the tests, the critical load acting on the EMC of the button shear sample was measured at different shear angles and a finite element model was used to evaluate the stresses at the interface between the mold compound and the copper substrate. In this paper, an energy-based method is proposed by deriving the energy to initiate each of the tensile and shear modes of failure across the interfaces of the button shear test samples for the chosen EMC/leadframe material system. Component stresses were extracted from the numerical simulation in order to compute the distortional strain energy density, (U/sub d/), and the hydrostatic strain energy density, (U/sub h/), relating respectively to the shear and tensile mode. (U/sub d/) and (U/sub h/) were calculated from the Young's modulus of EMC and the average stresses within a selected region of the finite element model where it exhibits high stress values.
{"title":"An energy-based method to predict delamination in electronic packaging","authors":"H. Fan, P. Chung, M. Yuen, P. Chan","doi":"10.1109/ECTC.2002.1008197","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008197","url":null,"abstract":"The propensity and significance of interfacial delamination as a crucial failure mechanism in electronic packaging have been well documented in many papers. Many of the failure criteria were used to solve 2-dimensional problem with a pre-crack. However, in real electronic packages, the size and location of the cracks or/and delamination cannot be predicted. It is not easy to use the traditional fracture criteria to deal with more complicated 3-D delamination problems. The potential delamination interface of copper leadframe/Epoxy Molding Compound (EMC) was selected in the study. The stresses of the interface were evaluated by the Button Shear Test. A series of Button Shear Tests was conducted to evaluate the adhesion properties of Epoxy Molding Compounds (EMCs) on copper substrate. In each of the tests, the critical load acting on the EMC of the button shear sample was measured at different shear angles and a finite element model was used to evaluate the stresses at the interface between the mold compound and the copper substrate. In this paper, an energy-based method is proposed by deriving the energy to initiate each of the tensile and shear modes of failure across the interfaces of the button shear test samples for the chosen EMC/leadframe material system. Component stresses were extracted from the numerical simulation in order to compute the distortional strain energy density, (U/sub d/), and the hydrostatic strain energy density, (U/sub h/), relating respectively to the shear and tensile mode. (U/sub d/) and (U/sub h/) were calculated from the Young's modulus of EMC and the average stresses within a selected region of the finite element model where it exhibits high stress values.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"442 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131955152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008345
Sidharth, R. Blish, D. Natekar
Solder joint fatigue failure is a common failure mechanism in semiconductor packages mounted on boards. The thermal expansion mismatch between the package and the board causes cyclic loading on the solder joints during temperature cycling. It is therefore important to model the solder joint shape and standoff height accurately to estimate the reliability of a solder joint assembly. This paper discusses details of solder shape prediction using the Surface Evolver tool and its validation with experimental data. A comparison with truncated sphere model is also provided. A strategy for importing Surface Evolver data into a finite element based reliability evaluation is outlined.
{"title":"Solder joint shape and standoff height prediction and integration with FEA-based methodology for reliability evaluation","authors":"Sidharth, R. Blish, D. Natekar","doi":"10.1109/ECTC.2002.1008345","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008345","url":null,"abstract":"Solder joint fatigue failure is a common failure mechanism in semiconductor packages mounted on boards. The thermal expansion mismatch between the package and the board causes cyclic loading on the solder joints during temperature cycling. It is therefore important to model the solder joint shape and standoff height accurately to estimate the reliability of a solder joint assembly. This paper discusses details of solder shape prediction using the Surface Evolver tool and its validation with experimental data. A comparison with truncated sphere model is also provided. A strategy for importing Surface Evolver data into a finite element based reliability evaluation is outlined.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132145507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008215
Renyi Wang, R. Kuder, B. Wu, G. Emmerson, G. Seeley
Lead frame micro-electronic packages are still the most widely used in the semiconductor industry. The surface properties of metal lead frames are involved in several important interfacial interactions within micro-electronic packages and hence have crucial impact on package integrity and reliability. In this work, detailed investigations were carried out to elucidate the chemical compositions of surface treatment solutions as well as the chemical and physical properties of lead frame surfaces. Results from /sup 1/H nuclear magnetic resonance (NMR), X-ray photoelectron spectroscopy (XPS), optical microscopy, and static secondary ion mass spectroscopy (SSIMS) are described. Adhesion testing data obtained from lead frames with different surface treatments, and with die attach adhesives of various chemistries, are reported. In addition, JEDEC reliability tests, using a new die attach adhesive, were performed on molded packages with different packaging material combinations and the results are reported.
{"title":"Understanding lead frame surface treatment and its impact on package reliability","authors":"Renyi Wang, R. Kuder, B. Wu, G. Emmerson, G. Seeley","doi":"10.1109/ECTC.2002.1008215","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008215","url":null,"abstract":"Lead frame micro-electronic packages are still the most widely used in the semiconductor industry. The surface properties of metal lead frames are involved in several important interfacial interactions within micro-electronic packages and hence have crucial impact on package integrity and reliability. In this work, detailed investigations were carried out to elucidate the chemical compositions of surface treatment solutions as well as the chemical and physical properties of lead frame surfaces. Results from /sup 1/H nuclear magnetic resonance (NMR), X-ray photoelectron spectroscopy (XPS), optical microscopy, and static secondary ion mass spectroscopy (SSIMS) are described. Adhesion testing data obtained from lead frames with different surface treatments, and with die attach adhesives of various chemistries, are reported. In addition, JEDEC reliability tests, using a new die attach adhesive, were performed on molded packages with different packaging material combinations and the results are reported.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121083752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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