Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008233
D. Kam, Heeseok Lee, Seungyong Baek, Bongcheol Park, Joungho Kim
The concept of twisted pair on the cable interconnection can be readily applied to the differential lines on printed circuit board (PCB), which enables enhanced immunity against crosstalk and radiated emission. In this paper, twisted differential line (TDL) is implemented on PCB and fully characterized. First, the transmission characteristics of TDL including propagation constant and differential impedance are extracted by using 3D full-wave analysis. The potential of TDL for the transmission of over GHz signal and enhanced immunity against crosstalk and radiated emission is clearly shown. Second, the measurement results reconfirm TDL's capability as a good transmission line structure over several GHz. Also, it is modeled by a simple equivalent circuit, based on measurement results. Third, the enhanced immunity of TDL against crosstalk and radiated emission is clearly demonstrated by measurement results. TDL is compared with other transmission line structures showing its superiority. Finally, several ideas to improve TDL's performance are suggested and verified to be useful.
{"title":"GHz twisted differential line structure on printed circuit board to minimize EMI and crosstalk noises","authors":"D. Kam, Heeseok Lee, Seungyong Baek, Bongcheol Park, Joungho Kim","doi":"10.1109/ECTC.2002.1008233","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008233","url":null,"abstract":"The concept of twisted pair on the cable interconnection can be readily applied to the differential lines on printed circuit board (PCB), which enables enhanced immunity against crosstalk and radiated emission. In this paper, twisted differential line (TDL) is implemented on PCB and fully characterized. First, the transmission characteristics of TDL including propagation constant and differential impedance are extracted by using 3D full-wave analysis. The potential of TDL for the transmission of over GHz signal and enhanced immunity against crosstalk and radiated emission is clearly shown. Second, the measurement results reconfirm TDL's capability as a good transmission line structure over several GHz. Also, it is modeled by a simple equivalent circuit, based on measurement results. Third, the enhanced immunity of TDL against crosstalk and radiated emission is clearly demonstrated by measurement results. TDL is compared with other transmission line structures showing its superiority. Finally, several ideas to improve TDL's performance are suggested and verified to be useful.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131128804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008245
W. Kwon, K. Paik
In this paper the maximum current carrying capability of ACAs flip chip joint is investigated based on two failure mechanisms: (1) degradation of the interface between gold stud bumps and aluminum pads; and (2) ACA swelling between chips and substrates under high current stress. For the determination of the maximum allowable current, bias stressing was applied to ACAs flip chip joint. The current level at which current carrying capability is saturated is defined as the maximum allowable current. The degradation mechanism under high current stress was studied by in-situ monitoring of gold stud bump-aluminum pad ACA contact resistance and also ACA junction temperature at various current level. The cumulative failure distributions were used to predict the lifetime of ACAs flip chip joint under high current stressing. These experimental results can be used to better understand and to improve the current carrying capability of ACA flip chip joint.
{"title":"High current induced failure of ACAs flip chip joint","authors":"W. Kwon, K. Paik","doi":"10.1109/ECTC.2002.1008245","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008245","url":null,"abstract":"In this paper the maximum current carrying capability of ACAs flip chip joint is investigated based on two failure mechanisms: (1) degradation of the interface between gold stud bumps and aluminum pads; and (2) ACA swelling between chips and substrates under high current stress. For the determination of the maximum allowable current, bias stressing was applied to ACAs flip chip joint. The current level at which current carrying capability is saturated is defined as the maximum allowable current. The degradation mechanism under high current stress was studied by in-situ monitoring of gold stud bump-aluminum pad ACA contact resistance and also ACA junction temperature at various current level. The cumulative failure distributions were used to predict the lifetime of ACAs flip chip joint under high current stressing. These experimental results can be used to better understand and to improve the current carrying capability of ACA flip chip joint.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134447145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008184
Anh-Vu Pham
Major educational barriers exist in providing both quality and quantity of RF and electronic packaging engineers to meet industry needs. Although the National Science Foundation Microsystems Packaging Research Center has done excellent work in revolutionizing its education program with an outreach component, nation-wide students still have limited exposure to the field. For example, students at a nearby engineering institution, Clemson University (1.5-hour drive to Georgia Tech) do not have any courses in electronics packaging. This has been due to the lack of experts in the rapid growth of electronic technology. This is true in the RF electronics and MEMS that represent emerging technologies for developing the next-generation microsystems. Other barriers include the lack of departmental support for offering courses in electronics packaging, where the needs are to fulfil the core and traditional courses.
{"title":"Educational project: development of a seminar course on RF MEMS and RF microsystems","authors":"Anh-Vu Pham","doi":"10.1109/ECTC.2002.1008184","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008184","url":null,"abstract":"Major educational barriers exist in providing both quality and quantity of RF and electronic packaging engineers to meet industry needs. Although the National Science Foundation Microsystems Packaging Research Center has done excellent work in revolutionizing its education program with an outreach component, nation-wide students still have limited exposure to the field. For example, students at a nearby engineering institution, Clemson University (1.5-hour drive to Georgia Tech) do not have any courses in electronics packaging. This has been due to the lack of experts in the rapid growth of electronic technology. This is true in the RF electronics and MEMS that represent emerging technologies for developing the next-generation microsystems. Other barriers include the lack of departmental support for offering courses in electronics packaging, where the needs are to fulfil the core and traditional courses.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134643173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008329
M. O. Alam, Y. Chan, K. Hung
Detailed microstructural studies were carried out to compare the reaction kinetics of Pb-Sn solder and Sn-Ag solder with electroless Ni-P layer for different reflow times. It was found that Sn-Ag solder reacts at a faster rate with the electroless Ni-P layer to form a Ni-Sn intermetallic compound (IMC) and hence a P-rich layer is formed quickly by expellation of the P from the reacting Ni-P layer. The Ni-Sn reaction at the interface of molten Sn-Ag solder with electroless Ni-P is so much quicker, resulting in the entrapment of some P in the Ni-Sn IMC. The initial P content in the electroless Ni-P layer is around 20 at%. However, as high as 38 at% P is detected in the dark Ni-P layer at the Sn-Ag solder interface. After 180 minutes reflow of the Sn-Ag solder joint, the Ni-P layer is found to disappear, leading to the full conversion of the 15 /spl mu/m Cu pad to Cu-Sn IMC. On the contrary, Ni-Sn IMC growth rate in the Pb-Sn solder interface is slower as well as more adherent. For 180 minutes reflow of the Pb-Sn solder interface, the electroless Ni-P layer is found to act as a diffusion barrier for Sri towards the Cu pad. Its implications for lead-free soldering are highlighted.
研究了不同回流时间下Pb-Sn焊料和Sn-Ag钎料与化学Ni-P层的反应动力学。结果表明，Sn-Ag焊料与化学镀Ni-P层反应速度更快，形成Ni-Sn金属间化合物(IMC)，从而使反应的Ni-P层中的P析出，快速形成富P层。熔态Sn-Ag钎料与化学镀Ni-P界面的Ni-Sn反应速度较快，导致Ni-Sn IMC中有部分P被包裹。化学镀Ni-P层的初始P含量约为20% at%。然而，在Sn-Ag钎料界面处的暗Ni-P层中检测到高达38 at% P。Sn-Ag焊点回流180分钟后，发现Ni-P层消失，导致15 /spl mu/m的Cu焊盘完全转化为Cu- sn IMC。相反，Ni-Sn IMC在Pb-Sn钎料界面的生长速度较慢，附着力更强。在Pb-Sn焊料界面回流180分钟后，发现化学镀Ni-P层充当了Sri向Cu焊盘扩散的屏障。强调了其对无铅焊接的影响。
{"title":"Reaction kinetics of Pb-Sn and Sn-Ag solder balls with electroless Ni-P/Cu pad during reflow soldering in microelectronic packaging","authors":"M. O. Alam, Y. Chan, K. Hung","doi":"10.1109/ECTC.2002.1008329","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008329","url":null,"abstract":"Detailed microstructural studies were carried out to compare the reaction kinetics of Pb-Sn solder and Sn-Ag solder with electroless Ni-P layer for different reflow times. It was found that Sn-Ag solder reacts at a faster rate with the electroless Ni-P layer to form a Ni-Sn intermetallic compound (IMC) and hence a P-rich layer is formed quickly by expellation of the P from the reacting Ni-P layer. The Ni-Sn reaction at the interface of molten Sn-Ag solder with electroless Ni-P is so much quicker, resulting in the entrapment of some P in the Ni-Sn IMC. The initial P content in the electroless Ni-P layer is around 20 at%. However, as high as 38 at% P is detected in the dark Ni-P layer at the Sn-Ag solder interface. After 180 minutes reflow of the Sn-Ag solder joint, the Ni-P layer is found to disappear, leading to the full conversion of the 15 /spl mu/m Cu pad to Cu-Sn IMC. On the contrary, Ni-Sn IMC growth rate in the Pb-Sn solder interface is slower as well as more adherent. For 180 minutes reflow of the Pb-Sn solder interface, the electroless Ni-P layer is found to act as a diffusion barrier for Sri towards the Cu pad. Its implications for lead-free soldering are highlighted.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114010773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008346
Bin Rao, Rong Zhang, F. Shi
In this work, the relative intensity noise (RIN) with relation to alignment parameters of a non-isolator packaging process is reported for the first time. We present the first detailed report on the dependence of the RIN of a fiber pigtailed laser diode on the process of pigtailing to a cleaved single mode fiber. The packaged device might have different RIN value due to the different alignment position where the reflection from the package is different. It is demonstrated that there is an optimal fiber-laser alignment position at which the value of RIN is at a minimum. It is thus important to consider the RIN optimization during fiber-laser alignment, in addition to seeking the maximum optical power coupled into the fiber. This work demonstrates that the RIN measurement is imperative when we prototype any non-isolator laser diode packaging.
{"title":"Alignment dependence of relative intensity noise in laser diode fiber pigtailing","authors":"Bin Rao, Rong Zhang, F. Shi","doi":"10.1109/ECTC.2002.1008346","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008346","url":null,"abstract":"In this work, the relative intensity noise (RIN) with relation to alignment parameters of a non-isolator packaging process is reported for the first time. We present the first detailed report on the dependence of the RIN of a fiber pigtailed laser diode on the process of pigtailing to a cleaved single mode fiber. The packaged device might have different RIN value due to the different alignment position where the reflection from the package is different. It is demonstrated that there is an optimal fiber-laser alignment position at which the value of RIN is at a minimum. It is thus important to consider the RIN optimization during fiber-laser alignment, in addition to seeking the maximum optical power coupled into the fiber. This work demonstrates that the RIN measurement is imperative when we prototype any non-isolator laser diode packaging.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115268246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008091
C. Key Chung, R. Aspandiar, K. Foo Leong, Cheng Siew Tay
The solder interaction of Pb within the Sn/Ag/Cu system was characterized using Differential Scanning Calorimetry (DSC). Components were then assembled with the Pb-free solder. Cross-sectioning and fine polishing were performed on the solder joints at the as-soldered stage and after temperature cycle readouts at 250, 500, 750, and 1000 cycles. The microstructure of the solder joints was examined using Scanning Electron Microscopy (SEM), and solder elements were mapped and identified by Energy-Dispersive X-ray (EDX) analysis. DSC detected Pb reaction with Sn/Ag at 179/spl deg/C and ternary compound formation. SEM/EDX found that Pb diffused into the Sn/Ag/Cu matrix during reflow soldering to form different microstructures, namely CuSn, SnAg, SnPbAg, and Pb-rich phases. The SnAg structure was found as a rod/needle morphology that was detrimental to solder joint reliability. During temperature cycling, this structure loosened its embedding effects due to grain-boundary sliding in the solder matrix, which accelerated solder fatigue crack propagation. Solutions to this problem are discussed.
{"title":"The interactions of lead (Pb) in lead free solder (Sn/Ag/Cu) system","authors":"C. Key Chung, R. Aspandiar, K. Foo Leong, Cheng Siew Tay","doi":"10.1109/ECTC.2002.1008091","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008091","url":null,"abstract":"The solder interaction of Pb within the Sn/Ag/Cu system was characterized using Differential Scanning Calorimetry (DSC). Components were then assembled with the Pb-free solder. Cross-sectioning and fine polishing were performed on the solder joints at the as-soldered stage and after temperature cycle readouts at 250, 500, 750, and 1000 cycles. The microstructure of the solder joints was examined using Scanning Electron Microscopy (SEM), and solder elements were mapped and identified by Energy-Dispersive X-ray (EDX) analysis. DSC detected Pb reaction with Sn/Ag at 179/spl deg/C and ternary compound formation. SEM/EDX found that Pb diffused into the Sn/Ag/Cu matrix during reflow soldering to form different microstructures, namely CuSn, SnAg, SnPbAg, and Pb-rich phases. The SnAg structure was found as a rod/needle morphology that was detrimental to solder joint reliability. During temperature cycling, this structure loosened its embedding effects due to grain-boundary sliding in the solder matrix, which accelerated solder fatigue crack propagation. Solutions to this problem are discussed.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124469620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008226
Seong-Ho Shin, I. Jeong, Ju-Hyun Ko, Myung-Gyu Kang, Su-Jin Lee, Y. Kwon
This paper introduces a new type of monolithic transmission line structure for high-density microwave and millimeter wave integrated circuits. An air-buried microstrip line (ABMSL) has been monolithically fabricated on glass substrates using a new multi-layer process. The ABMSL has the advantages of low insertion loss and high isolation between transmission lines compared to conventional planar transmission lines such as microstrip lines and coplanar waveguides (CPWs), because of its geometric structure that has air as a dielectric medium and ground conductor walls formed to surround the strip conductor. Over a high frequency range (from 5 GHz to 40 GHz), the ABMSL has very low insertion loss below 0.08 dB/mm. The isolation between two ABMSLs that have 2 mm coupling length and are separated by a 60 /spl mu/m distance is less than -43 dB.
{"title":"Monolithic implementation of air-buried microstrip lines for high-density microwave and millimeter wave ICs","authors":"Seong-Ho Shin, I. Jeong, Ju-Hyun Ko, Myung-Gyu Kang, Su-Jin Lee, Y. Kwon","doi":"10.1109/ECTC.2002.1008226","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008226","url":null,"abstract":"This paper introduces a new type of monolithic transmission line structure for high-density microwave and millimeter wave integrated circuits. An air-buried microstrip line (ABMSL) has been monolithically fabricated on glass substrates using a new multi-layer process. The ABMSL has the advantages of low insertion loss and high isolation between transmission lines compared to conventional planar transmission lines such as microstrip lines and coplanar waveguides (CPWs), because of its geometric structure that has air as a dielectric medium and ground conductor walls formed to surround the strip conductor. Over a high frequency range (from 5 GHz to 40 GHz), the ABMSL has very low insertion loss below 0.08 dB/mm. The isolation between two ABMSLs that have 2 mm coupling length and are separated by a 60 /spl mu/m distance is less than -43 dB.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123533139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008336
S. Law, L. Poladian
The demands of device design often result in devices with output optical parameters significantly different to standard single mode fibre. This results in an increase in coupling loss and a greater sensitivity to misalignment even when the fibre parameters are modified to match the device. In this paper we look at the effect of the optical parameters of a rectangular planar waveguide (height, width and refractive index difference) on the coupling loss and alignment tolerance for fibre attachment. It is shown that in the case of V-groove alignment of ribbon fibre (for example), where the height deviation of fibre cores can be significantly greater than the pitch deviation and there is a channel to channel variation in bond line thickness, this can lead to significant channel to channel variation in coupling loss.
{"title":"Effect of waveguide optical parameters on alignment tolerances for fibre attachment","authors":"S. Law, L. Poladian","doi":"10.1109/ECTC.2002.1008336","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008336","url":null,"abstract":"The demands of device design often result in devices with output optical parameters significantly different to standard single mode fibre. This results in an increase in coupling loss and a greater sensitivity to misalignment even when the fibre parameters are modified to match the device. In this paper we look at the effect of the optical parameters of a rectangular planar waveguide (height, width and refractive index difference) on the coupling loss and alignment tolerance for fibre attachment. It is shown that in the case of V-groove alignment of ribbon fibre (for example), where the height deviation of fibre cores can be significantly greater than the pitch deviation and there is a channel to channel variation in bond line thickness, this can lead to significant channel to channel variation in coupling loss.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123685806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008142
S. Dalmia, J. Hobbs, V. Sundaram, M. Swaminathan, Seock-Hee Lee, F. Ayazi, G. White, S. Bhattacharya
Integration of passive devices such as inductors and capacitors in packages or on silicon is an important step towards miniaturization and reduction of cost. These passive devices are used as stand-alone components or form an integral part of filters, oscillators, amplifiers, mixers and other RF circuits. This paper discusses the design of high Q inductors and high Q capacitors in organic substrates. Inductors with maximum quality factors in the range of 60-180 were obtained at frequencies in the 1-3 GHz band for inductances in the range of 1 nH-20 nH. This is the first demonstration of such high Q inductors in organic substrates processed using low-temperature (<200/spl deg/C) processes. The dimensions of all inductors are comparable to a low temperature co-fired ceramic (LTCC, <900/spl deg/C) and multichip module deposition (400/spl deg/C
{"title":"Design and optimization of high Q RF passives on SOP-based organic substrates","authors":"S. Dalmia, J. Hobbs, V. Sundaram, M. Swaminathan, Seock-Hee Lee, F. Ayazi, G. White, S. Bhattacharya","doi":"10.1109/ECTC.2002.1008142","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008142","url":null,"abstract":"Integration of passive devices such as inductors and capacitors in packages or on silicon is an important step towards miniaturization and reduction of cost. These passive devices are used as stand-alone components or form an integral part of filters, oscillators, amplifiers, mixers and other RF circuits. This paper discusses the design of high Q inductors and high Q capacitors in organic substrates. Inductors with maximum quality factors in the range of 60-180 were obtained at frequencies in the 1-3 GHz band for inductances in the range of 1 nH-20 nH. This is the first demonstration of such high Q inductors in organic substrates processed using low-temperature (<200/spl deg/C) processes. The dimensions of all inductors are comparable to a low temperature co-fired ceramic (LTCC, <900/spl deg/C) and multichip module deposition (400/spl deg/C<MCM-D<500/spl deg/C) technology process and well suited for integration in a variety of applications. The paper also discusses the performance of embedded capacitors in organic substrates. Although the Q factors for the capacitors in organic technologies are comparable to ceramic technologies, they do not compare well with the performance of inductors. The results for embedded capacitors show the need for lower loss materials compared to those currently used in low-temperature organic passive technology.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121795883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008103
M. Goetz
There are two competing technologies pursuing the 'holy grail' of complete system integration. Today, the most common method used to create the 'system' is to mount separately packaged ICs on a next-level substrate. Even with a low pin count, a package is typically several times larger than the IC, to accommodate the low wiring density on the PCB. High-performance systems, such as network processor systems, require high data bandwidth between key components and thus need an increased number of signal I/Os. Wide I/O busses switching at high speeds consequently require a larger number of power and ground pins to reduce switching noise. As a result, system performance is limited by increasing package size and the associated parasitic inductance and capacitance of the package and its connection on the PCB. System on chip (SoC) architecture attempts to integrate many functions, both analog and digital into a monolithic device. The successes are many, but so are the challenges. Many functions cannot be optimized due to the limitation of the semiconductor substrate used. Also, as defect density scales with area, the notion of integrating large scale functions (memory, switch fabrics) with small scale functions (rf devices) results in compounded yield impacts. System in Package (SiP) technology allows heterogeneous devices to be integrated into a small form factor. The integration technology includes embedded devices in the substrate and 3 dimensional chip-stacking approaches. By using a silicon based SiP, a copper/low K interconnect defined by lithographic processes on silicon offers very dense routing with high speed, low noise signal paths. The ICs used in the SiP can be designed to leverage the high density interconnect by optimizing both the core and the I/O of each device. Additionally, specialized devices can be designed specifically for the SiP architecture to take advantage of the high bandwidth and low latency features. Reducing chip-to-chip bus capacitance can dramatically decrease system power requirements and thermal dissipation. The lower bus power can be traded against higher bus frequency to improve performance at a fixed power level.
{"title":"System on chip design methodology applied to system in package architecture","authors":"M. Goetz","doi":"10.1109/ECTC.2002.1008103","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008103","url":null,"abstract":"There are two competing technologies pursuing the 'holy grail' of complete system integration. Today, the most common method used to create the 'system' is to mount separately packaged ICs on a next-level substrate. Even with a low pin count, a package is typically several times larger than the IC, to accommodate the low wiring density on the PCB. High-performance systems, such as network processor systems, require high data bandwidth between key components and thus need an increased number of signal I/Os. Wide I/O busses switching at high speeds consequently require a larger number of power and ground pins to reduce switching noise. As a result, system performance is limited by increasing package size and the associated parasitic inductance and capacitance of the package and its connection on the PCB. System on chip (SoC) architecture attempts to integrate many functions, both analog and digital into a monolithic device. The successes are many, but so are the challenges. Many functions cannot be optimized due to the limitation of the semiconductor substrate used. Also, as defect density scales with area, the notion of integrating large scale functions (memory, switch fabrics) with small scale functions (rf devices) results in compounded yield impacts. System in Package (SiP) technology allows heterogeneous devices to be integrated into a small form factor. The integration technology includes embedded devices in the substrate and 3 dimensional chip-stacking approaches. By using a silicon based SiP, a copper/low K interconnect defined by lithographic processes on silicon offers very dense routing with high speed, low noise signal paths. The ICs used in the SiP can be designed to leverage the high density interconnect by optimizing both the core and the I/O of each device. Additionally, specialized devices can be designed specifically for the SiP architecture to take advantage of the high bandwidth and low latency features. Reducing chip-to-chip bus capacitance can dramatically decrease system power requirements and thermal dissipation. The lower bus power can be traded against higher bus frequency to improve performance at a fixed power level.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124794862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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