Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008346
Bin Rao, Rong Zhang, F. Shi
In this work, the relative intensity noise (RIN) with relation to alignment parameters of a non-isolator packaging process is reported for the first time. We present the first detailed report on the dependence of the RIN of a fiber pigtailed laser diode on the process of pigtailing to a cleaved single mode fiber. The packaged device might have different RIN value due to the different alignment position where the reflection from the package is different. It is demonstrated that there is an optimal fiber-laser alignment position at which the value of RIN is at a minimum. It is thus important to consider the RIN optimization during fiber-laser alignment, in addition to seeking the maximum optical power coupled into the fiber. This work demonstrates that the RIN measurement is imperative when we prototype any non-isolator laser diode packaging.
{"title":"Alignment dependence of relative intensity noise in laser diode fiber pigtailing","authors":"Bin Rao, Rong Zhang, F. Shi","doi":"10.1109/ECTC.2002.1008346","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008346","url":null,"abstract":"In this work, the relative intensity noise (RIN) with relation to alignment parameters of a non-isolator packaging process is reported for the first time. We present the first detailed report on the dependence of the RIN of a fiber pigtailed laser diode on the process of pigtailing to a cleaved single mode fiber. The packaged device might have different RIN value due to the different alignment position where the reflection from the package is different. It is demonstrated that there is an optimal fiber-laser alignment position at which the value of RIN is at a minimum. It is thus important to consider the RIN optimization during fiber-laser alignment, in addition to seeking the maximum optical power coupled into the fiber. This work demonstrates that the RIN measurement is imperative when we prototype any non-isolator laser diode packaging.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115268246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008208
Qi Zhu, Lunyu Ma, S. Sitaraman
As the rapid advances in IC design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great advantages for next-generation packaging. A novel compliant off-chip interconnect, One-Turn Helix (OTH), is designed as an underfill-free interconnect. It has excellent compliance in all directions to compensate the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of OTH is similar to standard IC fabrication, and wafer-level packaging makes it cost effective. In this work, we study the effect of geometry parameters on mechanical and electrical performance of OTH. Thinner and narrower arcuate beam with larger radius and taller post are found to have better mechanical compliance. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of OTH. Response surface methodology and an optimization technique have been used to select the optimal OTH structure parameters.
{"title":"Design and optimization of a novel compliant off-chip interconnect One-Turn Helix","authors":"Qi Zhu, Lunyu Ma, S. Sitaraman","doi":"10.1109/ECTC.2002.1008208","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008208","url":null,"abstract":"As the rapid advances in IC design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great advantages for next-generation packaging. A novel compliant off-chip interconnect, One-Turn Helix (OTH), is designed as an underfill-free interconnect. It has excellent compliance in all directions to compensate the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of OTH is similar to standard IC fabrication, and wafer-level packaging makes it cost effective. In this work, we study the effect of geometry parameters on mechanical and electrical performance of OTH. Thinner and narrower arcuate beam with larger radius and taller post are found to have better mechanical compliance. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of OTH. Response surface methodology and an optimization technique have been used to select the optimal OTH structure parameters.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116354721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008289
A. Xiao, Q. Tong, J. Shah, P. Morganelli
A novel no-flow underfill material for advanced flip chip and CSP packaging has been successfully developed. This new material is based on a non-anhydride resin system and therefore it does not have the chemical sensitizing concern. Unlike the short pot life of most anhydride systems this new material exhibited excellent pot life. The viscosity of the material did not increase over 48 hours at room temperature. During the assembly process, the material demonstrated that it fluxed the solder bumps, formed a nice fillet, and was fully cured during a single reflow exposure. Production efficiency is therefore significantly increased. In addition, the assembled packages using this novel no-flow underfill material also achieved high interconnect yield. In this paper, we present the curing kinetics study and material properties of this novel no-flow material. The influence of fluxing agents on curing kinetics of this system is discussed. Material properties such as glass transition temperature (Tg), modulus, and viscosity were systematically characterized. Differential scanning calorimetry (DSC) dynamic-mechanical analysis (DMA), and rheometry were used for this study. In addition, promising assembly trial results, using small flip chips (PB8) and CSPs (TV46), are reported. Finally, the effects of the formulations and reflow profile on voiding and yield are also discussed.
{"title":"A novel no-flow flux underfill material for advanced flip chip packaging","authors":"A. Xiao, Q. Tong, J. Shah, P. Morganelli","doi":"10.1109/ECTC.2002.1008289","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008289","url":null,"abstract":"A novel no-flow underfill material for advanced flip chip and CSP packaging has been successfully developed. This new material is based on a non-anhydride resin system and therefore it does not have the chemical sensitizing concern. Unlike the short pot life of most anhydride systems this new material exhibited excellent pot life. The viscosity of the material did not increase over 48 hours at room temperature. During the assembly process, the material demonstrated that it fluxed the solder bumps, formed a nice fillet, and was fully cured during a single reflow exposure. Production efficiency is therefore significantly increased. In addition, the assembled packages using this novel no-flow underfill material also achieved high interconnect yield. In this paper, we present the curing kinetics study and material properties of this novel no-flow material. The influence of fluxing agents on curing kinetics of this system is discussed. Material properties such as glass transition temperature (Tg), modulus, and viscosity were systematically characterized. Differential scanning calorimetry (DSC) dynamic-mechanical analysis (DMA), and rheometry were used for this study. In addition, promising assembly trial results, using small flip chips (PB8) and CSPs (TV46), are reported. Finally, the effects of the formulations and reflow profile on voiding and yield are also discussed.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116696080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008226
Seong-Ho Shin, I. Jeong, Ju-Hyun Ko, Myung-Gyu Kang, Su-Jin Lee, Y. Kwon
This paper introduces a new type of monolithic transmission line structure for high-density microwave and millimeter wave integrated circuits. An air-buried microstrip line (ABMSL) has been monolithically fabricated on glass substrates using a new multi-layer process. The ABMSL has the advantages of low insertion loss and high isolation between transmission lines compared to conventional planar transmission lines such as microstrip lines and coplanar waveguides (CPWs), because of its geometric structure that has air as a dielectric medium and ground conductor walls formed to surround the strip conductor. Over a high frequency range (from 5 GHz to 40 GHz), the ABMSL has very low insertion loss below 0.08 dB/mm. The isolation between two ABMSLs that have 2 mm coupling length and are separated by a 60 /spl mu/m distance is less than -43 dB.
{"title":"Monolithic implementation of air-buried microstrip lines for high-density microwave and millimeter wave ICs","authors":"Seong-Ho Shin, I. Jeong, Ju-Hyun Ko, Myung-Gyu Kang, Su-Jin Lee, Y. Kwon","doi":"10.1109/ECTC.2002.1008226","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008226","url":null,"abstract":"This paper introduces a new type of monolithic transmission line structure for high-density microwave and millimeter wave integrated circuits. An air-buried microstrip line (ABMSL) has been monolithically fabricated on glass substrates using a new multi-layer process. The ABMSL has the advantages of low insertion loss and high isolation between transmission lines compared to conventional planar transmission lines such as microstrip lines and coplanar waveguides (CPWs), because of its geometric structure that has air as a dielectric medium and ground conductor walls formed to surround the strip conductor. Over a high frequency range (from 5 GHz to 40 GHz), the ABMSL has very low insertion loss below 0.08 dB/mm. The isolation between two ABMSLs that have 2 mm coupling length and are separated by a 60 /spl mu/m distance is less than -43 dB.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123533139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008336
S. Law, L. Poladian
The demands of device design often result in devices with output optical parameters significantly different to standard single mode fibre. This results in an increase in coupling loss and a greater sensitivity to misalignment even when the fibre parameters are modified to match the device. In this paper we look at the effect of the optical parameters of a rectangular planar waveguide (height, width and refractive index difference) on the coupling loss and alignment tolerance for fibre attachment. It is shown that in the case of V-groove alignment of ribbon fibre (for example), where the height deviation of fibre cores can be significantly greater than the pitch deviation and there is a channel to channel variation in bond line thickness, this can lead to significant channel to channel variation in coupling loss.
{"title":"Effect of waveguide optical parameters on alignment tolerances for fibre attachment","authors":"S. Law, L. Poladian","doi":"10.1109/ECTC.2002.1008336","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008336","url":null,"abstract":"The demands of device design often result in devices with output optical parameters significantly different to standard single mode fibre. This results in an increase in coupling loss and a greater sensitivity to misalignment even when the fibre parameters are modified to match the device. In this paper we look at the effect of the optical parameters of a rectangular planar waveguide (height, width and refractive index difference) on the coupling loss and alignment tolerance for fibre attachment. It is shown that in the case of V-groove alignment of ribbon fibre (for example), where the height deviation of fibre cores can be significantly greater than the pitch deviation and there is a channel to channel variation in bond line thickness, this can lead to significant channel to channel variation in coupling loss.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123685806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008142
S. Dalmia, J. Hobbs, V. Sundaram, M. Swaminathan, Seock-Hee Lee, F. Ayazi, G. White, S. Bhattacharya
Integration of passive devices such as inductors and capacitors in packages or on silicon is an important step towards miniaturization and reduction of cost. These passive devices are used as stand-alone components or form an integral part of filters, oscillators, amplifiers, mixers and other RF circuits. This paper discusses the design of high Q inductors and high Q capacitors in organic substrates. Inductors with maximum quality factors in the range of 60-180 were obtained at frequencies in the 1-3 GHz band for inductances in the range of 1 nH-20 nH. This is the first demonstration of such high Q inductors in organic substrates processed using low-temperature (<200/spl deg/C) processes. The dimensions of all inductors are comparable to a low temperature co-fired ceramic (LTCC, <900/spl deg/C) and multichip module deposition (400/spl deg/C
{"title":"Design and optimization of high Q RF passives on SOP-based organic substrates","authors":"S. Dalmia, J. Hobbs, V. Sundaram, M. Swaminathan, Seock-Hee Lee, F. Ayazi, G. White, S. Bhattacharya","doi":"10.1109/ECTC.2002.1008142","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008142","url":null,"abstract":"Integration of passive devices such as inductors and capacitors in packages or on silicon is an important step towards miniaturization and reduction of cost. These passive devices are used as stand-alone components or form an integral part of filters, oscillators, amplifiers, mixers and other RF circuits. This paper discusses the design of high Q inductors and high Q capacitors in organic substrates. Inductors with maximum quality factors in the range of 60-180 were obtained at frequencies in the 1-3 GHz band for inductances in the range of 1 nH-20 nH. This is the first demonstration of such high Q inductors in organic substrates processed using low-temperature (<200/spl deg/C) processes. The dimensions of all inductors are comparable to a low temperature co-fired ceramic (LTCC, <900/spl deg/C) and multichip module deposition (400/spl deg/C<MCM-D<500/spl deg/C) technology process and well suited for integration in a variety of applications. The paper also discusses the performance of embedded capacitors in organic substrates. Although the Q factors for the capacitors in organic technologies are comparable to ceramic technologies, they do not compare well with the performance of inductors. The results for embedded capacitors show the need for lower loss materials compared to those currently used in low-temperature organic passive technology.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"247 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121795883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008103
M. Goetz
There are two competing technologies pursuing the 'holy grail' of complete system integration. Today, the most common method used to create the 'system' is to mount separately packaged ICs on a next-level substrate. Even with a low pin count, a package is typically several times larger than the IC, to accommodate the low wiring density on the PCB. High-performance systems, such as network processor systems, require high data bandwidth between key components and thus need an increased number of signal I/Os. Wide I/O busses switching at high speeds consequently require a larger number of power and ground pins to reduce switching noise. As a result, system performance is limited by increasing package size and the associated parasitic inductance and capacitance of the package and its connection on the PCB. System on chip (SoC) architecture attempts to integrate many functions, both analog and digital into a monolithic device. The successes are many, but so are the challenges. Many functions cannot be optimized due to the limitation of the semiconductor substrate used. Also, as defect density scales with area, the notion of integrating large scale functions (memory, switch fabrics) with small scale functions (rf devices) results in compounded yield impacts. System in Package (SiP) technology allows heterogeneous devices to be integrated into a small form factor. The integration technology includes embedded devices in the substrate and 3 dimensional chip-stacking approaches. By using a silicon based SiP, a copper/low K interconnect defined by lithographic processes on silicon offers very dense routing with high speed, low noise signal paths. The ICs used in the SiP can be designed to leverage the high density interconnect by optimizing both the core and the I/O of each device. Additionally, specialized devices can be designed specifically for the SiP architecture to take advantage of the high bandwidth and low latency features. Reducing chip-to-chip bus capacitance can dramatically decrease system power requirements and thermal dissipation. The lower bus power can be traded against higher bus frequency to improve performance at a fixed power level.
{"title":"System on chip design methodology applied to system in package architecture","authors":"M. Goetz","doi":"10.1109/ECTC.2002.1008103","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008103","url":null,"abstract":"There are two competing technologies pursuing the 'holy grail' of complete system integration. Today, the most common method used to create the 'system' is to mount separately packaged ICs on a next-level substrate. Even with a low pin count, a package is typically several times larger than the IC, to accommodate the low wiring density on the PCB. High-performance systems, such as network processor systems, require high data bandwidth between key components and thus need an increased number of signal I/Os. Wide I/O busses switching at high speeds consequently require a larger number of power and ground pins to reduce switching noise. As a result, system performance is limited by increasing package size and the associated parasitic inductance and capacitance of the package and its connection on the PCB. System on chip (SoC) architecture attempts to integrate many functions, both analog and digital into a monolithic device. The successes are many, but so are the challenges. Many functions cannot be optimized due to the limitation of the semiconductor substrate used. Also, as defect density scales with area, the notion of integrating large scale functions (memory, switch fabrics) with small scale functions (rf devices) results in compounded yield impacts. System in Package (SiP) technology allows heterogeneous devices to be integrated into a small form factor. The integration technology includes embedded devices in the substrate and 3 dimensional chip-stacking approaches. By using a silicon based SiP, a copper/low K interconnect defined by lithographic processes on silicon offers very dense routing with high speed, low noise signal paths. The ICs used in the SiP can be designed to leverage the high density interconnect by optimizing both the core and the I/O of each device. Additionally, specialized devices can be designed specifically for the SiP architecture to take advantage of the high bandwidth and low latency features. Reducing chip-to-chip bus capacitance can dramatically decrease system power requirements and thermal dissipation. The lower bus power can be traded against higher bus frequency to improve performance at a fixed power level.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124794862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008231
W. Beyene
A new method is proposed for an efficient transient analysis of an interconnect-dominated system with a large number of linear, lumped and distributed elements and few nonlinear driver and termination networks. The method is based on partitioning the system into linear and nonlinear subnetworks and solving each subsystem iteratively using waveform relaxation technique. This allows a suitable and efficient simulation technique to be applied on each subnetwork. The linear network is analyzed using a reduced-order-modeling technique in the frequency domain and the time-domain waveforms are obtained using the inverse Laplace transform relation and reclusive convolution in the absence of the nonlinear networks. The method improves the simulation speed and accuracy because smaller nonlinear circuits are solved using conventional simulation methods. The technique and the validity of the method are discussed with an example using the Rambus memory channel.
{"title":"Efficient simulation of chip-to-chip interconnect system by combining waveform relaxation with reduced-order modeling methods","authors":"W. Beyene","doi":"10.1109/ECTC.2002.1008231","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008231","url":null,"abstract":"A new method is proposed for an efficient transient analysis of an interconnect-dominated system with a large number of linear, lumped and distributed elements and few nonlinear driver and termination networks. The method is based on partitioning the system into linear and nonlinear subnetworks and solving each subsystem iteratively using waveform relaxation technique. This allows a suitable and efficient simulation technique to be applied on each subnetwork. The linear network is analyzed using a reduced-order-modeling technique in the frequency domain and the time-domain waveforms are obtained using the inverse Laplace transform relation and reclusive convolution in the absence of the nonlinear networks. The method improves the simulation speed and accuracy because smaller nonlinear circuits are solved using conventional simulation methods. The technique and the validity of the method are discussed with an example using the Rambus memory channel.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125254457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008257
H.D. Thacker, M. Bakir, D. Keezer, K. Martin, J. Meindl
The ultra high I/O density sea of leads (SoL) chip-scale package (Bakir et al, Proc. 52nd Electron. and Comp. Tech. Conf., 2002) has the potential to revolutionize testability of a gigascale system-on-a-chip (SoC). With this wafer-level packaging technology, testing and burn-in can be migrated to the wafer-level. The parallel nature of wafer-level testing and burn-in, facilitated by SoL, can drive down the cost of obtaining a packaged known good die. The extremely high I/O density of the SoL package, typically 12,000 I/O/cm/sup 2/, provides access to internal nodes on a chip. Greater node access enables partitioning of the device-under-test (DUT) into smaller units while maintaining the ability to control and observe them. In turn, smaller units for testing equates to reduced test vector sets and shorter test times - a much sought after objective. A compliant probe technology has been developed to contact the SoL package. It provides a high-density, low-parasitic, and reliable interface between the package and automated test equipment (ATE) during testing. The compliant probes when used jointly with SoL offer a novel approach to efficiently testing a future SoC.
芯片级封装的超高I/O密度引线海(SoL) (Bakir et al, Proc. 52 Electron)。和Comp. Tech. Conf.， 2002)有可能彻底改变千兆级片上系统(SoC)的可测试性。利用这种晶圆级封装技术，测试和老化可以迁移到晶圆级。晶圆级测试和老化的并行性质，由SoL促进，可以降低获得封装好的已知好芯片的成本。SoL封装的极高I/O密度(通常为12,000 I/O/cm/sup 2/)提供了对芯片内部节点的访问。更大的节点访问可以将被测设备(DUT)划分为更小的单元，同时保持控制和观察它们的能力。反过来，更小的测试单元等同于减少的测试向量集和更短的测试时间——这是一个非常追求的目标。开发了一种兼容的探针技术来接触SoL包。在测试过程中，它在封装和自动测试设备(ATE)之间提供了高密度、低寄生和可靠的接口。当与SoL联合使用时，兼容探头提供了一种有效测试未来SoC的新方法。
{"title":"Compliant probe substrates for testing high pin-count chip scale packages","authors":"H.D. Thacker, M. Bakir, D. Keezer, K. Martin, J. Meindl","doi":"10.1109/ECTC.2002.1008257","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008257","url":null,"abstract":"The ultra high I/O density sea of leads (SoL) chip-scale package (Bakir et al, Proc. 52nd Electron. and Comp. Tech. Conf., 2002) has the potential to revolutionize testability of a gigascale system-on-a-chip (SoC). With this wafer-level packaging technology, testing and burn-in can be migrated to the wafer-level. The parallel nature of wafer-level testing and burn-in, facilitated by SoL, can drive down the cost of obtaining a packaged known good die. The extremely high I/O density of the SoL package, typically 12,000 I/O/cm/sup 2/, provides access to internal nodes on a chip. Greater node access enables partitioning of the device-under-test (DUT) into smaller units while maintaining the ability to control and observe them. In turn, smaller units for testing equates to reduced test vector sets and shorter test times - a much sought after objective. A compliant probe technology has been developed to contact the SoL package. It provides a high-density, low-parasitic, and reliable interface between the package and automated test equipment (ATE) during testing. The compliant probes when used jointly with SoL offer a novel approach to efficiently testing a future SoC.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130547915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008152
Y. Kishida, Y. Kuba, R. Komeda, Takehiro Okumichi, Katsuhide Setoguchi, T. Matsubara
In an effort to provide a breakthrough in next-generation fiber optic data links, we are proposing a concept in optics and electronics (OE) integrated surface mount packaging technology. It can provide more compact and easier assembly of optoelectronics packaging. One assembly issue of surface mount packaging is being able to secure high bit rate transmission lines from board level to optics mount level as well as optical connectivity on the board. In this paper, we describe how a flat lead type surface mount package utilizing RF vias, which has broadband characteristics and provides high performance, low distortion of the pulse waveform, and low jitter, from active devices. For a demonstration, we evaluated actual EO modules using 2 mm length RF vias, enabling a receptacle such as an SC type to be attached. Measurement results of electrical/optical eye diagram tests were very close to the theoretical expectations. Therefore, we believe that the technology is a positive solution to develop downsizing and mass-productivity of optoelectronics packaging.
{"title":"Development of OE integrated surface mount packaging","authors":"Y. Kishida, Y. Kuba, R. Komeda, Takehiro Okumichi, Katsuhide Setoguchi, T. Matsubara","doi":"10.1109/ECTC.2002.1008152","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008152","url":null,"abstract":"In an effort to provide a breakthrough in next-generation fiber optic data links, we are proposing a concept in optics and electronics (OE) integrated surface mount packaging technology. It can provide more compact and easier assembly of optoelectronics packaging. One assembly issue of surface mount packaging is being able to secure high bit rate transmission lines from board level to optics mount level as well as optical connectivity on the board. In this paper, we describe how a flat lead type surface mount package utilizing RF vias, which has broadband characteristics and provides high performance, low distortion of the pulse waveform, and low jitter, from active devices. For a demonstration, we evaluated actual EO modules using 2 mm length RF vias, enabling a receptacle such as an SC type to be attached. Measurement results of electrical/optical eye diagram tests were very close to the theoretical expectations. Therefore, we believe that the technology is a positive solution to develop downsizing and mass-productivity of optoelectronics packaging.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128158653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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