Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008257
H.D. Thacker, M. Bakir, D. Keezer, K. Martin, J. Meindl
The ultra high I/O density sea of leads (SoL) chip-scale package (Bakir et al, Proc. 52nd Electron. and Comp. Tech. Conf., 2002) has the potential to revolutionize testability of a gigascale system-on-a-chip (SoC). With this wafer-level packaging technology, testing and burn-in can be migrated to the wafer-level. The parallel nature of wafer-level testing and burn-in, facilitated by SoL, can drive down the cost of obtaining a packaged known good die. The extremely high I/O density of the SoL package, typically 12,000 I/O/cm/sup 2/, provides access to internal nodes on a chip. Greater node access enables partitioning of the device-under-test (DUT) into smaller units while maintaining the ability to control and observe them. In turn, smaller units for testing equates to reduced test vector sets and shorter test times - a much sought after objective. A compliant probe technology has been developed to contact the SoL package. It provides a high-density, low-parasitic, and reliable interface between the package and automated test equipment (ATE) during testing. The compliant probes when used jointly with SoL offer a novel approach to efficiently testing a future SoC.
芯片级封装的超高I/O密度引线海(SoL) (Bakir et al, Proc. 52 Electron)。和Comp. Tech. Conf.， 2002)有可能彻底改变千兆级片上系统(SoC)的可测试性。利用这种晶圆级封装技术，测试和老化可以迁移到晶圆级。晶圆级测试和老化的并行性质，由SoL促进，可以降低获得封装好的已知好芯片的成本。SoL封装的极高I/O密度(通常为12,000 I/O/cm/sup 2/)提供了对芯片内部节点的访问。更大的节点访问可以将被测设备(DUT)划分为更小的单元，同时保持控制和观察它们的能力。反过来，更小的测试单元等同于减少的测试向量集和更短的测试时间——这是一个非常追求的目标。开发了一种兼容的探针技术来接触SoL包。在测试过程中，它在封装和自动测试设备(ATE)之间提供了高密度、低寄生和可靠的接口。当与SoL联合使用时，兼容探头提供了一种有效测试未来SoC的新方法。
{"title":"Compliant probe substrates for testing high pin-count chip scale packages","authors":"H.D. Thacker, M. Bakir, D. Keezer, K. Martin, J. Meindl","doi":"10.1109/ECTC.2002.1008257","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008257","url":null,"abstract":"The ultra high I/O density sea of leads (SoL) chip-scale package (Bakir et al, Proc. 52nd Electron. and Comp. Tech. Conf., 2002) has the potential to revolutionize testability of a gigascale system-on-a-chip (SoC). With this wafer-level packaging technology, testing and burn-in can be migrated to the wafer-level. The parallel nature of wafer-level testing and burn-in, facilitated by SoL, can drive down the cost of obtaining a packaged known good die. The extremely high I/O density of the SoL package, typically 12,000 I/O/cm/sup 2/, provides access to internal nodes on a chip. Greater node access enables partitioning of the device-under-test (DUT) into smaller units while maintaining the ability to control and observe them. In turn, smaller units for testing equates to reduced test vector sets and shorter test times - a much sought after objective. A compliant probe technology has been developed to contact the SoL package. It provides a high-density, low-parasitic, and reliable interface between the package and automated test equipment (ATE) during testing. The compliant probes when used jointly with SoL offer a novel approach to efficiently testing a future SoC.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130547915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008305
Johan Liu, Liqiang Cao, Xitao Wang, J. Morris
The authors have developed a course on electrically conductive adhesives for Internet delivery from multiple sites. The paper lays out detailed lecture by lecture content, and details of the experimental sequences, which include both high end analytical techniques and experiments which would be adaptable to any basic undergraduate laboratory environment. Today the course is now installed in an Internet server for easy access. The course starts with a general introduction of conductive adhesive joining technology, followed by a section on ICA part. The course ends with the ACA part of the conductive adhesive technology. Both audio and video techniques are used to facilitate the study.
{"title":"Implementation of the Internet course on conductive adhesives for electronics packaging","authors":"Johan Liu, Liqiang Cao, Xitao Wang, J. Morris","doi":"10.1109/ECTC.2002.1008305","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008305","url":null,"abstract":"The authors have developed a course on electrically conductive adhesives for Internet delivery from multiple sites. The paper lays out detailed lecture by lecture content, and details of the experimental sequences, which include both high end analytical techniques and experiments which would be adaptable to any basic undergraduate laboratory environment. Today the course is now installed in an Internet server for easy access. The course starts with a general introduction of conductive adhesive joining technology, followed by a section on ICA part. The course ends with the ACA part of the conductive adhesive technology. Both audio and video techniques are used to facilitate the study.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122493894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008215
Renyi Wang, R. Kuder, B. Wu, G. Emmerson, G. Seeley
Lead frame micro-electronic packages are still the most widely used in the semiconductor industry. The surface properties of metal lead frames are involved in several important interfacial interactions within micro-electronic packages and hence have crucial impact on package integrity and reliability. In this work, detailed investigations were carried out to elucidate the chemical compositions of surface treatment solutions as well as the chemical and physical properties of lead frame surfaces. Results from /sup 1/H nuclear magnetic resonance (NMR), X-ray photoelectron spectroscopy (XPS), optical microscopy, and static secondary ion mass spectroscopy (SSIMS) are described. Adhesion testing data obtained from lead frames with different surface treatments, and with die attach adhesives of various chemistries, are reported. In addition, JEDEC reliability tests, using a new die attach adhesive, were performed on molded packages with different packaging material combinations and the results are reported.
{"title":"Understanding lead frame surface treatment and its impact on package reliability","authors":"Renyi Wang, R. Kuder, B. Wu, G. Emmerson, G. Seeley","doi":"10.1109/ECTC.2002.1008215","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008215","url":null,"abstract":"Lead frame micro-electronic packages are still the most widely used in the semiconductor industry. The surface properties of metal lead frames are involved in several important interfacial interactions within micro-electronic packages and hence have crucial impact on package integrity and reliability. In this work, detailed investigations were carried out to elucidate the chemical compositions of surface treatment solutions as well as the chemical and physical properties of lead frame surfaces. Results from /sup 1/H nuclear magnetic resonance (NMR), X-ray photoelectron spectroscopy (XPS), optical microscopy, and static secondary ion mass spectroscopy (SSIMS) are described. Adhesion testing data obtained from lead frames with different surface treatments, and with die attach adhesives of various chemistries, are reported. In addition, JEDEC reliability tests, using a new die attach adhesive, were performed on molded packages with different packaging material combinations and the results are reported.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121083752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008208
Qi Zhu, Lunyu Ma, S. Sitaraman
As the rapid advances in IC design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great advantages for next-generation packaging. A novel compliant off-chip interconnect, One-Turn Helix (OTH), is designed as an underfill-free interconnect. It has excellent compliance in all directions to compensate the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of OTH is similar to standard IC fabrication, and wafer-level packaging makes it cost effective. In this work, we study the effect of geometry parameters on mechanical and electrical performance of OTH. Thinner and narrower arcuate beam with larger radius and taller post are found to have better mechanical compliance. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of OTH. Response surface methodology and an optimization technique have been used to select the optimal OTH structure parameters.
{"title":"Design and optimization of a novel compliant off-chip interconnect One-Turn Helix","authors":"Qi Zhu, Lunyu Ma, S. Sitaraman","doi":"10.1109/ECTC.2002.1008208","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008208","url":null,"abstract":"As the rapid advances in IC design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great advantages for next-generation packaging. A novel compliant off-chip interconnect, One-Turn Helix (OTH), is designed as an underfill-free interconnect. It has excellent compliance in all directions to compensate the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of OTH is similar to standard IC fabrication, and wafer-level packaging makes it cost effective. In this work, we study the effect of geometry parameters on mechanical and electrical performance of OTH. Thinner and narrower arcuate beam with larger radius and taller post are found to have better mechanical compliance. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of OTH. Response surface methodology and an optimization technique have been used to select the optimal OTH structure parameters.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116354721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008231
W. Beyene
A new method is proposed for an efficient transient analysis of an interconnect-dominated system with a large number of linear, lumped and distributed elements and few nonlinear driver and termination networks. The method is based on partitioning the system into linear and nonlinear subnetworks and solving each subsystem iteratively using waveform relaxation technique. This allows a suitable and efficient simulation technique to be applied on each subnetwork. The linear network is analyzed using a reduced-order-modeling technique in the frequency domain and the time-domain waveforms are obtained using the inverse Laplace transform relation and reclusive convolution in the absence of the nonlinear networks. The method improves the simulation speed and accuracy because smaller nonlinear circuits are solved using conventional simulation methods. The technique and the validity of the method are discussed with an example using the Rambus memory channel.
{"title":"Efficient simulation of chip-to-chip interconnect system by combining waveform relaxation with reduced-order modeling methods","authors":"W. Beyene","doi":"10.1109/ECTC.2002.1008231","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008231","url":null,"abstract":"A new method is proposed for an efficient transient analysis of an interconnect-dominated system with a large number of linear, lumped and distributed elements and few nonlinear driver and termination networks. The method is based on partitioning the system into linear and nonlinear subnetworks and solving each subsystem iteratively using waveform relaxation technique. This allows a suitable and efficient simulation technique to be applied on each subnetwork. The linear network is analyzed using a reduced-order-modeling technique in the frequency domain and the time-domain waveforms are obtained using the inverse Laplace transform relation and reclusive convolution in the absence of the nonlinear networks. The method improves the simulation speed and accuracy because smaller nonlinear circuits are solved using conventional simulation methods. The technique and the validity of the method are discussed with an example using the Rambus memory channel.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125254457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008145
G. Wang, F. Barlow, A. Elshabini
For embedded resistors in LTCC, the challenge is the high resistance tolerance, normally 20/spl sim/30%. This paper is aimed at modeling and reduction of the tolerance to meet the requirements for high frequency applications; less than 10% resistance tolerance. A mathematical equation for resistance tolerance was derived and experimentally validated. The predicted resistance tolerance agrees with the measured value. With the aid of this equation, resistance tolerance can be related to the tolerance of the print geometry, which is measurable and adjustable prior to firing. It is predicted that for the 10% resistance tolerance goal, print thickness tolerance must be no more than 8%. A comprehensive analysis and step-by-step strategy for tolerance reduction is presented in this work. Some experimental studies have been performed to determine the major factors affecting tolerance. Non-process related factors include resistor size (width and aspect ratio), number of resistor layers in the substrate, location of the resistors on a layer, and printer set-up. As for processing, if the printing is performed in a period of 7 to 17 minutes after paste is applied on the screen, consistent print geometry can be obtained. In addition, a 3-level and 5 factors design of experiments (DOE) shows that the printing parameters, except the low level of squeegee travel, have no significant effect on tolerance of print thickness and width. These results indicate that tolerance control must begin with the design, and include an optimized printer set-up for uniform print thickness across a large printed area. In addition, an appropriate printing process must be used to obtain high resolution rectangular resistors. Through these efforts, 6% to 10% thickness tolerance have been achieved for various print runs and process combinations. Further experiments are underway to evaluate tolerances from high volume production.
{"title":"Modeling and control of resistance tolerance for embedded resistors in LTCC","authors":"G. Wang, F. Barlow, A. Elshabini","doi":"10.1109/ECTC.2002.1008145","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008145","url":null,"abstract":"For embedded resistors in LTCC, the challenge is the high resistance tolerance, normally 20/spl sim/30%. This paper is aimed at modeling and reduction of the tolerance to meet the requirements for high frequency applications; less than 10% resistance tolerance. A mathematical equation for resistance tolerance was derived and experimentally validated. The predicted resistance tolerance agrees with the measured value. With the aid of this equation, resistance tolerance can be related to the tolerance of the print geometry, which is measurable and adjustable prior to firing. It is predicted that for the 10% resistance tolerance goal, print thickness tolerance must be no more than 8%. A comprehensive analysis and step-by-step strategy for tolerance reduction is presented in this work. Some experimental studies have been performed to determine the major factors affecting tolerance. Non-process related factors include resistor size (width and aspect ratio), number of resistor layers in the substrate, location of the resistors on a layer, and printer set-up. As for processing, if the printing is performed in a period of 7 to 17 minutes after paste is applied on the screen, consistent print geometry can be obtained. In addition, a 3-level and 5 factors design of experiments (DOE) shows that the printing parameters, except the low level of squeegee travel, have no significant effect on tolerance of print thickness and width. These results indicate that tolerance control must begin with the design, and include an optimized printer set-up for uniform print thickness across a large printed area. In addition, an appropriate printing process must be used to obtain high resolution rectangular resistors. Through these efforts, 6% to 10% thickness tolerance have been achieved for various print runs and process combinations. Further experiments are underway to evaluate tolerances from high volume production.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125479308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008289
A. Xiao, Q. Tong, J. Shah, P. Morganelli
A novel no-flow underfill material for advanced flip chip and CSP packaging has been successfully developed. This new material is based on a non-anhydride resin system and therefore it does not have the chemical sensitizing concern. Unlike the short pot life of most anhydride systems this new material exhibited excellent pot life. The viscosity of the material did not increase over 48 hours at room temperature. During the assembly process, the material demonstrated that it fluxed the solder bumps, formed a nice fillet, and was fully cured during a single reflow exposure. Production efficiency is therefore significantly increased. In addition, the assembled packages using this novel no-flow underfill material also achieved high interconnect yield. In this paper, we present the curing kinetics study and material properties of this novel no-flow material. The influence of fluxing agents on curing kinetics of this system is discussed. Material properties such as glass transition temperature (Tg), modulus, and viscosity were systematically characterized. Differential scanning calorimetry (DSC) dynamic-mechanical analysis (DMA), and rheometry were used for this study. In addition, promising assembly trial results, using small flip chips (PB8) and CSPs (TV46), are reported. Finally, the effects of the formulations and reflow profile on voiding and yield are also discussed.
{"title":"A novel no-flow flux underfill material for advanced flip chip packaging","authors":"A. Xiao, Q. Tong, J. Shah, P. Morganelli","doi":"10.1109/ECTC.2002.1008289","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008289","url":null,"abstract":"A novel no-flow underfill material for advanced flip chip and CSP packaging has been successfully developed. This new material is based on a non-anhydride resin system and therefore it does not have the chemical sensitizing concern. Unlike the short pot life of most anhydride systems this new material exhibited excellent pot life. The viscosity of the material did not increase over 48 hours at room temperature. During the assembly process, the material demonstrated that it fluxed the solder bumps, formed a nice fillet, and was fully cured during a single reflow exposure. Production efficiency is therefore significantly increased. In addition, the assembled packages using this novel no-flow underfill material also achieved high interconnect yield. In this paper, we present the curing kinetics study and material properties of this novel no-flow material. The influence of fluxing agents on curing kinetics of this system is discussed. Material properties such as glass transition temperature (Tg), modulus, and viscosity were systematically characterized. Differential scanning calorimetry (DSC) dynamic-mechanical analysis (DMA), and rheometry were used for this study. In addition, promising assembly trial results, using small flip chips (PB8) and CSPs (TV46), are reported. Finally, the effects of the formulations and reflow profile on voiding and yield are also discussed.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116696080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008319
T.Y. Lin, K. Davison, W. Leong, S. Chua, J. S. Pan, J. Chai, K. Toh, W. C. Tjiu
The copper migration on the silver plated surface of the lead-frames with various heat treatments was evaluated by X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM) and atomic force microscopy (AFM) methodologies. The copper migration may introduce copper oxidation and result in the wedge bonding failures due to the non-stick on lead (NSOL). The experiment was performed on the two kinds of TQFP leadframes with the stamped and etched manufacturing processes. XPS results showed that the etched leadframe was the relatively better one in that less copper oxide was detected on silver surface after annealing process. However, more copper was clearly observed to diffuse onto the silver surface after annealing process in the stamped leadframe. In comparison between the stamped and etched lead-frames, the silver plated layer in latter more efficiently blocks the copper diffusion - either surface or bulk diffusion. In addition, TEM and AFM provided the additional insight of the grain structure and surface roughness measurement of silver.
{"title":"The evaluation of copper migration during the die attach curing and second wire bonding process","authors":"T.Y. Lin, K. Davison, W. Leong, S. Chua, J. S. Pan, J. Chai, K. Toh, W. C. Tjiu","doi":"10.1109/ECTC.2002.1008319","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008319","url":null,"abstract":"The copper migration on the silver plated surface of the lead-frames with various heat treatments was evaluated by X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM) and atomic force microscopy (AFM) methodologies. The copper migration may introduce copper oxidation and result in the wedge bonding failures due to the non-stick on lead (NSOL). The experiment was performed on the two kinds of TQFP leadframes with the stamped and etched manufacturing processes. XPS results showed that the etched leadframe was the relatively better one in that less copper oxide was detected on silver surface after annealing process. However, more copper was clearly observed to diffuse onto the silver surface after annealing process in the stamped leadframe. In comparison between the stamped and etched lead-frames, the silver plated layer in latter more efficiently blocks the copper diffusion - either surface or bulk diffusion. In addition, TEM and AFM provided the additional insight of the grain structure and surface roughness measurement of silver.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131510767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008152
Y. Kishida, Y. Kuba, R. Komeda, Takehiro Okumichi, Katsuhide Setoguchi, T. Matsubara
In an effort to provide a breakthrough in next-generation fiber optic data links, we are proposing a concept in optics and electronics (OE) integrated surface mount packaging technology. It can provide more compact and easier assembly of optoelectronics packaging. One assembly issue of surface mount packaging is being able to secure high bit rate transmission lines from board level to optics mount level as well as optical connectivity on the board. In this paper, we describe how a flat lead type surface mount package utilizing RF vias, which has broadband characteristics and provides high performance, low distortion of the pulse waveform, and low jitter, from active devices. For a demonstration, we evaluated actual EO modules using 2 mm length RF vias, enabling a receptacle such as an SC type to be attached. Measurement results of electrical/optical eye diagram tests were very close to the theoretical expectations. Therefore, we believe that the technology is a positive solution to develop downsizing and mass-productivity of optoelectronics packaging.
{"title":"Development of OE integrated surface mount packaging","authors":"Y. Kishida, Y. Kuba, R. Komeda, Takehiro Okumichi, Katsuhide Setoguchi, T. Matsubara","doi":"10.1109/ECTC.2002.1008152","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008152","url":null,"abstract":"In an effort to provide a breakthrough in next-generation fiber optic data links, we are proposing a concept in optics and electronics (OE) integrated surface mount packaging technology. It can provide more compact and easier assembly of optoelectronics packaging. One assembly issue of surface mount packaging is being able to secure high bit rate transmission lines from board level to optics mount level as well as optical connectivity on the board. In this paper, we describe how a flat lead type surface mount package utilizing RF vias, which has broadband characteristics and provides high performance, low distortion of the pulse waveform, and low jitter, from active devices. For a demonstration, we evaluated actual EO modules using 2 mm length RF vias, enabling a receptacle such as an SC type to be attached. Measurement results of electrical/optical eye diagram tests were very close to the theoretical expectations. Therefore, we believe that the technology is a positive solution to develop downsizing and mass-productivity of optoelectronics packaging.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128158653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008345
Sidharth, R. Blish, D. Natekar
Solder joint fatigue failure is a common failure mechanism in semiconductor packages mounted on boards. The thermal expansion mismatch between the package and the board causes cyclic loading on the solder joints during temperature cycling. It is therefore important to model the solder joint shape and standoff height accurately to estimate the reliability of a solder joint assembly. This paper discusses details of solder shape prediction using the Surface Evolver tool and its validation with experimental data. A comparison with truncated sphere model is also provided. A strategy for importing Surface Evolver data into a finite element based reliability evaluation is outlined.
{"title":"Solder joint shape and standoff height prediction and integration with FEA-based methodology for reliability evaluation","authors":"Sidharth, R. Blish, D. Natekar","doi":"10.1109/ECTC.2002.1008345","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008345","url":null,"abstract":"Solder joint fatigue failure is a common failure mechanism in semiconductor packages mounted on boards. The thermal expansion mismatch between the package and the board causes cyclic loading on the solder joints during temperature cycling. It is therefore important to model the solder joint shape and standoff height accurately to estimate the reliability of a solder joint assembly. This paper discusses details of solder shape prediction using the Surface Evolver tool and its validation with experimental data. A comparison with truncated sphere model is also provided. A strategy for importing Surface Evolver data into a finite element based reliability evaluation is outlined.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132145507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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