Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008344
K. Pandya, Klaus Pietrczak
This paper will address the shift from a 12-V to a 42-V system voltage in automobiles and its implications for applications using discrete components. The effects of rising voltage levels, such as higher power-handling requirements and side-by-side operation of 12-V and 42-V subsystems during the transition, will be discussed. This paper also will present basic definitions of the two Boardnet voltages, a comparison of the components and electrical characteristics required for each system, an analysis of the types of applications made possible with the higher voltages, and a description and schematics of similarly configured applications. A brief reference to current products that help to address the specific engineering issues accompanying these higher-voltage systems also will be included.
{"title":"Shifting from 12-V to 42-V systems in automotive applications","authors":"K. Pandya, Klaus Pietrczak","doi":"10.1109/ECTC.2002.1008344","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008344","url":null,"abstract":"This paper will address the shift from a 12-V to a 42-V system voltage in automobiles and its implications for applications using discrete components. The effects of rising voltage levels, such as higher power-handling requirements and side-by-side operation of 12-V and 42-V subsystems during the transition, will be discussed. This paper also will present basic definitions of the two Boardnet voltages, a comparison of the components and electrical characteristics required for each system, an analysis of the types of applications made possible with the higher voltages, and a description and schematics of similarly configured applications. A brief reference to current products that help to address the specific engineering issues accompanying these higher-voltage systems also will be included.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121928267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008095
A. Tay, H. Zhu
In this paper, the effects of thickness of the die (t/sub d/), die-pad (t/sub p/) and die attach (t/sub a/) on delaminations in Thin Shrink Small Outline Plastic IC packages were studied. The effects of t/sub d/ and t/sub p/ on Crack I, II and III are individually investigated where Crack I lies in the pad-encapsulant interface, Crack II in the die-encapsulant interface and Crack III in the pad-die attach interface. A fracture mechanics approach was used to compute the strain energy release rate (ERR) at the crack tips. For the die attach thickness t/sub a/, only its effect on Crack III was investigated. According to the literature, the Young's Modulus E of the die attach has a great influence on delamination along the pad-die attach interface. Thus a full factorial analysis of die attach thickness (t/sub a/) and Young's Modulus E on Crack III crack tip energy release rate was also carried out. Among other things, it was found that increasing the thickness of the die increases the ERR of cracks at all three interfaces and increasing the thickness of die pad increases the ERR of Crack I and II. It was also found that a smaller Young's Modulus and a greater thickness of the die attach is a good design against propagation of Crack III.
{"title":"A numerical study of the effect of die, die pad and die attach thicknesses on thin plastic packages","authors":"A. Tay, H. Zhu","doi":"10.1109/ECTC.2002.1008095","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008095","url":null,"abstract":"In this paper, the effects of thickness of the die (t/sub d/), die-pad (t/sub p/) and die attach (t/sub a/) on delaminations in Thin Shrink Small Outline Plastic IC packages were studied. The effects of t/sub d/ and t/sub p/ on Crack I, II and III are individually investigated where Crack I lies in the pad-encapsulant interface, Crack II in the die-encapsulant interface and Crack III in the pad-die attach interface. A fracture mechanics approach was used to compute the strain energy release rate (ERR) at the crack tips. For the die attach thickness t/sub a/, only its effect on Crack III was investigated. According to the literature, the Young's Modulus E of the die attach has a great influence on delamination along the pad-die attach interface. Thus a full factorial analysis of die attach thickness (t/sub a/) and Young's Modulus E on Crack III crack tip energy release rate was also carried out. Among other things, it was found that increasing the thickness of the die increases the ERR of cracks at all three interfaces and increasing the thickness of die pad increases the ERR of Crack I and II. It was also found that a smaller Young's Modulus and a greater thickness of the die attach is a good design against propagation of Crack III.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122212204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008301
B. Zahn
Three-dimensional finite element analysis has been applied to determine the time-dependent solder joint fatigue response of a tape based chip-scale package under accelerated temperature cycling conditions (-40C to +125C, 15min ramps/15min dwells). The effects of differing ball via configurations due to variations in both package assembly and tape vendors were investigated, including the use of punched, etched, laser etched, and enhanced re-flow pad area vias. The solder structures accommodate the bulk of the plastic strain that is generated during accelerated temperature cycling due to the thermal expansion mismatch between the various materials that encompass the chip-scale package. Since plastic strain is a dominant parameter that influences low-cycle fatigue, it was used as a basis for evaluation of solder joint structural integrity. An extensively published and correlated solder joint fatigue life prediction methodology was incorporated by which finite element simulation results were translated into estimated cycles to failure. This study discusses the analysis methodologies as implemented in the ANSYS finite element simulation software tool.
{"title":"Impact of ball via configurations on solder joint reliability in tape-based, chip-scale packages","authors":"B. Zahn","doi":"10.1109/ECTC.2002.1008301","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008301","url":null,"abstract":"Three-dimensional finite element analysis has been applied to determine the time-dependent solder joint fatigue response of a tape based chip-scale package under accelerated temperature cycling conditions (-40C to +125C, 15min ramps/15min dwells). The effects of differing ball via configurations due to variations in both package assembly and tape vendors were investigated, including the use of punched, etched, laser etched, and enhanced re-flow pad area vias. The solder structures accommodate the bulk of the plastic strain that is generated during accelerated temperature cycling due to the thermal expansion mismatch between the various materials that encompass the chip-scale package. Since plastic strain is a dominant parameter that influences low-cycle fatigue, it was used as a basis for evaluation of solder joint structural integrity. An extensively published and correlated solder joint fatigue life prediction methodology was incorporated by which finite element simulation results were translated into estimated cycles to failure. This study discusses the analysis methodologies as implemented in the ANSYS finite element simulation software tool.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128336505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008164
V. Sundaram, Fuhan Liu, S. Dalmia, J. Hobbs, E. Matoglu, M. Davis, T. Nonaka, J. Laskar, Madhavan Swaminathan, George E. White, Rao Tummala
The Packaging Research Center (PRC) is developing system-on-a-package (SOP) technology, as a complimentary alternative to SOC, as the fundamental building block for next generation convergent systems with computing, telecom and consumer capabilities with data and voice. Any systems of this nature have to provide not only high-speed digital, but also high bandwidth optical, analog, RF and perhaps MEMS functions. The SOP technology being pursued at PRC with embedded digital, optical and RF functions addresses this need, optimizing the IC and the package for functions, performance, cost, size and reliability. The PRC is developing this complimentary alternative to SOC using a three tier strategy consisting of fundamental research innovations, enabling technology developments and system-level testbeds. Individual digital, optical and RF testbeds have been developed to enable the integration of novel packaging technologies like embedded passive and optical components, high density global interconnections and wafer level flip-chip assembly. A phased system testbed is being evolved from these three testbeds to develop new SOP convergent system platforms for a digital/optical/RF system implementation. This paper summarizes the latest PRC accomplishments in the development of SOP baseline processes and system testbeds and updates the progress from basic research and technology integration to system testbeds for SOP.
{"title":"Digital and RF integration in system-on-a-package (SOP)","authors":"V. Sundaram, Fuhan Liu, S. Dalmia, J. Hobbs, E. Matoglu, M. Davis, T. Nonaka, J. Laskar, Madhavan Swaminathan, George E. White, Rao Tummala","doi":"10.1109/ECTC.2002.1008164","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008164","url":null,"abstract":"The Packaging Research Center (PRC) is developing system-on-a-package (SOP) technology, as a complimentary alternative to SOC, as the fundamental building block for next generation convergent systems with computing, telecom and consumer capabilities with data and voice. Any systems of this nature have to provide not only high-speed digital, but also high bandwidth optical, analog, RF and perhaps MEMS functions. The SOP technology being pursued at PRC with embedded digital, optical and RF functions addresses this need, optimizing the IC and the package for functions, performance, cost, size and reliability. The PRC is developing this complimentary alternative to SOC using a three tier strategy consisting of fundamental research innovations, enabling technology developments and system-level testbeds. Individual digital, optical and RF testbeds have been developed to enable the integration of novel packaging technologies like embedded passive and optical components, high density global interconnections and wafer level flip-chip assembly. A phased system testbed is being evolved from these three testbeds to develop new SOP convergent system platforms for a digital/optical/RF system implementation. This paper summarizes the latest PRC accomplishments in the development of SOP baseline processes and system testbeds and updates the progress from basic research and technology integration to system testbeds for SOP.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129489943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008229
L. Hwang, Li Li, J. Drye, S. Kuo
An RF switch made using MEMS (Micro Electro-Mechanical System) technology shows attractive electrical characteristics that are critically needed in the next generation low power consumption, high data rate RF wireless systems. In order to provide environmental protection and at the same time preserve electrical performance of the MEMS switch, an RF package must be carefully designed. For example, it is important for the RF package to maintain low insertion loss, low return loss, and high isolation between ports of the MEMS switches. In this paper, a methodology used to analyze: the electrical performance of packaged switches is described. Simulation results of two Kyocera ceramic packages are shown. Ansoft HFSS fullwave simulator was used to obtain the package and wire bond interconnect characteristics, and combined with either measured or simulated device characteristics. The results were compared with general system specifications. Wire bond profiles, which resemble those actually were used in the packages, were created in the simulation. The three-dimensional grounding system of the packages was also implemented in the simulation. Experimental validation using TRL on-board calibration and direct SOLT package probing were also completed.
{"title":"Performance evaluation of RF MEMS packages","authors":"L. Hwang, Li Li, J. Drye, S. Kuo","doi":"10.1109/ECTC.2002.1008229","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008229","url":null,"abstract":"An RF switch made using MEMS (Micro Electro-Mechanical System) technology shows attractive electrical characteristics that are critically needed in the next generation low power consumption, high data rate RF wireless systems. In order to provide environmental protection and at the same time preserve electrical performance of the MEMS switch, an RF package must be carefully designed. For example, it is important for the RF package to maintain low insertion loss, low return loss, and high isolation between ports of the MEMS switches. In this paper, a methodology used to analyze: the electrical performance of packaged switches is described. Simulation results of two Kyocera ceramic packages are shown. Ansoft HFSS fullwave simulator was used to obtain the package and wire bond interconnect characteristics, and combined with either measured or simulated device characteristics. The results were compared with general system specifications. Wire bond profiles, which resemble those actually were used in the packages, were created in the simulation. The three-dimensional grounding system of the packages was also implemented in the simulation. Experimental validation using TRL on-board calibration and direct SOLT package probing were also completed.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130554709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008290
Chunho Kim, D. Baldwin
No-flow underfill process has been widely accepted as a key technology to implement low-cost, high-throughput flip chip on board (FCOB) assembly because of the elimination of processing steps such as flux application, flux residue cleaning, capillary underfill flow and secondary thermal curing of the underfill. While feasibility tests for the low-cost, high-throughput flip chip assembly based on no-flow underfill over a wide range of flip chip configurations are underway, unfamiliar process defects that have not been observed in the conventional capillary flow process are newly emerging. Of those new process defects, "chip floating" over the board surface after chip placement process is a critical issue that may significantly impact process yield when process variables are not properly controlled. It was found that much of the yield losses observed post reflow is attributed to the "chip floating". In order to understand the underlying physics of the floating phenomena and predict process variables to eliminate the process defects, a process model has been. developed. The critical process variables include chip placement speed, chip placement force, dwell time, deposited underfill mass and underfill material properties such as viscosity, density, surface tension, wetting speed on the board, etc. A test chip and board was made such that chip floating over the board can be detected by testing the electric continuity of the path connecting the chip and board via the solder bumps. The effects of the critical process variables on the chip floating are investigated by a series of experiments and the results are compared to the theoretical model prediction for the model validation.
{"title":"No-flow underfill process modeling and analysis for low cost, high throughput flip chip assembly","authors":"Chunho Kim, D. Baldwin","doi":"10.1109/ECTC.2002.1008290","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008290","url":null,"abstract":"No-flow underfill process has been widely accepted as a key technology to implement low-cost, high-throughput flip chip on board (FCOB) assembly because of the elimination of processing steps such as flux application, flux residue cleaning, capillary underfill flow and secondary thermal curing of the underfill. While feasibility tests for the low-cost, high-throughput flip chip assembly based on no-flow underfill over a wide range of flip chip configurations are underway, unfamiliar process defects that have not been observed in the conventional capillary flow process are newly emerging. Of those new process defects, \"chip floating\" over the board surface after chip placement process is a critical issue that may significantly impact process yield when process variables are not properly controlled. It was found that much of the yield losses observed post reflow is attributed to the \"chip floating\". In order to understand the underlying physics of the floating phenomena and predict process variables to eliminate the process defects, a process model has been. developed. The critical process variables include chip placement speed, chip placement force, dwell time, deposited underfill mass and underfill material properties such as viscosity, density, surface tension, wetting speed on the board, etc. A test chip and board was made such that chip floating over the board can be detected by testing the electric continuity of the path connecting the chip and board via the solder bumps. The effects of the critical process variables on the chip floating are investigated by a series of experiments and the results are compared to the theoretical model prediction for the model validation.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129078143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008343
S. Pradhan, A. Mazloom, J. Arbulich, K. Srihari
An EDFA involves the use of Single Mode Fibers (SMFs) and Erbium Doped Fibers (EDFs). Studies have indicated that the splicing of an SMF to another SMF is less sensitive to fusion splicing parameters, if they are selected within an appropriate range. However, splicing of dissimilar fibers such as an SMF to an EDF poses a new set of requirements on the splicing specifications. Due to the variation in physical properties of the two fibers, the splice loss between them is much higher compared with that between SMF-SMF. The objective of this research endeavor was to develop a systematic procedure to minimize the losses between an EDF and an SMF. Relevant splicing parameters were identified through statistically designed experiments. Significant parameters were screened out and their interactions studied. The experimental results are discussed. Through this research effort, a systematic procedure for evaluating an EDF and identifying the parameters that could be used for a specific batch of fibers was developed. Guidelines for the characterization process are also discussed.
{"title":"Minimization of splice loss between a single mode fiber and an erbium doped fiber","authors":"S. Pradhan, A. Mazloom, J. Arbulich, K. Srihari","doi":"10.1109/ECTC.2002.1008343","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008343","url":null,"abstract":"An EDFA involves the use of Single Mode Fibers (SMFs) and Erbium Doped Fibers (EDFs). Studies have indicated that the splicing of an SMF to another SMF is less sensitive to fusion splicing parameters, if they are selected within an appropriate range. However, splicing of dissimilar fibers such as an SMF to an EDF poses a new set of requirements on the splicing specifications. Due to the variation in physical properties of the two fibers, the splice loss between them is much higher compared with that between SMF-SMF. The objective of this research endeavor was to develop a systematic procedure to minimize the losses between an EDF and an SMF. Relevant splicing parameters were identified through statistically designed experiments. Significant parameters were screened out and their interactions studied. The experimental results are discussed. Through this research effort, a systematic procedure for evaluating an EDF and identifying the parameters that could be used for a specific batch of fibers was developed. Guidelines for the characterization process are also discussed.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129123985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008172
D. Lochun, E. Zeira, R. Menize
We report a reel-to-reel manufacturing method for flexible electrical interconnects with copper conductivity that can be attained from a two-stage process of printing and electrolytic plating. This process can rapidly manufacture a range of patterns that can be applied to single sided circuitry including radio frequency identification structures. We disclose a method to print a material on a reel-to-reel printer that has sufficient conductivity to allow subsequent electrolytic plating on a reel-to-reel processing line and have sufficient ink/substrate adhesion to withstand the aggressiveness of the electrolytic plating chemistry, Depending on the printing technology chosen speeds of 150 feet per minute (fpm) to 300 fpm can be readily achieved. Judicious choice of image design will facilitate reel-to-reel electrolytic plating on a dedicated line. Electrolytic plating will occur only on connected lines and is therefore an additive technology eliminating the requirement for an etching step and so reducing the environmental impact of printed circuit manufacture.
{"title":"Reel-to-reel manufacturability of flexible electrical interconnects and radio-frequency identification structures","authors":"D. Lochun, E. Zeira, R. Menize","doi":"10.1109/ECTC.2002.1008172","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008172","url":null,"abstract":"We report a reel-to-reel manufacturing method for flexible electrical interconnects with copper conductivity that can be attained from a two-stage process of printing and electrolytic plating. This process can rapidly manufacture a range of patterns that can be applied to single sided circuitry including radio frequency identification structures. We disclose a method to print a material on a reel-to-reel printer that has sufficient conductivity to allow subsequent electrolytic plating on a reel-to-reel processing line and have sufficient ink/substrate adhesion to withstand the aggressiveness of the electrolytic plating chemistry, Depending on the printing technology chosen speeds of 150 feet per minute (fpm) to 300 fpm can be readily achieved. Judicious choice of image design will facilitate reel-to-reel electrolytic plating on a dedicated line. Electrolytic plating will occur only on connected lines and is therefore an additive technology eliminating the requirement for an etching step and so reducing the environmental impact of printed circuit manufacture.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"38-40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123640559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008271
M. Thurston, G. Raiser, D. Chiang, S. Tandon, M. Mello
A methodology for predicting the thermo-mechanical reliability of electronic packaging as a function of package design, material, and assembly process variables and environmental conditions is described. The methodology integrates finite element stress and strength analysis, experimental material constitutive and strength property measurement, experimental package stress and strength validation, and statistical design of experiment (DOE) and Monte Carlo analysis techniques. The results of extensive experimental and numerical evaluations demonstrating the stability and capability of the experimental and modeling techniques constituting the methodology are presented.
{"title":"Modeling methodology for predicting the thermo-mechanical reliability of electronic packaging","authors":"M. Thurston, G. Raiser, D. Chiang, S. Tandon, M. Mello","doi":"10.1109/ECTC.2002.1008271","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008271","url":null,"abstract":"A methodology for predicting the thermo-mechanical reliability of electronic packaging as a function of package design, material, and assembly process variables and environmental conditions is described. The methodology integrates finite element stress and strength analysis, experimental material constitutive and strength property measurement, experimental package stress and strength validation, and statistical design of experiment (DOE) and Monte Carlo analysis techniques. The results of extensive experimental and numerical evaluations demonstrating the stability and capability of the experimental and modeling techniques constituting the methodology are presented.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114333679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008306
P. Mccluskey
Today's product developers operate in a world of shortened design cycles in which quick time-to-market is essential. In such an environment, the luxury of improving reliability through multiple prototyping is a thing of the past. No longer is it possible to make a prototype, subject it to a series of standardized tests, analyze the failures, fix the design, and test again. Instead, new methods of reliability improvement have been developed that consider reliability up-front in the design cycle. Now the design can be analyzed and fixed before the first prototype is made. This new method of designing for reliability, however, requires a fundamental understanding of the chemical, electrical, mechanical, and thermo-mechanical mechanisms that cause failure of electronics.
{"title":"A web-based graduate course on design-for-reliability of electronic systems","authors":"P. Mccluskey","doi":"10.1109/ECTC.2002.1008306","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008306","url":null,"abstract":"Today's product developers operate in a world of shortened design cycles in which quick time-to-market is essential. In such an environment, the luxury of improving reliability through multiple prototyping is a thing of the past. No longer is it possible to make a prototype, subject it to a series of standardized tests, analyze the failures, fix the design, and test again. Instead, new methods of reliability improvement have been developed that consider reliability up-front in the design cycle. Now the design can be analyzed and fixed before the first prototype is made. This new method of designing for reliability, however, requires a fundamental understanding of the chemical, electrical, mechanical, and thermo-mechanical mechanisms that cause failure of electronics.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116272131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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